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This commit is contained in:
Bernhard Stoeckner
2024-03-19 16:56:28 +01:00
parent 12933b2d3c
commit 3bf16b890c
78 changed files with 1400 additions and 590 deletions
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3
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -348,6 +348,9 @@ namespace DisplayPort
//
bool bPowerDownPhyBeforeD3;
// Force DSC on sink irrespective of LT status
bool bForceDscOnSink;
//
// Reset the MSTM_CTRL registers on branch device irrespective of
// IRQ VECTOR register having stale message. Certain branch devices

4
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -294,8 +294,8 @@ namespace DisplayPort
else
{
// if FEC is not enabled, link overhead comprises only of
// 0.05% downspread.
return rate - 5 * rate/ 1000;
// 0.6% downspread.
return rate - 6 * rate/ 1000;
}
}

6
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -79,6 +79,11 @@
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
//
// Bug 4459839 : This regkey will enable DSC irrespective of LT status.
//
#define NV_DP_REGKEY_FORCE_DSC_ON_SINK "DP_FORCE_DSC_ON_SINK"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -113,6 +118,7 @@ struct DP_REGKEY_DATABASE
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
bool bMSTPCONCapsReadDisabled;
bool bForceDscOnSink;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

35
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -174,6 +174,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
this->bForceDscOnSink = dpRegkeyDatabase.bForceDscOnSink;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -3129,7 +3130,7 @@ bool ConnectorImpl::notifyAttachBegin(Group * target, // Gr
// if LT is successful, see if panel supports DSC and if so, set DSC enabled/disabled
// according to the mode requested.
if(bLinkTrainingStatus)
if(bLinkTrainingStatus || bForceDscOnSink)
{
for (Device * dev = target->enumDevices(0); dev; dev = target->enumDevices(dev))
{
@@ -4631,6 +4632,11 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
}
}
//
// There is no point in fallback here since we are link training
// to loweset link config that can support the mode.
//
lowestSelected.policy.setSkipFallBack(true);
bLinkTrainingSuccessful = train(lowestSelected, false);
//
// If LT failed, check if skipLT was marked. If so, clear the flag and
@@ -4648,16 +4654,37 @@ bool ConnectorImpl::trainLinkOptimized(LinkConfiguration lConfig)
}
if (!bLinkTrainingSuccessful)
{
// Try fall back to max link config and if that fails try original assessed link configuration
// If optimized link config fails, try max link config with fallback.
if (!train(getMaxLinkConfig(), false))
{
//
// Note here that if highest link config fails and a lower
// link config passes, link training will be returned as
// failure but activeLinkConfig will be set to that passing config.
//
if (!willLinkSupportModeSST(activeLinkConfig, groupAttached->lastModesetInfo))
{
//
// If none of the link configs pass LT or a fall back link config passed LT
// but cannot support the mode, then we will force the optimized link config
// on the link and mark LT as fail.
//
train(lowestSelected, true);
// Mark link training as failed since we forced it
bLinkTrainingSuccessful = false;
}
else
{
//
// If a fallback link config pass LT and can support
// the mode, mark LT as pass.
//
bLinkTrainingSuccessful = true;
}
}
else
{
// If LT passes at max link config, mark LT as pass.
bLinkTrainingSuccessful = true;
}
}
}

3
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -94,7 +94,8 @@ const struct
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_DSC_ON_SINK, &dpRegkeyDatabase.bForceDscOnSink, DP_REG_VAL_BOOL},
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r551_40
#define NV_BUILD_BRANCH r550_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r551_40
#define NV_PUBLIC_BRANCH r550_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_40-171"
#define NV_BUILD_CHANGELIST_NUM (33992326)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-204"
#define NV_BUILD_CHANGELIST_NUM (34025356)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_40-171"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992326)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-204"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34025356)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r551_40-15"
#define NV_BUILD_CHANGELIST_NUM (33992326)
#define NV_BUILD_BRANCH_VERSION "r550_00-192"
#define NV_BUILD_CHANGELIST_NUM (34025356)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "551.78"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33992326)
#define NV_BUILD_NAME "551.86"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34025356)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.54.15"
#define NV_VERSION_STRING "550.67"
#else

5
src/common/modeset/timing/nvt_edid.c
View File

@@ -2388,7 +2388,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
if (parseCta861DataBlockInfo(pData_collection, (NvU32)ctaDTD_Offset - 4, NULL) == NVT_STATUS_SUCCESS)
{
pData_collection++;
pData_collection++; // go to the next byte. skip Tag+Length byte
if (ctaBlockTag == NVT_CEA861_TAG_VIDEO)
{
for (i=0; i < ctaPayload; i++)
@@ -2432,6 +2433,8 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
}
else
{
pData_collection++; // go to the next byte. skip Tag+Length byte
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_INVALID_DATA_BLOCK);
pData_collection += ctaPayload;
}

34
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -1609,7 +1609,6 @@ void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo)
CODE_SEGMENT(PAGE_DD_CODE)
NVT_STATUS get861ExtInfo(NvU8 *p, NvU32 size, NVT_EDID_CEA861_INFO *p861info)
{
NvU32 dtd_offset;
// sanity check
if (p == NULL || size < sizeof(EDIDV1STRUC))
@@ -1725,8 +1724,8 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
if (payload >= 1)
{
ext_tag = p[i];
if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_CAP && payload < 2) return NVT_STATUS_ERR;
else if (ext_tag == NVT_CEA861_EXT_TAG_COLORIMETRY && payload < 3) return NVT_STATUS_ERR;
if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_CAP && (payload != 2)) return NVT_STATUS_ERR;
else if (ext_tag == NVT_CEA861_EXT_TAG_COLORIMETRY && payload != 3) return NVT_STATUS_ERR;
else if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE && payload < 2) return NVT_STATUS_ERR;
else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_VIDEO && payload < 2) return NVT_STATUS_ERR;
else if (ext_tag == NVT_CEA861_EXT_TAG_YCBCR420_CAP && payload < 1) return NVT_STATUS_ERR;
@@ -1856,19 +1855,22 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
}
else if (tag == NVT_CTA861_TAG_VIDEO_FORMAT)
{
p861info->vfdb[vfd_index].info.vfd_len = p[i] & 0x03;
p861info->vfdb[vfd_index].info.ntsc = (p[i] & 0x40) >> 6;
p861info->vfdb[vfd_index].info.y420 = (p[i] & 0x80) >> 7;
p861info->vfdb[vfd_index].total_vfd = (NvU8)(payload - 1) / (p861info->vfdb[vfd_index].info.vfd_len + 1);
i++; payload--;
for (j = 0; j < payload; j++, i++)
if (payload > 0)
{
p861info->vfdb[vfd_index].video_format_desc[j] = p[i];
}
p861info->vfdb[vfd_index].info.vfd_len = p[i] & 0x03;
p861info->vfdb[vfd_index].info.ntsc = (p[i] & 0x40) >> 6;
p861info->vfdb[vfd_index].info.y420 = (p[i] & 0x80) >> 7;
p861info->vfdb[vfd_index].total_vfd = (NvU8)(payload - 1) / (p861info->vfdb[vfd_index].info.vfd_len + 1);
p861info->total_vfdb = ++vfd_index;
i++; payload--;
for (j = 0; (j < payload) && (p861info->vfdb[vfd_index].total_vfd != 0); j++, i++)
{
p861info->vfdb[vfd_index].video_format_desc[j] = p[i];
}
p861info->total_vfdb = ++vfd_index;
}
}
else if (tag == NVT_CEA861_TAG_EXTENDED_FLAG)
{
@@ -1879,14 +1881,14 @@ NVT_STATUS parseCta861DataBlockInfo(NvU8 *p,
{
p861info->video_capability = p[i + 1] & NVT_CEA861_VIDEO_CAPABILITY_MASK;
p861info->valid.VCDB = 1;
i += 2;
i += payload;
}
else if (ext_tag == NVT_CEA861_EXT_TAG_COLORIMETRY && payload >= 3)
{
p861info->colorimetry.byte1 = p[i + 1] & NVT_CEA861_COLORIMETRY_MASK;
p861info->colorimetry.byte2 = p[i + 2] & NVT_CEA861_GAMUT_METADATA_MASK;
p861info->valid.colorimetry = 1;
i += 3;
i += payload;
}
else if (ext_tag == NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE && payload >= 2)
{

3
src/common/nvlink/inband/interface/nvlink_inband_msg.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -80,6 +80,7 @@ typedef struct
#define NVLINK_INBAND_GPU_PROBE_CAPS_SRIOV_ENABLED NVBIT(0)
#define NVLINK_INBAND_GPU_PROBE_CAPS_PROBE_UPDATE NVBIT(1)
#define NVLINK_INBAND_GPU_PROBE_CAPS_EGM_SUPPORT NVBIT(2)
/* Add more caps as need in the future */

16
src/common/nvlink/kernel/nvlink/interface/nvlink_kern_shutdown_entry.c
View File

@@ -378,6 +378,21 @@ nvlink_lib_powerdown_links_from_active_to_off
lockLinkCount++;
}
if (lockLinkCount == 0)
{
if (conns != NULL)
nvlink_free((void *)conns);
if (lockLinks != NULL)
nvlink_free((void *)lockLinks);
// Release the top-level lock
nvlink_lib_top_lock_release();
NVLINK_PRINT((DBG_MODULE_NVLINK_CORE, NVLINK_DBG_LEVEL_ERRORS,
"%s: No conns were found\n", __FUNCTION__));
return NVL_NOT_FOUND;
}
// Acquire the per-link locks for all links captured
status = nvlink_lib_link_locks_acquire(lockLinks, lockLinkCount);
if (status != NVL_SUCCESS)
@@ -923,4 +938,3 @@ nvlink_core_powerdown_floorswept_conns_to_off_end:
return status;
}

2
src/common/nvswitch/kernel/inc/boards_nvswitch.h
View File

@@ -38,6 +38,7 @@
#define NVSWITCH_BOARD_LS10_5612_0002_ES 0x03D6
#define NVSWITCH_BOARD_LS10_4697_0000_895 0x03B9
#define NVSWITCH_BOARD_LS10_4262_0000_895 0x04FE
#define NVSWITCH_BOARD_LS10_4300_0000_895 0x0571
#define NVSWITCH_BOARD_UNKNOWN_NAME "UNKNOWN"
@@ -48,5 +49,6 @@
#define NVSWITCH_BOARD_LS10_5612_0002_ES_NAME "LS10_5612_0002_ES"
#define NVSWITCH_BOARD_LS10_4697_0000_895_NAME "LS10_4697_0000_895"
#define NVSWITCH_BOARD_LS10_4262_0000_895_NAME "LS10_4262_0000_895"
#define NVSWITCH_BOARD_LS10_4300_0000_895_NAME "LS10_4300_0000_895"
#endif // _BOARDS_NVSWITCH_H_

12
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -894,9 +894,9 @@ _nvswitch_collect_error_info_ls10
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_ROUTE_HDR;
NVSWITCH_PRINT(device, INFO,
"ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-8], data->data[i-7], data->data[i-6], data->data[i-5],
data->data[i-4], data->data[i-3], data->data[i-2], data->data[i-1]);
"ROUTE: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4],
data->data[i-3], data->data[i-2], data->data[i-1]);
}
}
}
@@ -940,9 +940,9 @@ _nvswitch_collect_error_info_ls10
{
data->flags |= NVSWITCH_RAW_ERROR_LOG_DATA_FLAG_INGRESS_HDR;
NVSWITCH_PRINT(device, INFO,
"INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-7], data->data[i-6], data->data[i-5], data->data[i-4],
data->data[i-3], data->data[i-2], data->data[i-1]);
"INGRESS: HEADER: 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x, 0x%08x,\n",
data->data[i-6], data->data[i-5], data->data[i-4], data->data[i-3],
data->data[i-2], data->data[i-1]);
}
}
}

27
src/common/nvswitch/kernel/ls10/pmgr_ls10.c
View File

@@ -32,6 +32,7 @@
#include "export_nvswitch.h"
#include "soe/soe_nvswitch.h"
#include "soe/soeifcore.h"
#include "boards_nvswitch.h"
#include "nvswitch/ls10/dev_pmgr.h"
@@ -176,6 +177,16 @@ static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_Default[] =
static const NvU32 nvswitch_gpio_pin_Default_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_Default);
static const NVSWITCH_GPIO_INFO nvswitch_gpio_pin_4300[] =
{
NVSWITCH_DESCRIBE_GPIO_PIN( 0, _INSTANCE_ID0, 0, IN), // Instance ID bit 0
NVSWITCH_DESCRIBE_GPIO_PIN( 1, _INSTANCE_ID1, 0, IN), // Instance ID bit 1
NVSWITCH_DESCRIBE_GPIO_PIN( 2, _INSTANCE_ID2, 0, IN), // Instance ID bit 2
NVSWITCH_DESCRIBE_GPIO_PIN( 6, _INSTANCE_ID3, 0, IN), // Instance ID bit 3
NVSWITCH_DESCRIBE_GPIO_PIN( 7, _INSTANCE_ID4, 0, IN), // Instance ID bit 4
};
static const NvU32 nvswitch_gpio_pin_4300_size = NV_ARRAY_ELEMENTS(nvswitch_gpio_pin_4300);
//
// Initialize the software state of the switch I2C & GPIO interface
// Temporarily forcing default GPIO values.
@@ -191,6 +202,8 @@ nvswitch_init_pmgr_devices_ls10
{
ls10_device *chip_device = NVSWITCH_GET_CHIP_DEVICE_LS10(device);
PNVSWITCH_OBJI2C pI2c = device->pI2c;
NvlStatus retval;
NvU16 boardId;
if (IS_FMODEL(device) || IS_EMULATION(device) || IS_RTLSIM(device))
{
@@ -200,8 +213,18 @@ nvswitch_init_pmgr_devices_ls10
}
else
{
chip_device->gpio_pin = nvswitch_gpio_pin_Default;
chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size;
retval = nvswitch_get_board_id(device, &boardId);
if (retval == NVL_SUCCESS &&
boardId == NVSWITCH_BOARD_LS10_4300_0000_895)
{
chip_device->gpio_pin = nvswitch_gpio_pin_4300;
chip_device->gpio_pin_size = nvswitch_gpio_pin_4300_size;
}
else
{
chip_device->gpio_pin = nvswitch_gpio_pin_Default;
chip_device->gpio_pin_size = nvswitch_gpio_pin_Default_size;
}
}
pI2c->device_list = NULL;

2
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -62,7 +62,7 @@ static NvlStatus _nvswitch_ctrl_inband_flush_data(nvswitch_device *device, NVSWI
#define NVSWITCH_DEV_CMD_DISPATCH_RESERVED(cmd) \
case cmd: \
{ \
retval = -NVL_ERR_NOT_IMPLEMENTED; \
retval = -NVL_ERR_NOT_SUPPORTED; \
break; \
} \

1
src/nvidia-modeset/Makefile
View File

@@ -95,6 +95,7 @@ endif
ifeq ($(TARGET_ARCH),aarch64)
CFLAGS += -mgeneral-regs-only
CFLAGS += -march=armv8-a
CFLAGS += -ffixed-x18
CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
endif

1
src/nvidia/Makefile
View File

@@ -90,6 +90,7 @@ ifeq ($(TARGET_ARCH),aarch64)
CFLAGS += -mgeneral-regs-only
CFLAGS += -march=armv8-a
CFLAGS += -mstrict-align
CFLAGS += -ffixed-x18
CONDITIONAL_CFLAGS += $(call TEST_CC_ARG, -mno-outline-atomics)
endif

16
src/nvidia/arch/nvalloc/unix/src/os-hypervisor.c
View File

@@ -74,7 +74,7 @@ NV_STATUS hypervisorInjectInterrupt_IMPL
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
if (pVgpuNsIntr->pVgpuVfioRef)
status = osVgpuInjectInterrupt(pVgpuNsIntr->pVgpuVfioRef);
return NV_ERR_NOT_SUPPORTED;
else
{
if (pVgpuNsIntr->guestMSIAddr && pVgpuNsIntr->guestMSIData)
@@ -142,14 +142,22 @@ static NV_STATUS get_available_instances(
swizzIdInUseMask = kmigmgrGetSwizzIdInUseMask(pGpu, pKernelMIGManager);
if (!vgpuTypeInfo->gpuInstanceSize)
{
// Query for a non MIG vgpuType
NV_PRINTF(LEVEL_INFO, "%s Query for a non MIG vGPU type \n",
__FUNCTION__);
rmStatus = NV_OK;
goto exit;
}
rmStatus = kvgpumgrGetPartitionFlag(vgpuTypeInfo->vgpuTypeId,
&partitionFlag);
if (rmStatus != NV_OK)
{
// Query for a non MIG vgpuType
NV_PRINTF(LEVEL_ERROR, "%s Query for a non MIG vGPU type \n",
NV_PRINTF(LEVEL_ERROR, "%s failed to get partition flags.\n",
__FUNCTION__);
rmStatus = NV_OK;
goto exit;
}
@@ -192,7 +200,7 @@ static NV_STATUS get_available_instances(
if (vgpuTypeInfo->gpuInstanceSize)
{
// Query for a MIG vgpuType
NV_PRINTF(LEVEL_ERROR, "%s Query for a MIG vGPU type \n",
NV_PRINTF(LEVEL_INFO, "%s Query for a MIG vGPU type \n",
__FUNCTION__);
rmStatus = NV_OK;
goto exit;

1
src/nvidia/generated/g_gpu_nvoc.h
View File

@@ -1255,6 +1255,7 @@ struct OBJGPU {
TMR_EVENT *pVideoTimerEvent;
NVENC_SESSION_LIST nvencSessionList;
NvU32 encSessionStatsReportingState;
NvBool bNvEncSessionDataProcessingWorkItemPending;
NVFBC_SESSION_LIST nvfbcSessionList;
struct OBJVASPACE *pFabricVAS;
NvBool bPipelinedPteMemEnabled;

3
src/nvidia/generated/g_nv_name_released.h
View File

@@ -1014,6 +1014,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2702, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 SUPER" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2705, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti SUPER" },
{ 0x2709, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" },
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2730, 0x0000, 0x0000, "NVIDIA RTX 5000 Ada Generation Laptop GPU" },
{ 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
@@ -1021,6 +1022,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x2783, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 SUPER" },
{ 0x2786, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070" },
{ 0x2788, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" },
{ 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" },
@@ -1043,6 +1045,7 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x27FB, 0x0000, 0x0000, "NVIDIA RTX 3500 Ada Generation Embedded GPU" },
{ 0x2803, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" },
{ 0x2805, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060 Ti" },
{ 0x2808, 0x0000, 0x0000, "NVIDIA GeForce RTX 4060" },
{ 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2838, 0x0000, 0x0000, "NVIDIA RTX 3000 Ada Generation Laptop GPU" },
{ 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },

5
src/nvidia/generated/g_spdm_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -108,6 +108,9 @@ struct Spdm {
NvU32 sessionMsgCount;
PTMR_EVENT pHeartbeatEvent;
NvU32 heartbeatPeriodSec;
NvU8 *pTransportBuffer;
NvU32 transportBufferSize;
NvU32 pendingResponseSize;
};
#ifndef __NVOC_CLASS_Spdm_TYPEDEF__

2
src/nvidia/generated/g_vgpuconfigapi_nvoc.h
View File

@@ -7,7 +7,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

20
src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h
View File

@@ -103,4 +103,24 @@ typedef struct MESSAGE_QUEUE_COLLECTION
#define GSP_MSG_QUEUE_HEADER_SIZE RM_PAGE_SIZE
#define GSP_MSG_QUEUE_HEADER_ALIGN 4 // 2 ^ 4 = 16
/*!
* Calculate 32-bit checksum
*
* This routine assumes that the data is padded out with zeros to the next
* 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
*/
static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
{
NvU64 *p = (NvU64 *)pData;
NvU64 *pEnd = (NvU64 *)((NvUPtr)pData + uLen);
NvU64 checkSum = 0;
NV_ASSERT_CHECKED(uLen > 0);
while (p < pEnd)
checkSum ^= *p++;
return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
}
#endif // _MESSAGE_QUEUE_PRIV_H_

7
src/nvidia/src/kernel/gpu/bif/arch/maxwell/kernel_bif_gm107.c
View File

@@ -585,6 +585,13 @@ kbifRestorePcieConfigRegisters_GM107
NvU64 timeStampStart;
NvU64 timeStampEnd;
if (pKernelBif->xveRegmapRef[0].bufBootConfigSpace == NULL)
{
NV_PRINTF(LEVEL_ERROR, "Config space buffer is NULL!\n");
NV_ASSERT(0);
return NV_ERR_OBJECT_NOT_FOUND;
}
// Restore pcie config space for function 0
status = _kbifRestorePcieConfigRegisters_GM107(pGpu, pKernelBif,
&pKernelBif->xveRegmapRef[0]);

2
src/nvidia/src/kernel/gpu/device.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

40
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -259,32 +259,50 @@ kfspPollForQueueEmpty_IMPL
KernelFsp *pKernelFsp
)
{
NV_STATUS status = NV_OK;
RMTIMEOUT timeout;
gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout, GPU_TIMEOUT_FLAGS_OSTIMER | GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
gpuSetTimeout(pGpu, GPU_TIMEOUT_DEFAULT, &timeout,
GPU_TIMEOUT_FLAGS_OSTIMER |
GPU_TIMEOUT_FLAGS_BYPASS_THREAD_STATE);
while (!kfspIsQueueEmpty(pGpu, pKernelFsp))
{
//
// For now we assume that any response from FSP before RM message send is complete
// indicates an error and we should abort.
// For now we assume that any response from FSP before RM message
// send is complete indicates an error and we should abort.
//
// Ongoing dicussion on usefullness of this check. Bug to be filed.
//
if (!kfspIsMsgQueueEmpty(pGpu, pKernelFsp))
{
kfspReadMessage(pGpu, pKernelFsp, NULL, 0);
NV_PRINTF(LEVEL_ERROR, "Received error message from FSP while waiting for CMDQ to be empty.\n");
return NV_ERR_GENERIC;
NV_PRINTF(LEVEL_ERROR,
"Received error message from FSP while waiting for CMDQ to be empty.\n");
status = NV_ERR_GENERIC;
break;
}
if (gpuCheckTimeout(pGpu, &timeout) == NV_ERR_TIMEOUT)
{
NV_PRINTF(LEVEL_ERROR, "Timed out waiting for FSP command queue to be empty.\n");
return NV_ERR_TIMEOUT;
}
osSpinLoop();
status = gpuCheckTimeout(pGpu, &timeout);
if (status != NV_OK)
{
if ((status == NV_ERR_TIMEOUT) &&
kfspIsQueueEmpty(pGpu, pKernelFsp))
{
status = NV_OK;
}
else
{
NV_PRINTF(LEVEL_ERROR,
"Timed out waiting for FSP command queue to be empty.\n");
}
break;
}
}
return NV_OK;
return status;
}
/*!

8
src/nvidia/src/kernel/gpu/gsp/kernel_gsp.c
View File

@@ -846,6 +846,14 @@ _kgspRpcEventIsGpuDegradedCallback
OBJRPC *pRpc
)
{
RPC_PARAMS(nvlink_is_gpu_degraded, _v17_00);
KernelNvlink *pKernelNvlink = GPU_GET_KERNEL_NVLINK(pGpu);
NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_v17_00 *dest = &rpc_params->params;
if(dest->bIsGpuDegraded)
{
knvlinkSetDegradedMode(pGpu, pKernelNvlink, dest->linkId);
}
}
static void

47
src/nvidia/src/kernel/gpu/gsp/message_queue_cpu.c
View File

@@ -476,24 +476,6 @@ void GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection)
*ppMQCollection = NULL;
}
/*!
* Calculate 32-bit checksum
*
* This routine assumes that the data is padded out with zeros to the next
* 8-byte alignment, and it is OK to read past the end to the 8-byte alignment.
*/
static NV_INLINE NvU32 _checkSum32(void *pData, NvU32 uLen)
{
NvU64 *p = (NvU64 *)pData;
NvU64 *pEnd = (NvU64 *)((NvUPtr)pData + uLen);
NvU64 checkSum = 0;
while (p < pEnd)
checkSum ^= *p++;
return NvU64_HI32(checkSum) ^ NvU64_LO32(checkSum);
}
/*!
* GspMsgQueueSendCommand
*
@@ -532,7 +514,7 @@ NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
pCQE->seqNum = pMQI->txSeqNum;
pCQE->elemCount = GSP_MSG_QUEUE_BYTES_TO_ELEMENTS(uElementSize);
pCQE->checkSum = 0;
pCQE->checkSum = 0; // The checkSum field is included in the checksum calculation, so zero it.
if (gpuIsCCFeatureEnabled(pGpu))
{
@@ -666,7 +648,8 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
NvU32 nRetries;
NvU32 nMaxRetries = 3;
NvU32 nElements = 1; // Assume record fits in one queue element for now.
NvU32 uElementSize = 0;
NvU32 uElementSize;
NvU32 checkSum;
NvU32 seqMismatchDiff = NV_U32_MAX;
NV_STATUS nvStatus = NV_OK;
@@ -717,15 +700,23 @@ NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu)
// Retry if checksum fails.
if (gpuIsCCFeatureEnabled(pGpu))
{
// In Confidential Compute scenario, checksum includes complete element range.
if (_checkSum32(pMQI->pCmdQueueElement, (nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN)) != 0)
{
NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
nvStatus = NV_ERR_INVALID_DATA;
continue;
}
//
// In the Confidential Compute scenario, the actual message length
// is inside the encrypted payload, and we can't access it before
// decryption, therefore the checksum encompasses the whole element
// range. This makes checksum verification significantly slower
// because messages are typically much smaller than element size.
//
checkSum = _checkSum32(pMQI->pCmdQueueElement,
(nElements * GSP_MSG_QUEUE_ELEMENT_SIZE_MIN));
} else
if (_checkSum32(pMQI->pCmdQueueElement, uElementSize) != 0)
{
checkSum = _checkSum32(pMQI->pCmdQueueElement,
(GSP_MSG_QUEUE_ELEMENT_HDR_SIZE +
pMQI->pCmdQueueElement->rpc.length));
}
if (checkSum != 0)
{
NV_PRINTF(LEVEL_ERROR, "Bad checksum.\n");
nvStatus = NV_ERR_INVALID_DATA;

2
src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

11
src/nvidia/src/kernel/gpu/mem_sys/kern_mem_sys_ctrl.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -475,11 +475,14 @@ _kmemsysGetFbInfos
// It will be zero unless VGA display memory is reserved
if (pKernelMemorySystem->fbOverrideStartKb != 0)
{
status = NV_OK;
data = NvU64_LO32(pKernelMemorySystem->fbOverrideStartKb);
NV_ASSERT(((NvU64) data << 10ULL) == pKernelMemorySystem->fbOverrideStartKb);
NV_ASSERT_OR_ELSE((NvU64) data == pKernelMemorySystem->fbOverrideStartKb,
status = NV_ERR_INVALID_DATA);
}
else
{
else
{
//
// Returns start of heap in kbytes. This is zero unless
// VGA display memory is reserved.

49
src/nvidia/src/kernel/gpu/nvenc/nvencsession.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2012-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -159,6 +159,7 @@ nvencsessionConstruct_IMPL
(listCount(&(pGpu->nvencSessionList)) == 1))
{
// Register 1Hz timer callback for this GPU.
pGpu->bNvEncSessionDataProcessingWorkItemPending = NV_FALSE;
status = osSchedule1HzCallback(pGpu,
_gpuNvEncSessionDataProcessingCallback,
NULL,
@@ -379,8 +380,7 @@ _gpuNvEncSessionProcessBuffer(POBJGPU pGpu, NvencSession *pNvencSession)
portMemFree(pLocalSessionInfoBuffer);
}
static void
_gpuNvEncSessionDataProcessingCallback(POBJGPU pGpu, void *data)
static void _gpuNvEncSessionDataProcessing(OBJGPU *pGpu)
{
PNVENC_SESSION_LIST_ITEM pNvencSessionListItem;
PNVENC_SESSION_LIST_ITEM pNvencSessionListItemNext;
@@ -416,3 +416,46 @@ _gpuNvEncSessionDataProcessingCallback(POBJGPU pGpu, void *data)
}
}
}
static void _gpuNvEncSessionDataProcessingWorkItem(NvU32 gpuInstance, void *pArgs)
{
OBJGPU *pGpu;
pGpu = gpumgrGetGpu(gpuInstance);
if (pGpu == NULL)
{
NV_PRINTF(LEVEL_ERROR, "NVENC Sessions GPU instance is invalid\n");
return;
}
_gpuNvEncSessionDataProcessing(pGpu);
pGpu->bNvEncSessionDataProcessingWorkItemPending = NV_FALSE;
}
static void
_gpuNvEncSessionDataProcessingCallback(POBJGPU pGpu, void *data)
{
NV_STATUS status;
if (!pGpu->bNvEncSessionDataProcessingWorkItemPending)
{
status = osQueueWorkItemWithFlags(pGpu,
_gpuNvEncSessionDataProcessingWorkItem,
NULL,
OS_QUEUE_WORKITEM_FLAGS_LOCK_SEMA
| OS_QUEUE_WORKITEM_FLAGS_LOCK_GPU_GROUP_DEVICE_RW);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR,
"NVENC session queuing async callback failed, status=%x\n",
status);
// Call directly to do NVENC session data processing
_gpuNvEncSessionDataProcessing(pGpu);
}
else
{
pGpu->bNvEncSessionDataProcessingWorkItemPending = NV_TRUE;
}
}
}

19
src/nvidia/src/kernel/gpu/nvlink/kernel_nvlinkcorelibtrain.c
View File

@@ -1034,6 +1034,7 @@ knvlinkCoreShutdownDeviceLinks_IMPL
OBJSYS *pSys = SYS_GET_INSTANCE();
NvU32 count = 0;
NvU32 linkId;
NvlStatus status = NV_OK;
// Skip link shutdown where fabric manager is present, for nvlink version bellow 4.0
if ((pKernelNvlink->ipVerNvlink < NVLINK_VERSION_40 &&
@@ -1096,13 +1097,23 @@ knvlinkCoreShutdownDeviceLinks_IMPL
// Trigger laneshutdown through core lib if shutdown is supported
if (pKernelNvlink->getProperty(pKernelNvlink, PDB_PROP_KNVLINK_LANE_SHUTDOWN_ENABLED) && (count > 0))
{
if (nvlink_lib_powerdown_links_from_active_to_off(
pLinks, count, NVLINK_STATE_CHANGE_SYNC))
status = nvlink_lib_powerdown_links_from_active_to_off(
pLinks, count, NVLINK_STATE_CHANGE_SYNC);
if (status != NVL_SUCCESS)
{
NV_PRINTF(LEVEL_ERROR, "Unable to turn off links for the GPU%d\n",
if (status == NVL_NOT_FOUND)
{
// Bug 4419022
NV_PRINTF(LEVEL_ERROR, "Need to shutdown all links unilaterally for GPU%d\n",
pGpu->gpuInstance);
}
else
{
NV_PRINTF(LEVEL_ERROR, "Unable to turn off links for the GPU%d\n",
pGpu->gpuInstance);
return NV_ERR_INVALID_STATE;
return NV_ERR_INVALID_STATE;
}
}
}

159
src/nvidia/src/kernel/gpu/spdm/arch/hopper/spdm_gh100.c
View File

@@ -51,6 +51,14 @@
// Regardless of whether Requester is configured to support these,
// we only expect Responder to provide these capabilities.
//
//
// TODO: SPDM_CAPABILITIES_FLAGS_GH100 and g_SpdmAlgoCheckTable_GH100 is expected capabilities flags
// and attributions what GH100 receive from responder. Currently, we have only 1 responder
// and return fixed capabilities flags and attributions.
// If we want to support different return capabilitis and attributions afterwards, we need
// to refactor spdmCheckConnection_GH100().
//
#define SPDM_CAPABILITIES_FLAGS_GH100 \
SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_CERT_CAP | \
SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_MEAS_CAP_SIG | \
@@ -64,21 +72,6 @@
SPDM_GET_CAPABILITIES_RESPONSE_FLAGS_HBEAT_CAP;
/* ------------------------ Static Variables ------------------------------- */
//
// For transport functionality, we require access to the GPU and Spdm objects,
// as well as additional state (temporary response buffer).
//
// However, libspdm transport layer is implemented via callbacks which currently
// do not support passing any custom parameters, meaning we must use static variables
// to access these objects. If we ever require multiple instances of the Spdm object,
// this will be an issue.
//
static OBJGPU *g_pGpu = NULL;
static Spdm *g_pSpdm = NULL;
static NvU8 *g_pTransportBuffer = NULL;
static NvU32 g_transportBufferSize = 0;
static NvU32 g_pendingResponseSize = 0;
static SPDM_ALGO_CHECK_ENTRY g_SpdmAlgoCheckTable_GH100[] =
{
{ LIBSPDM_DATA_MEASUREMENT_SPEC, SPDM_MEASUREMENT_SPECIFICATION_DMTF },
@@ -127,7 +120,6 @@ static libspdm_return_t _spdmSendMessageGsp(void *spdm_context, size_t message_s
static libspdm_return_t _spdmReceiveMessageGsp(void *spdm_context, size_t *message_size,
void **message, uint64_t timeout);
/* ------------------------ Static Functions ------------------------------- */
//
// Hardcoding check for libspdm secured message callbacks version.
@@ -311,6 +303,8 @@ _spdmEncodeMessageGsp
void *pSecuredMessageContext = NULL;
NV_SPDM_DESC_HEADER *pNvSpdmDescHdr = NULL;
NvU32 payloadSize = 0;
Spdm *pSpdm = NULL;
size_t dataSize = sizeof(void *);
// Check libspdm parameters.
if (spdm_context == NULL || message == NULL || message_size == 0 ||
@@ -332,6 +326,21 @@ _spdmEncodeMessageGsp
return LIBSPDM_STATUS_INVALID_MSG_FIELD;
}
status = libspdm_get_data(spdm_context, LIBSPDM_DATA_APP_CONTEXT_DATA,
NULL, (void *)&pSpdm, &dataSize);
if (status != LIBSPDM_STATUS_SUCCESS)
{
NV_PRINTF(LEVEL_ERROR, ", spdmStatus != LIBSPDM_STATUS_SUCCESS \n ");
return status;
}
if (pSpdm == NULL)
{
NV_PRINTF(LEVEL_ERROR, " pSpdm == NULL, SPDM context probably corrupted !! \n ");
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
}
// Initialize descriptor header.
pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)*transport_message;
portMemSet(pNvSpdmDescHdr, 0, sizeof(NV_SPDM_DESC_HEADER));
@@ -401,7 +410,7 @@ _spdmEncodeMessageGsp
}
// Check final encrypted message size.
if (*transport_message_size > g_pSpdm->payloadBufferSize)
if (*transport_message_size > pSpdm->payloadBufferSize)
{
return LIBSPDM_STATUS_BUFFER_TOO_SMALL;
}
@@ -432,6 +441,8 @@ _spdmDecodeMessageGsp
void *pSecuredMessageContext = NULL;
libspdm_return_t status = LIBSPDM_STATUS_SUCCESS;
spdm_secured_message_a_data_header1_t *pSpdmSecuredMsgHdr = NULL;
Spdm *pSpdm = NULL;
size_t dataSize = sizeof(void *);
// Check libspdm parameters.
if (spdm_context == NULL || session_id == NULL || is_app_message == NULL ||
@@ -447,10 +458,25 @@ _spdmDecodeMessageGsp
return LIBSPDM_STATUS_INVALID_PARAMETER;
}
status = libspdm_get_data(spdm_context, LIBSPDM_DATA_APP_CONTEXT_DATA,
NULL, (void *)&pSpdm, &dataSize);
if (status != LIBSPDM_STATUS_SUCCESS)
{
NV_PRINTF(LEVEL_ERROR, " spdmStatus != LIBSPDM_STATUS_SUCCESS \n ");
return status;
}
if (pSpdm == NULL)
{
NV_PRINTF(LEVEL_ERROR, " pSpdm == NULL, SPDM context probably corrupted !! \n ");
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
}
// Retrieve NV-header from message, and perform basic validation.
pNvSpdmDescHdr = (NV_SPDM_DESC_HEADER *)transport_message;
if (transport_message_size < sizeof(NV_SPDM_DESC_HEADER) ||
transport_message_size > g_pSpdm->payloadBufferSize)
transport_message_size > pSpdm->payloadBufferSize)
{
return LIBSPDM_STATUS_INVALID_MSG_FIELD;
}
@@ -566,11 +592,11 @@ _spdmSendMessageGsp
uint64_t timeout
)
{
NV_STATUS nvStatus = NV_OK;
libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS;
// Ensure size is cleared to indicate no response pending in buffer yet
g_pendingResponseSize = 0;
NV_STATUS nvStatus = NV_OK;
libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS;
Spdm *pSpdm = NULL;
OBJGPU *pGpu = NULL;
size_t dataSize = sizeof(void *);
// Check libspdm parameters.
if (message_size == 0 || message == NULL)
@@ -578,23 +604,44 @@ _spdmSendMessageGsp
return LIBSPDM_STATUS_INVALID_PARAMETER;
}
if (g_pGpu == NULL || g_pSpdm == NULL)
spdmStatus = libspdm_get_data(spdm_context, LIBSPDM_DATA_APP_CONTEXT_DATA,
NULL, (void *)&pSpdm, &dataSize);
if (spdmStatus != LIBSPDM_STATUS_SUCCESS)
{
NV_PRINTF(LEVEL_ERROR," spdmStatus != LIBSPDM_STATUS_SUCCESS \n ");
return spdmStatus;
}
if (pSpdm == NULL)
{
NV_PRINTF(LEVEL_ERROR, " pSpdm == NULL, SPDM context probably corrupted !! \n ");
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
}
if (g_transportBufferSize < message_size)
pGpu = ENG_GET_GPU(pSpdm);
if (pGpu == NULL)
{
NV_PRINTF(LEVEL_ERROR, " pGpu == NULL, SPDM context probably corrupted !! \n ");
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
}
// Ensure size is cleared to indicate no response pending in buffer yet
pSpdm->pendingResponseSize = 0;
if (pSpdm->transportBufferSize < message_size)
{
return LIBSPDM_STATUS_BUFFER_TOO_SMALL;
}
// Fill transport buffer with message and send
g_pendingResponseSize = g_transportBufferSize;
portMemCopy(g_pTransportBuffer, g_transportBufferSize, message, message_size);
pSpdm->pendingResponseSize = pSpdm->transportBufferSize;
portMemCopy(pSpdm->pTransportBuffer, pSpdm->transportBufferSize, message, message_size);
nvStatus = spdmMessageProcess_HAL(g_pGpu, g_pSpdm,
g_pTransportBuffer, message_size,
g_pTransportBuffer, &g_pendingResponseSize);
nvStatus = spdmMessageProcess_HAL(pGpu, pSpdm,
pSpdm->pTransportBuffer, message_size,
pSpdm->pTransportBuffer, &pSpdm->pendingResponseSize);
if (nvStatus != NV_OK)
{
spdmStatus = LIBSPDM_STATUS_SEND_FAIL;
@@ -603,7 +650,7 @@ _spdmSendMessageGsp
if (spdmStatus != LIBSPDM_STATUS_SUCCESS)
{
// If message failed, size is cleared to indicate no response pending
g_pendingResponseSize = 0;
pSpdm->pendingResponseSize = 0;
}
return spdmStatus;
@@ -623,7 +670,9 @@ _spdmReceiveMessageGsp
uint64_t timeout
)
{
libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS;
libspdm_return_t spdmStatus = LIBSPDM_STATUS_SUCCESS;
Spdm *pSpdm = NULL;
size_t dataSize = sizeof(void *);
// Check libspdm parameters.
if (message_size == NULL || message == NULL || *message == NULL)
@@ -631,25 +680,36 @@ _spdmReceiveMessageGsp
return LIBSPDM_STATUS_INVALID_PARAMETER;
}
if (g_pGpu == NULL || g_pSpdm == NULL)
spdmStatus = libspdm_get_data(spdm_context, LIBSPDM_DATA_APP_CONTEXT_DATA,
NULL, (void *)&pSpdm, &dataSize);
if (spdmStatus != LIBSPDM_STATUS_SUCCESS)
{
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
NV_PRINTF(LEVEL_ERROR, " spdmStatus != LIBSPDM_STATUS_SUCCESS \n ");
return spdmStatus;
}
if (pSpdm == NULL)
{
NV_PRINTF(LEVEL_ERROR, " pSpdm == NULL, SPDM context probably corrupted !! \n ");
return LIBSPDM_STATUS_INVALID_STATE_LOCAL;
}
// Basic validation to ensure we have a real response.
if (g_pendingResponseSize == 0 || g_pendingResponseSize > *message_size)
if (pSpdm->pendingResponseSize == 0 ||
pSpdm->pendingResponseSize > *message_size)
{
spdmStatus = LIBSPDM_STATUS_RECEIVE_FAIL;
goto ErrorExit;
}
portMemCopy(*message, *message_size, g_pTransportBuffer, g_pendingResponseSize);
*message_size = g_pendingResponseSize;
portMemCopy(*message, *message_size,
pSpdm->pTransportBuffer, pSpdm->pendingResponseSize);
*message_size = pSpdm->pendingResponseSize;
ErrorExit:
// Ensure size is cleared to indicate no response pending in buffer
g_pendingResponseSize = 0;
pSpdm->pendingResponseSize = 0;
return spdmStatus;
}
@@ -673,18 +733,14 @@ spdmDeviceInit_GH100
return NV_ERR_INVALID_ARGUMENT;
}
g_pGpu = pGpu;
g_pSpdm = pSpdm;
g_pendingResponseSize = 0;
g_pTransportBuffer = portMemAllocNonPaged(pSpdm->payloadBufferSize);
if (g_pTransportBuffer == NULL)
pSpdm->pendingResponseSize = 0;
pSpdm->pTransportBuffer = portMemAllocNonPaged(pSpdm->payloadBufferSize);
if (pSpdm->pTransportBuffer == NULL)
{
g_transportBufferSize = 0;
pSpdm->transportBufferSize = 0;
return NV_ERR_NO_MEMORY;
}
g_transportBufferSize = pSpdm->payloadBufferSize;
pSpdm->transportBufferSize = pSpdm->payloadBufferSize;
// Register transport layer functionality with library.
libspdm_register_transport_layer_func(pSpdm->pLibspdmContext,
@@ -703,7 +759,6 @@ spdmDeviceInit_GH100
return NV_OK;
}
/*!
* To deinitialize the GSP SPDM Responder, we need to release the surface for
* SPDM communication. GSP-RM will handle the rest.
@@ -717,10 +772,10 @@ spdmDeviceDeinit_GH100
)
{
// Just-in-case, portMemFree handles NULL.
portMemFree(g_pTransportBuffer);
g_pTransportBuffer = NULL;
g_transportBufferSize = 0;
g_pendingResponseSize = 0;
portMemFree(pSpdm->pTransportBuffer);
pSpdm->pTransportBuffer = NULL;
pSpdm->transportBufferSize = 0;
pSpdm->pendingResponseSize = 0;
return NV_OK;
}

5
src/nvidia/src/kernel/gpu/spdm/spdm.c
View File

@@ -432,6 +432,11 @@ spdmContextInit_IMPL
libspdm_init_msg_log(pSpdm->pLibspdmContext, pSpdm->pMsgLog, pSpdm->msgLogMaxSize);
// Store SPDM object pointer to libspdm context
CHECK_SPDM_STATUS(libspdm_set_data(pSpdm->pLibspdmContext, LIBSPDM_DATA_APP_CONTEXT_DATA,
NULL, (void *)&pSpdm, sizeof(void *)));
//
// Perform any device-specific initialization. spdmDeviceInit is also
// responsible for registering transport layer functions with libspdm.

3
src/nvidia/src/kernel/mem_mgr/mem_export.c
View File

@@ -606,7 +606,8 @@ _memoryexportVerifyMem
if (pGpu == NULL)
return NV_OK;
if (pKernelMIGGpuInstance != NULL)
// MIG is about vidmem partitioning, so limit the check.
if ((pKernelMIGGpuInstance != NULL) && (addrSpace == ADDR_FBMEM))
{
if ((pKernelMIGGpuInstance->pMemoryPartitionHeap != pSrcMemory->pHeap))
return NV_ERR_INVALID_OBJECT_PARENT;

10
src/nvidia/src/kernel/virtualization/kernel_vgpu_mgr.c
View File

@@ -1396,15 +1396,9 @@ NvU32 kvgpumgrGetPgpuSubdevIdEncoding(OBJGPU *pGpu, NvU8 *pgpuString,
return NV_U32_MAX;
}
switch (chipID)
{
default:
// The encoding of the subdevice ID is its value converted to string
bytes = NvU32ToAsciiStr(subID, SUBDEVID_ENCODED_VALUE_SIZE,
// The encoding of the subdevice ID is its value converted to string
bytes = NvU32ToAsciiStr(subID, SUBDEVID_ENCODED_VALUE_SIZE,
pgpuString, NV_FALSE);
break;
}
return bytes;
}