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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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35
kernel-open/common/inc/dce_rm_client_ipc.h Normal file
View File

@@ -0,0 +1,35 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OS_DCE_CLIENT_IPC_H_
#define _OS_DCE_CLIENT_IPC_H_
// RM IPC Client Types
#define DCE_CLIENT_RM_IPC_TYPE_SYNC 0x0
#define DCE_CLIENT_RM_IPC_TYPE_EVENT 0x1
#define DCE_CLIENT_RM_IPC_TYPE_MAX 0x2
void dceclientHandleAsyncRpcCallback(NvU32 handle, NvU32 interfaceType,
NvU32 msgLength, void *data,
void *usrCtx);
#endif

229
kernel-open/common/inc/nv-linux.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2001-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2001-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,8 +36,7 @@
#include "nv-timer.h"
#include "nv-time.h"
#include "nv-chardev-numbers.h"
#define NV_KERNEL_NAME "Linux"
#include "nv-platform.h"
#ifndef AUTOCONF_INCLUDED
#if defined(NV_GENERATED_AUTOCONF_H_PRESENT)
@@ -239,7 +238,7 @@ NV_STATUS nvos_forward_error_to_cray(struct pci_dev *, NvU32,
#undef NV_SET_PAGES_UC_PRESENT
#endif
#if !defined(NVCPU_AARCH64) && !defined(NVCPU_PPC64LE) && !defined(NVCPU_RISCV64)
#if !defined(NVCPU_AARCH64) && !defined(NVCPU_RISCV64)
#if !defined(NV_SET_MEMORY_UC_PRESENT) && !defined(NV_SET_PAGES_UC_PRESENT)
#error "This driver requires the ability to change memory types!"
#endif
@@ -403,7 +402,7 @@ typedef enum
NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
} nv_memory_type_t;
#if defined(NVCPU_AARCH64) || defined(NVCPU_PPC64LE) || defined(NVCPU_RISCV64)
#if defined(NVCPU_AARCH64) || defined(NVCPU_RISCV64)
#define NV_ALLOW_WRITE_COMBINING(mt) 1
#elif defined(NVCPU_X86_64)
#if defined(NV_ENABLE_PAT_SUPPORT)
@@ -461,10 +460,7 @@ static inline void *nv_vmalloc(unsigned long size)
#else
void *ptr = __vmalloc(size, GFP_KERNEL);
#endif
if (ptr)
{
NV_MEMDBG_ADD(ptr, size);
}
NV_MEMDBG_ADD(ptr, size);
return ptr;
}
@@ -481,10 +477,7 @@ static inline void *nv_ioremap(NvU64 phys, NvU64 size)
#else
void *ptr = ioremap(phys, size);
#endif
if (ptr)
{
NV_MEMDBG_ADD(ptr, size);
}
NV_MEMDBG_ADD(ptr, size);
return ptr;
}
@@ -500,29 +493,12 @@ static inline void *nv_ioremap_cache(NvU64 phys, NvU64 size)
ptr = ioremap_cache_shared(phys, size);
#elif defined(NV_IOREMAP_CACHE_PRESENT)
ptr = ioremap_cache(phys, size);
#elif defined(NVCPU_PPC64LE)
//
// ioremap_cache() has been only implemented correctly for ppc64le with
// commit f855b2f544d6 in April 2017 (kernel 4.12+). Internally, the kernel
// does provide a default implementation of ioremap_cache() that would be
// incorrect for our use (creating an uncached mapping) before the
// referenced commit, but that implementation is not exported and the
// NV_IOREMAP_CACHE_PRESENT conftest doesn't pick it up, and we end up in
// this #elif branch.
//
// At the same time, ppc64le have supported ioremap_prot() since May 2011
// (commit 40f1ce7fb7e8, kernel 3.0+) and that covers all kernels we
// support on power.
//
ptr = ioremap_prot(phys, size, pgprot_val(PAGE_KERNEL));
#else
return nv_ioremap(phys, size);
#endif
if (ptr)
{
NV_MEMDBG_ADD(ptr, size);
}
NV_MEMDBG_ADD(ptr, size);
return ptr;
}
@@ -537,10 +513,8 @@ static inline void *nv_ioremap_wc(NvU64 phys, NvU64 size)
return nv_ioremap_nocache(phys, size);
#endif
if (ptr)
{
NV_MEMDBG_ADD(ptr, size);
}
NV_MEMDBG_ADD(ptr, size);
return ptr;
}
@@ -560,22 +534,19 @@ static NvBool nv_numa_node_has_memory(int node_id)
#define NV_KMALLOC(ptr, size) \
{ \
(ptr) = kmalloc(size, NV_GFP_KERNEL); \
if (ptr) \
NV_MEMDBG_ADD(ptr, size); \
NV_MEMDBG_ADD(ptr, size); \
}
#define NV_KZALLOC(ptr, size) \
{ \
(ptr) = kzalloc(size, NV_GFP_KERNEL); \
if (ptr) \
NV_MEMDBG_ADD(ptr, size); \
NV_MEMDBG_ADD(ptr, size); \
}
#define NV_KMALLOC_ATOMIC(ptr, size) \
{ \
(ptr) = kmalloc(size, NV_GFP_ATOMIC); \
if (ptr) \
NV_MEMDBG_ADD(ptr, size); \
NV_MEMDBG_ADD(ptr, size); \
}
#if defined(__GFP_RETRY_MAYFAIL)
@@ -589,8 +560,7 @@ static NvBool nv_numa_node_has_memory(int node_id)
#define NV_KMALLOC_NO_OOM(ptr, size) \
{ \
(ptr) = kmalloc(size, NV_GFP_NO_OOM); \
if (ptr) \
NV_MEMDBG_ADD(ptr, size); \
NV_MEMDBG_ADD(ptr, size); \
}
#define NV_KFREE(ptr, size) \
@@ -623,9 +593,9 @@ static inline pgprot_t nv_sme_clr(pgprot_t prot)
#endif // __sme_clr
}
static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra)
static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot)
{
pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra);
pgprot_t prot = __pgprot(pgprot_val(vm_prot));
#if defined(pgprot_decrypted)
return pgprot_decrypted(prot);
@@ -646,41 +616,6 @@ static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra)
#endif
#endif
static inline NvUPtr nv_vmap(struct page **pages, NvU32 page_count,
NvBool cached, NvBool unencrypted)
{
void *ptr;
pgprot_t prot = PAGE_KERNEL;
#if defined(NVCPU_X86_64)
#if defined(PAGE_KERNEL_NOENC)
if (unencrypted)
{
prot = cached ? nv_adjust_pgprot(PAGE_KERNEL_NOENC, 0) :
nv_adjust_pgprot(NV_PAGE_KERNEL_NOCACHE_NOENC, 0);
}
else
#endif
{
prot = cached ? PAGE_KERNEL : PAGE_KERNEL_NOCACHE;
}
#elif defined(NVCPU_AARCH64)
prot = cached ? PAGE_KERNEL : NV_PGPROT_UNCACHED(PAGE_KERNEL);
#endif
/* All memory cached in PPC64LE; can't honor 'cached' input. */
ptr = vmap(pages, page_count, VM_MAP, prot);
if (ptr)
{
NV_MEMDBG_ADD(ptr, page_count * PAGE_SIZE);
}
return (NvUPtr)ptr;
}
static inline void nv_vunmap(NvUPtr vaddr, NvU32 page_count)
{
vunmap((void *)vaddr);
NV_MEMDBG_REMOVE((void *)vaddr, page_count * PAGE_SIZE);
}
#if defined(NV_GET_NUM_PHYSPAGES_PRESENT)
#define NV_NUM_PHYSPAGES get_num_physpages()
#else
@@ -705,6 +640,47 @@ static inline void nv_vunmap(NvUPtr vaddr, NvU32 page_count)
#define NV_NUM_CPUS() num_possible_cpus()
#define NV_HAVE_MEMORY_ENCRYPT_DECRYPT 0
#if defined(NVCPU_X86_64) && \
NV_IS_EXPORT_SYMBOL_GPL_set_memory_encrypted && \
NV_IS_EXPORT_SYMBOL_GPL_set_memory_decrypted
#undef NV_HAVE_MEMORY_ENCRYPT_DECRYPT
#define NV_HAVE_MEMORY_ENCRYPT_DECRYPT 1
#endif
static inline void nv_set_memory_decrypted_zeroed(NvBool unencrypted,
unsigned long virt_addr,
int num_native_pages,
size_t size)
{
if (virt_addr == 0)
return;
#if NV_HAVE_MEMORY_ENCRYPT_DECRYPT
if (unencrypted)
{
set_memory_decrypted(virt_addr, num_native_pages);
memset((void *)virt_addr, 0, size);
}
#endif
}
static inline void nv_set_memory_encrypted(NvBool unencrypted,
unsigned long virt_addr,
int num_native_pages)
{
if (virt_addr == 0)
return;
#if NV_HAVE_MEMORY_ENCRYPT_DECRYPT
if (unencrypted)
{
set_memory_encrypted(virt_addr, num_native_pages);
}
#endif
}
static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
{
#if defined(NV_PHYS_TO_DMA_PRESENT)
@@ -885,94 +861,42 @@ typedef void irqreturn_t;
(((addr) >> NV_RM_PAGE_SHIFT) == \
(((addr) + (size) - 1) >> NV_RM_PAGE_SHIFT)))
/*
* The kernel may have a workaround for this, by providing a method to isolate
* a single 4K page in a given mapping.
*/
#if (PAGE_SIZE > NV_RM_PAGE_SIZE) && defined(NVCPU_PPC64LE) && defined(NV_PAGE_4K_PFN)
#define NV_4K_PAGE_ISOLATION_PRESENT
#define NV_4K_PAGE_ISOLATION_MMAP_ADDR(addr) \
((NvP64)((void*)(((addr) >> NV_RM_PAGE_SHIFT) << PAGE_SHIFT)))
#define NV_4K_PAGE_ISOLATION_MMAP_LEN(size) PAGE_SIZE
#define NV_4K_PAGE_ISOLATION_ACCESS_START(addr) \
((NvP64)((void*)((addr) & ~NV_RM_PAGE_MASK)))
#define NV_4K_PAGE_ISOLATION_ACCESS_LEN(addr, size) \
((((addr) & NV_RM_PAGE_MASK) + size + NV_RM_PAGE_MASK) & \
~NV_RM_PAGE_MASK)
#define NV_PROT_4K_PAGE_ISOLATION NV_PAGE_4K_PFN
#endif
static inline int nv_remap_page_range(struct vm_area_struct *vma,
unsigned long virt_addr, NvU64 phys_addr, NvU64 size, pgprot_t prot)
{
int ret = -1;
#if defined(NV_4K_PAGE_ISOLATION_PRESENT) && defined(NV_PROT_4K_PAGE_ISOLATION)
if ((size == PAGE_SIZE) &&
((pgprot_val(prot) & NV_PROT_4K_PAGE_ISOLATION) != 0))
{
/*
* remap_4k_pfn() hardcodes the length to a single OS page, and checks
* whether applying the page isolation workaround will cause PTE
* corruption (in which case it will fail, and this is an unsupported
* configuration).
*/
#if defined(NV_HASH__REMAP_4K_PFN_PRESENT)
ret = hash__remap_4k_pfn(vma, virt_addr, (phys_addr >> PAGE_SHIFT), prot);
#else
ret = remap_4k_pfn(vma, virt_addr, (phys_addr >> PAGE_SHIFT), prot);
#endif
}
else
#endif
{
ret = remap_pfn_range(vma, virt_addr, (phys_addr >> PAGE_SHIFT), size,
return remap_pfn_range(vma, virt_addr, (phys_addr >> PAGE_SHIFT), size,
prot);
}
return ret;
}
static inline int nv_io_remap_page_range(struct vm_area_struct *vma,
NvU64 phys_addr, NvU64 size, NvU32 extra_prot, NvU64 start)
NvU64 phys_addr, NvU64 size, NvU64 start)
{
int ret = -1;
#if !defined(NV_XEN_SUPPORT_FULLY_VIRTUALIZED_KERNEL)
ret = nv_remap_page_range(vma, start, phys_addr, size,
nv_adjust_pgprot(vma->vm_page_prot, extra_prot));
nv_adjust_pgprot(vma->vm_page_prot));
#else
ret = io_remap_pfn_range(vma, start, (phys_addr >> PAGE_SHIFT),
size, nv_adjust_pgprot(vma->vm_page_prot, extra_prot));
size, nv_adjust_pgprot(vma->vm_page_prot));
#endif
return ret;
}
static inline vm_fault_t nv_insert_pfn(struct vm_area_struct *vma,
NvU64 virt_addr, NvU64 pfn, NvU32 extra_prot)
NvU64 virt_addr, NvU64 pfn)
{
/*
* vm_insert_pfn{,_prot} replaced with vmf_insert_pfn{,_prot} in Linux 4.20
*/
#if defined(NV_VMF_INSERT_PFN_PROT_PRESENT)
return vmf_insert_pfn_prot(vma, virt_addr, pfn,
__pgprot(pgprot_val(vma->vm_page_prot) | extra_prot));
__pgprot(pgprot_val(vma->vm_page_prot)));
#else
int ret = -EINVAL;
/*
* Only PPC64LE (NV_4K_PAGE_ISOLATION_PRESENT) requires extra_prot to be
* used when remapping.
*
* vm_insert_pfn_prot() was added in Linux 4.4, whereas POWER9 support
* was added in Linux 4.8.
*
* Rather than tampering with the vma to make use of extra_prot with
* vm_insert_pfn() on older kernels, for now, just fail in this case, as
* it's not expected to be used currently.
*/
#if defined(NV_VM_INSERT_PFN_PROT_PRESENT)
ret = vm_insert_pfn_prot(vma, virt_addr, pfn,
__pgprot(pgprot_val(vma->vm_page_prot) | extra_prot));
#elif !defined(NV_4K_PAGE_ISOLATION_PRESENT)
__pgprot(pgprot_val(vma->vm_page_prot)));
#else
ret = vm_insert_pfn(vma, virt_addr, pfn);
#endif
switch (ret)
@@ -1158,7 +1082,6 @@ static inline void nv_kmem_cache_free_stack(nvidia_stack_t *stack)
typedef struct nvidia_pte_s {
NvU64 phys_addr;
unsigned long virt_addr;
NvU64 dma_addr;
} nvidia_pte_t;
#if defined(CONFIG_DMA_SHARED_BUFFER)
@@ -1199,6 +1122,7 @@ typedef struct nv_alloc_s {
NvS32 node_id; /* Node id for memory allocation when node is set in flags */
void *import_priv;
struct sg_table *import_sgt;
dma_addr_t dma_handle; /* dma handle used by dma_alloc_coherent(), dma_free_coherent() */
} nv_alloc_t;
/**
@@ -1424,6 +1348,23 @@ struct os_wait_queue {
struct completion q;
};
/*!
* @brief Mapping between clock names and clock handles.
*
* TEGRA_DISP_WHICH_CLK_MAX: maximum number of clocks
* defined in below enum.
*
* arch/nvalloc/unix/include/nv.h
* enum TEGRASOC_WHICH_CLK_MAX;
*
*/
typedef struct nvsoc_clks_s {
struct {
struct clk *handles;
const char *clkName;
} clk[TEGRASOC_WHICH_CLK_MAX];
} nvsoc_clks_t;
/*
* To report error in msi/msix when unhandled count reaches a threshold
*/
@@ -1583,6 +1524,8 @@ typedef struct nv_linux_state_s {
nv_acpi_t* nv_acpi_object;
#endif
nvsoc_clks_t soc_clk_handles;
/* Lock serializing ISRs for different SOC vectors */
nv_spinlock_t soc_isr_lock;
void *soc_bh_mutex;
@@ -1782,12 +1725,10 @@ static inline struct kmem_cache *nv_kmem_cache_create(const char *name, unsigned
*/
static inline NV_STATUS nv_check_gpu_state(nv_state_t *nv)
{
#if !defined(NVCPU_PPC64LE)
if (NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv))
{
return NV_ERR_GPU_IS_LOST;
}
#endif
return NV_OK;
}

3
kernel-open/common/inc/nv-msi.h
View File

@@ -26,8 +26,7 @@
#include "nv-linux.h"
#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64) || \
defined(NVCPU_PPC64LE)) && \
#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64)) && \
(defined(CONFIG_PCI_MSI) || defined(CONFIG_PCI_USE_VECTOR))
#define NV_LINUX_PCIE_MSI_SUPPORTED
#endif

36
kernel-open/common/inc/nv-platform.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef NV_PLATFORM_H
#define NV_PLATFORM_H
#include "nv-linux.h"
irqreturn_t nvidia_isr (int, void *);
irqreturn_t nvidia_isr_kthread_bh (int, void *);
#define NV_SUPPORTS_PLATFORM_DEVICE 0
#define NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE 0
#endif

2
kernel-open/common/inc/nv-proto.h
View File

@@ -41,7 +41,7 @@ void nv_procfs_remove_gpu (nv_linux_state_t *);
int nvidia_mmap (struct file *, struct vm_area_struct *);
int nvidia_mmap_helper (nv_state_t *, nv_linux_file_private_t *, nvidia_stack_t *, struct vm_area_struct *, void *);
int nv_encode_caching (pgprot_t *, NvU32, NvU32);
int nv_encode_caching (pgprot_t *, NvU32, nv_memory_type_t);
void nv_revoke_gpu_mappings_locked(nv_state_t *);
NvUPtr nv_vm_map_pages (struct page **, NvU32, NvBool, NvBool);

60
kernel-open/common/inc/nv.h
View File

@@ -168,6 +168,15 @@ typedef enum _TEGRASOC_WHICH_CLK
TEGRASOC_WHICH_CLK_PLLA_DISP,
TEGRASOC_WHICH_CLK_PLLA_DISPHUB,
TEGRASOC_WHICH_CLK_PLLA,
TEGRASOC_WHICH_CLK_EMC,
TEGRASOC_WHICH_CLK_GPU_FIRST,
TEGRASOC_WHICH_CLK_GPU_SYS = TEGRASOC_WHICH_CLK_GPU_FIRST,
TEGRASOC_WHICH_CLK_GPU_NVD,
TEGRASOC_WHICH_CLK_GPU_UPROC,
TEGRASOC_WHICH_CLK_GPU_GPC0,
TEGRASOC_WHICH_CLK_GPU_GPC1,
TEGRASOC_WHICH_CLK_GPU_GPC2,
TEGRASOC_WHICH_CLK_GPU_LAST = TEGRASOC_WHICH_CLK_GPU_GPC2,
TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only.
} TEGRASOC_WHICH_CLK;
@@ -283,7 +292,6 @@ typedef struct nv_usermap_access_params_s
MemoryArea memArea;
NvU64 access_start;
NvU64 access_size;
NvU64 remap_prot_extra;
NvBool contig;
NvU32 caching;
} nv_usermap_access_params_t;
@@ -299,7 +307,6 @@ typedef struct nv_alloc_mapping_context_s {
MemoryArea memArea;
NvU64 access_start;
NvU64 access_size;
NvU64 remap_prot_extra;
NvU32 prot;
NvBool valid;
NvU32 caching;
@@ -567,24 +574,24 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
* flags
*/
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
// Unused 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_SOC_IGPU 0x0200
#define NV_FLAG_OPEN 0x0001
#define NV_FLAG_EXCLUDE 0x0002
#define NV_FLAG_CONTROL 0x0004
// Unused 0x0008
#define NV_FLAG_SOC_DISPLAY 0x0010
#define NV_FLAG_USES_MSI 0x0020
#define NV_FLAG_USES_MSIX 0x0040
#define NV_FLAG_PASSTHRU 0x0080
#define NV_FLAG_SUSPENDED 0x0100
#define NV_FLAG_SOC_IGPU 0x0200
/* To be set when an FLR needs to be triggered after device shut down. */
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
// Unused 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
#define NV_FLAG_TRIGGER_FLR 0x0400
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
#define NV_FLAG_IN_RECOVERY 0x1000
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
#define NV_FLAG_UNBIND_LOCK 0x4000
/* To be set when GPU is not present on the bus, to help device teardown */
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
typedef enum
{
@@ -798,7 +805,7 @@ NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, Nv
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *);
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **);
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
void NV_API_CALL nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **);
NV_STATUS NV_API_CALL nv_register_peer_io_mem (nv_state_t *, NvU64 *, NvU64, void **);
@@ -918,6 +925,15 @@ NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *);
void NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *);
NV_STATUS NV_API_CALL nv_clk_get_handles (nv_state_t *);
void NV_API_CALL nv_clk_clear_handles (nv_state_t *);
NV_STATUS NV_API_CALL nv_enable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
void NV_API_CALL nv_disable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
NV_STATUS NV_API_CALL nv_get_curr_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
NV_STATUS NV_API_CALL nv_get_max_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
NV_STATUS NV_API_CALL nv_get_min_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
NV_STATUS NV_API_CALL nv_set_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32);
/*
* ---------------------------------------------------------------------------
*
@@ -945,6 +961,7 @@ NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *
void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *);
void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *);
NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *);
NvBool NV_API_CALL rm_wait_for_bar_firewall (nvidia_stack_t *, NvU32 domain, NvU8 bus, NvU8 device, NvU8 function, NvU16 devId);
NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t);
NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *);
NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *);
@@ -1043,6 +1060,9 @@ void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *);
NvBool NV_API_CALL rm_is_altstack_in_use(void);
void NV_API_CALL rm_notify_gpu_addition(nvidia_stack_t *, nv_state_t *);
void NV_API_CALL rm_notify_gpu_removal(nvidia_stack_t *, nv_state_t *);
/* vGPU VFIO specific functions */
NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *,
NvU32 *, NvU32 *, NvU32);
@@ -1057,7 +1077,7 @@ NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *,
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);
NV_STATUS NV_API_CALL nv_check_usermap_access_params(nv_state_t*, const nv_usermap_access_params_t*);
nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*);
void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size);

120
kernel-open/common/inc/nv_common_utils.h Normal file
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@@ -0,0 +1,120 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_COMMON_UTILS_H__
#define __NV_COMMON_UTILS_H__
#include "nvtypes.h"
#include "nvmisc.h"
#if !defined(TRUE)
#define TRUE NV_TRUE
#endif
#if !defined(FALSE)
#define FALSE NV_FALSE
#endif
#define NV_IS_UNSIGNED(x) ((__typeof__(x))-1 > 0)
/* Get the length of a statically-sized array. */
#define ARRAY_LEN(_arr) (sizeof(_arr) / sizeof(_arr[0]))
#define NV_INVALID_HEAD 0xFFFFFFFF
#define NV_INVALID_CONNECTOR_PHYSICAL_INFORMATION (~0)
#if !defined(NV_MIN)
# define NV_MIN(a,b) (((a)<(b))?(a):(b))
#endif
#define NV_MIN3(a,b,c) NV_MIN(NV_MIN(a, b), c)
#define NV_MIN4(a,b,c,d) NV_MIN3(NV_MIN(a,b),c,d)
#if !defined(NV_MAX)
# define NV_MAX(a,b) (((a)>(b))?(a):(b))
#endif
#define NV_MAX3(a,b,c) NV_MAX(NV_MAX(a, b), c)
#define NV_MAX4(a,b,c,d) NV_MAX3(NV_MAX(a,b),c,d)
static inline int NV_LIMIT_VAL_TO_MIN_MAX(int val, int min, int max)
{
if (val < min) {
return min;
}
if (val > max) {
return max;
}
return val;
}
#define NV_ROUNDUP_DIV(x,y) ((x) / (y) + (((x) % (y)) ? 1 : 0))
/*
* Macros used for computing palette entries:
*
* NV_UNDER_REPLICATE(val, source_size, result_size) expands a value
* of source_size bits into a value of target_size bits by shifting
* the source value into the high bits and replicating the high bits
* of the value into the low bits of the result.
*
* PALETTE_DEPTH_SHIFT(val, w) maps a colormap entry for a component
* that has w bits to an appropriate entry in a LUT of 256 entries.
*/
static inline unsigned int NV_UNDER_REPLICATE(unsigned short val,
int source_size,
int result_size)
{
return (val << (result_size - source_size)) |
(val >> ((source_size << 1) - result_size));
}
static inline unsigned short PALETTE_DEPTH_SHIFT(unsigned short val, int depth)
{
return NV_UNDER_REPLICATE(val, depth, 8);
}
/*
* Use __builtin_ffs where it is supported, or provide an equivalent
* implementation for platforms like riscv where it is not.
*/
#if defined(__GNUC__) && !NVCPU_IS_RISCV64
static inline int nv_ffs(int x)
{
return __builtin_ffs(x);
}
#else
static inline int nv_ffs(int x)
{
if (x == 0)
return 0;
LOWESTBITIDX_32(x);
return 1 + x;
}
#endif
#endif /* __NV_COMMON_UTILS_H__ */

370
kernel-open/common/inc/nv_dpy_id.h Normal file
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@@ -0,0 +1,370 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/*
* This header file defines the types NVDpyId and NVDpyIdList, as well
* as inline functions to manipulate these types. NVDpyId and
* NVDpyIdList should be treated as opaque by includers of this header
* file.
*/
#ifndef __NV_DPY_ID_H__
#define __NV_DPY_ID_H__
#include "nvtypes.h"
#include "nvmisc.h"
#include "nv_common_utils.h"
#include <nvlimits.h> /* NV_MAX_SUBDEVICES */
typedef struct {
NvU32 opaqueDpyId;
} NVDpyId;
typedef struct {
NvU32 opaqueDpyIdList;
} NVDpyIdList;
#define NV_DPY_ID_MAX_SUBDEVICES NV_MAX_SUBDEVICES
#define NV_DPY_ID_MAX_DPYS_IN_LIST 32
/*
* For use in combination with nvDpyIdToPrintFormat(); e.g.,
*
* printf("dpy id: " NV_DPY_ID_PRINT_FORMAT "\n",
* nvDpyIdToPrintFormat(dpyId));
*
* The includer should not make assumptions about the return type of
* nvDpyIdToPrintFormat().
*/
#define NV_DPY_ID_PRINT_FORMAT "0x%08x"
/* functions to return an invalid DpyId and empty DpyIdList */
static inline NVDpyId nvInvalidDpyId(void)
{
NVDpyId dpyId = { 0 };
return dpyId;
}
static inline NVDpyIdList nvEmptyDpyIdList(void)
{
NVDpyIdList dpyIdList = { 0 };
return dpyIdList;
}
static inline NVDpyIdList nvAllDpyIdList(void)
{
NVDpyIdList dpyIdList = { ~0U };
return dpyIdList;
}
static inline void
nvEmptyDpyIdListSubDeviceArray(NVDpyIdList dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
{
int dispIndex;
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
dpyIdList[dispIndex] = nvEmptyDpyIdList();
}
}
/* set operations on DpyIds and DpyIdLists: Add, Subtract, Intersect, Xor */
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvAddDpyIdToDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList |
dpyId.opaqueDpyId;
return tmpDpyIdList;
}
/* Passing an invalid display ID makes this function return an empty list. */
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvAddDpyIdToEmptyDpyIdList(NVDpyId dpyId)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyId.opaqueDpyId;
return tmpDpyIdList;
}
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvAddDpyIdListToDpyIdList(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdListB.opaqueDpyIdList |
dpyIdListA.opaqueDpyIdList;
return tmpDpyIdList;
}
/* Returns: dpyIdList - dpyId */
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvDpyIdListMinusDpyId(NVDpyIdList dpyIdList, NVDpyId dpyId)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
(~dpyId.opaqueDpyId);
return tmpDpyIdList;
}
/* Returns: dpyIdListA - dpyIdListB */
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvDpyIdListMinusDpyIdList(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
(~dpyIdListB.opaqueDpyIdList);
return tmpDpyIdList;
}
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvIntersectDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
dpyId.opaqueDpyId;
return tmpDpyIdList;
}
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvIntersectDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
dpyIdListB.opaqueDpyIdList;
return tmpDpyIdList;
}
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvXorDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList ^
dpyId.opaqueDpyId;
return tmpDpyIdList;
}
static inline __attribute__ ((warn_unused_result))
NVDpyIdList nvXorDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
NVDpyIdList tmpDpyIdList;
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList ^
dpyIdListB.opaqueDpyIdList;
return tmpDpyIdList;
}
/* boolean checks */
static inline NvBool nvDpyIdIsInDpyIdList(NVDpyId dpyId,
NVDpyIdList dpyIdList)
{
return !!(dpyIdList.opaqueDpyIdList & dpyId.opaqueDpyId);
}
static inline NvBool nvDpyIdIsInvalid(NVDpyId dpyId)
{
return (dpyId.opaqueDpyId == 0);
}
static inline NvBool nvDpyIdListIsEmpty(NVDpyIdList dpyIdList)
{
return (dpyIdList.opaqueDpyIdList == 0);
}
static inline NvBool
nvDpyIdListSubDeviceArrayIsEmpty(NVDpyIdList
dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
{
int dispIndex;
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
if (!nvDpyIdListIsEmpty(dpyIdList[dispIndex])) {
return NV_FALSE;
}
}
return NV_TRUE;
}
static inline NvBool nvDpyIdsAreEqual(NVDpyId dpyIdA, NVDpyId dpyIdB)
{
return (dpyIdA.opaqueDpyId == dpyIdB.opaqueDpyId);
}
static inline NvBool nvDpyIdListsAreEqual(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
return (dpyIdListA.opaqueDpyIdList == dpyIdListB.opaqueDpyIdList);
}
static inline NvBool nvDpyIdListIsASubSetofDpyIdList(NVDpyIdList dpyIdListA,
NVDpyIdList dpyIdListB)
{
NVDpyIdList intersectedDpyIdList =
nvIntersectDpyIdListAndDpyIdList(dpyIdListA, dpyIdListB);
return nvDpyIdListsAreEqual(intersectedDpyIdList, dpyIdListA);
}
/*
* retrieve the individual dpyIds from dpyIdList; if dpyId is invalid,
* start at the beginning of the list; otherwise, start at the dpyId
* after the specified dpyId
*/
static inline __attribute__ ((warn_unused_result))
NVDpyId nvNextDpyIdInDpyIdListUnsorted(NVDpyId dpyId, NVDpyIdList dpyIdList)
{
if (nvDpyIdIsInvalid(dpyId)) {
dpyId.opaqueDpyId = 1;
} else {
dpyId.opaqueDpyId <<= 1;
}
while (dpyId.opaqueDpyId) {
if (nvDpyIdIsInDpyIdList(dpyId, dpyIdList)) {
return dpyId;
}
dpyId.opaqueDpyId <<= 1;
}
/* no dpyIds left in dpyIdlist; return the invalid dpyId */
return nvInvalidDpyId();
}
#define FOR_ALL_DPY_IDS(_dpyId, _dpyIdList) \
for ((_dpyId) = nvNextDpyIdInDpyIdListUnsorted(nvInvalidDpyId(), \
(_dpyIdList)); \
!nvDpyIdIsInvalid(_dpyId); \
(_dpyId) = nvNextDpyIdInDpyIdListUnsorted((_dpyId), \
(_dpyIdList)))
/* report how many dpyIds are in the dpyIdList */
static inline int nvCountDpyIdsInDpyIdList(NVDpyIdList dpyIdList)
{
return nvPopCount32(dpyIdList.opaqueDpyIdList);
}
static inline int
nvCountDpyIdsInDpyIdListSubDeviceArray(NVDpyIdList
dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
{
int dispIndex, n = 0;
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
n += nvCountDpyIdsInDpyIdList(dpyIdList[dispIndex]);
}
return n;
}
/* convert between dpyId/dpyIdList and NV-CONTROL values */
static inline int nvDpyIdToNvControlVal(NVDpyId dpyId)
{
return (int) dpyId.opaqueDpyId;
}
static inline int nvDpyIdListToNvControlVal(NVDpyIdList dpyIdList)
{
return (int) dpyIdList.opaqueDpyIdList;
}
static inline NVDpyId nvNvControlValToDpyId(int val)
{
NVDpyId dpyId;
dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
return dpyId;
}
static inline NVDpyIdList nvNvControlValToDpyIdList(int val)
{
NVDpyIdList dpyIdList;
dpyIdList.opaqueDpyIdList = val;
return dpyIdList;
}
/* convert between dpyId and NvU32 */
static inline NVDpyId nvNvU32ToDpyId(NvU32 val)
{
NVDpyId dpyId;
dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
return dpyId;
}
static inline NVDpyIdList nvNvU32ToDpyIdList(NvU32 val)
{
NVDpyIdList dpyIdList;
dpyIdList.opaqueDpyIdList = val;
return dpyIdList;
}
static inline NvU32 nvDpyIdToNvU32(NVDpyId dpyId)
{
return dpyId.opaqueDpyId;
}
static inline NvU32 nvDpyIdListToNvU32(NVDpyIdList dpyIdList)
{
return dpyIdList.opaqueDpyIdList;
}
/* Return the bit position of dpyId: a number in the range [0..31]. */
static inline NvU32 nvDpyIdToIndex(NVDpyId dpyId)
{
return nv_ffs(dpyId.opaqueDpyId) - 1;
}
/* Return a display ID that is not in the list passed in. */
static inline NVDpyId nvNewDpyId(NVDpyIdList excludeList)
{
NVDpyId dpyId;
if (~excludeList.opaqueDpyIdList == 0) {
return nvInvalidDpyId();
}
dpyId.opaqueDpyId =
1U << (nv_ffs(~excludeList.opaqueDpyIdList) - 1);
return dpyId;
}
/* See comment for NV_DPY_ID_PRINT_FORMAT. */
static inline NvU32 nvDpyIdToPrintFormat(NVDpyId dpyId)
{
return nvDpyIdToNvU32(dpyId);
}
/* Prevent usage of opaque values. */
#define opaqueDpyId __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
#define opaqueDpyIdList __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
#endif /* __NV_DPY_ID_H__ */

40
kernel-open/common/inc/nv_mig_types.h Normal file
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@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_MIG_TYPES_H__
#define __NV_MIG_TYPES_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
typedef NvU32 MIGDeviceId;
#define NO_MIG_DEVICE 0L
#ifdef __cplusplus
}
#endif
#endif /* __NV_MIG_TYPES_H__ */

12
kernel-open/common/inc/nv_uvm_interface.h
View File

@@ -660,14 +660,20 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
RM will propagate the update to all channels using the provided VA space.
All channels must be idle when this call is made.
If the pageDirectory is in system memory then a CPU physical address must be
provided. RM will establish and manage the DMA mapping for the
pageDirectory.
Arguments:
vaSpace[IN} - VASpace Object
physAddress[IN] - Physical address of new page directory
physAddress[IN] - Physical address of new page directory. If
!bVidMemAperture this is a CPU physical address.
numEntries[IN] - Number of entries including previous PDE which will be copied
bVidMemAperture[IN] - If set pageDirectory will reside in VidMem aperture else sysmem
pasid[IN] - PASID (Process Address Space IDentifier) of the process
corresponding to the VA space. Ignored unless the VA space
object has ATS enabled.
dmaAddress[OUT] - DMA mapping created for physAddress.
Error codes:
NV_ERR_GENERIC
@@ -675,7 +681,8 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
*/
NV_STATUS nvUvmInterfaceSetPageDirectory(uvmGpuAddressSpaceHandle vaSpace,
NvU64 physAddress, unsigned numEntries,
NvBool bVidMemAperture, NvU32 pasid);
NvBool bVidMemAperture, NvU32 pasid,
NvU64 *dmaAddress);
/*******************************************************************************
nvUvmInterfaceUnsetPageDirectory
@@ -1862,5 +1869,4 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext,
NV_STATUS nvUvmInterfaceCslLogEncryption(UvmCslContext *uvmCslContext,
UvmCslOperation operation,
NvU32 bufferSize);
#endif // _NV_UVM_INTERFACE_H_

9
kernel-open/common/inc/nv_uvm_types.h
View File

@@ -268,6 +268,7 @@ typedef struct UvmGpuChannelInfo_tag
// The errorNotifier is filled out when the channel hits an RC error.
NvNotification *errorNotifier;
NvNotification *keyRotationNotifier;
NvU32 hwRunlistId;
@@ -297,6 +298,7 @@ typedef struct UvmGpuChannelInfo_tag
NvU64 gpFifoGpuVa;
NvU64 gpPutGpuVa;
NvU64 gpGetGpuVa;
// GPU VA of work submission offset is needed in Confidential Computing
// so CE channels can ring doorbell of other channels as required for
// WLC/LCIC work submission
@@ -374,6 +376,9 @@ typedef struct
// True if the CE can be used for P2P transactions
NvBool p2p:1;
// True if the CE supports encryption
NvBool secure:1;
// Mask of physical CEs assigned to this LCE
//
// The value returned by RM for this field may change when a GPU is
@@ -1007,17 +1012,17 @@ typedef struct UvmGpuFaultInfo_tag
NvU32 replayableFaultMask;
// Fault buffer CPU mapping
void* bufferAddress;
//
// When Confidential Computing is disabled, the mapping points to the
// actual HW fault buffer.
//
// When Confidential Computing is enabled, the mapping points to a
// copy of the HW fault buffer. This "shadow buffer" is maintained
// by GSP-RM.
void* bufferAddress;
// Size, in bytes, of the fault buffer pointed by bufferAddress.
NvU32 bufferSize;
// Mapping pointing to the start of the fault buffer metadata containing
// a 16Byte authentication tag and a valid byte. Always NULL when
// Confidential Computing is disabled.

37
kernel-open/common/inc/nvi2c.h Normal file
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@@ -0,0 +1,37 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _NV_I2C_H_
#define _NV_I2C_H_
#define NV_I2C_MSG_WR 0x0000
#define NV_I2C_MSG_RD 0x0001
typedef struct nv_i2c_msg_s
{
NvU16 addr;
NvU16 flags;
NvU16 len;
NvU8* buf;
} nv_i2c_msg_t;
#endif

96
kernel-open/common/inc/nvimpshared.h Normal file
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@@ -0,0 +1,96 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/******************************************************************************\
* *
* Description: *
* Accommodates sharing of IMP-related structures between kernel interface *
* files and core RM. *
* *
\******************************************************************************/
#pragma once
#include <nvtypes.h>
#if defined(_MSC_VER)
#pragma warning(disable:4324)
#endif
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: nvimpshared.finn
//
//
// There are only a small number of discrete dramclk frequencies available on
// the system. This structure contains IMP-relevant information associated
// with a specific dramclk frequency.
//
typedef struct DRAM_CLK_INSTANCE {
NvU32 dram_clk_freq_khz;
NvU32 mchub_clk_khz;
NvU32 mc_clk_khz;
NvU32 max_iso_bw_kbps;
//
// switch_latency_ns is the maximum time required to switch the dramclk
// frequency to the frequency specified in dram_clk_freq_khz.
//
NvU32 switch_latency_ns;
} DRAM_CLK_INSTANCE;
//
// This table is used to collect information from other modules that is needed
// for RM IMP calculations. (Used on Tegra only.)
//
typedef struct TEGRA_IMP_IMPORT_DATA {
//
// max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
// display, assuming display is the only active ISO client. (Note that ISO
// bandwidth will typically be allocated to multiple clients, so display
// will generally not have access to the maximum possible bandwidth.)
//
NvU32 max_iso_bw_kbps;
// On Orin, each dram channel is 16 bits wide.
NvU32 num_dram_channels;
//
// dram_clk_instance stores entries for all possible dramclk frequencies,
// sorted by dramclk frequency in increasing order.
//
// "24" is expected to be larger than the actual number of required entries
// (which is provided by a BPMP API), but it can be increased if necessary.
//
// num_dram_clk_entries is filled in with the actual number of distinct
// dramclk entries.
//
NvU32 num_dram_clk_entries;
DRAM_CLK_INSTANCE dram_clk_instance[24];
} TEGRA_IMP_IMPORT_DATA;

24
kernel-open/common/inc/nvkms-api-types.h
View File

@@ -640,22 +640,28 @@ enum NvKmsInputColorRange {
* If DEFAULT is provided, driver will assume full range for RGB formats
* and limited range for YUV formats.
*/
NVKMS_INPUT_COLORRANGE_DEFAULT = 0,
NVKMS_INPUT_COLOR_RANGE_DEFAULT = 0,
NVKMS_INPUT_COLORRANGE_LIMITED = 1,
NVKMS_INPUT_COLOR_RANGE_LIMITED = 1,
NVKMS_INPUT_COLORRANGE_FULL = 2,
NVKMS_INPUT_COLOR_RANGE_FULL = 2,
};
enum NvKmsInputColorSpace {
/* Unknown colorspace; no de-gamma will be applied */
NVKMS_INPUT_COLORSPACE_NONE = 0,
/* Unknown colorspace */
NVKMS_INPUT_COLOR_SPACE_NONE = 0,
/* Linear, Rec.709 [-0.5, 7.5) */
NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1,
NVKMS_INPUT_COLOR_SPACE_BT601 = 1,
NVKMS_INPUT_COLOR_SPACE_BT709 = 2,
NVKMS_INPUT_COLOR_SPACE_BT2020 = 3,
NVKMS_INPUT_COLOR_SPACE_BT2100 = NVKMS_INPUT_COLOR_SPACE_BT2020,
/* PQ, Rec.2020 unity */
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
NVKMS_INPUT_COLOR_SPACE_SCRGB = 4
};
enum NvKmsInputTf {
NVKMS_INPUT_TF_LINEAR = 0,
NVKMS_INPUT_TF_PQ = 1
};
enum NvKmsOutputColorimetry {

49
kernel-open/common/inc/nvkms-kapi.h
View File

@@ -24,8 +24,10 @@
#if !defined(__NVKMS_KAPI_H__)
#include "nvtypes.h"
#include "nv_mig_types.h"
#include "nv-gpu-info.h"
#include "nv_dpy_id.h"
#include "nvkms-api-types.h"
#include "nvkms-format.h"
@@ -173,12 +175,18 @@ struct NvKmsKapiDeviceResourcesInfo {
NvBool supportsSyncpts;
NvBool requiresVrrSemaphores;
NvBool supportsInputColorRange;
NvBool supportsInputColorSpace;
} caps;
NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX];
NvBool supportsICtCp[NVKMS_KAPI_LAYER_MAX];
struct NvKmsKapiLutCaps lutCaps;
NvU64 vtFbBaseAddress;
NvU64 vtFbSize;
};
#define NVKMS_KAPI_LAYER_MASK(layerType) (1 << (layerType))
@@ -204,6 +212,7 @@ struct NvKmsKapiConnectorInfo {
NvU32 numIncompatibleConnectors;
NvKmsKapiConnector incompatibleConnectorHandles[NVKMS_KAPI_MAX_CONNECTORS];
NVDpyIdList dynamicDpyIdList;
};
struct NvKmsKapiStaticDisplayInfo {
@@ -222,6 +231,8 @@ struct NvKmsKapiStaticDisplayInfo {
NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS];
NvU32 headMask;
NvBool isDpMST;
};
struct NvKmsKapiSyncParams {
@@ -260,7 +271,8 @@ struct NvKmsKapiLayerConfig {
NvBool enabled;
} hdrMetadata;
enum NvKmsOutputTf tf;
enum NvKmsInputTf inputTf;
enum NvKmsOutputTf outputTf;
NvU8 minPresentInterval;
NvBool tearing;
@@ -272,6 +284,7 @@ struct NvKmsKapiLayerConfig {
NvU16 dstWidth, dstHeight;
enum NvKmsInputColorSpace inputColorSpace;
enum NvKmsInputColorRange inputColorRange;
struct {
NvBool enabled;
@@ -315,7 +328,10 @@ struct NvKmsKapiLayerRequestedConfig {
NvBool dstXYChanged : 1;
NvBool dstWHChanged : 1;
NvBool cscChanged : 1;
NvBool tfChanged : 1;
NvBool inputTfChanged : 1;
NvBool outputTfChanged : 1;
NvBool inputColorSpaceChanged : 1;
NvBool inputColorRangeChanged : 1;
NvBool hdrMetadataChanged : 1;
NvBool matrixOverridesChanged : 1;
NvBool ilutChanged : 1;
@@ -481,6 +497,8 @@ struct NvKmsKapiEvent {
struct NvKmsKapiAllocateDeviceParams {
/* [IN] GPU ID obtained from enumerateGpus() */
NvU32 gpuId;
/* [IN] MIG device if requested */
MIGDeviceId migDevice;
/* [IN] Private data of device allocator */
void *privateData;
@@ -563,6 +581,11 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {
typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);
struct NvKmsKapiGpuInfo {
nv_gpu_info_t gpuInfo;
MIGDeviceId migDevice;
};
struct NvKmsKapiFunctionsTable {
/*!
@@ -586,7 +609,7 @@ struct NvKmsKapiFunctionsTable {
*
* \return Count of enumerated gpus.
*/
NvU32 (*enumerateGpus)(nv_gpu_info_t *gpuInfo);
NvU32 (*enumerateGpus)(struct NvKmsKapiGpuInfo *kapiGpuInfo);
/*!
* Allocate an NVK device using which you can query/allocate resources on
@@ -1559,6 +1582,26 @@ struct NvKmsKapiFunctionsTable {
NvS32 index
);
/*!
* Check or wait on a head's LUT notifier.
*
* \param [in] device A device allocated using allocateDevice().
*
* \param [in] head The head to check for LUT completion.
*
* \param [in] waitForCompletion If true, wait for the notifier in NvKms
* before returning.
*
* \param [out] complete Returns whether the notifier has completed.
*/
NvBool
(*checkLutNotifier)
(
struct NvKmsKapiDevice *device,
NvU32 head,
NvBool waitForCompletion
);
/*
* Notify NVKMS that the system's framebuffer console has been disabled and
* the reserved allocation for the old framebuffer console can be unmapped.

14
kernel-open/common/inc/nvmisc.h
View File

@@ -701,11 +701,6 @@ nvPrevPow2_U64(const NvU64 x )
} \
}
//
// Bug 4851259: Newly added functions must be hidden from certain HS-signed
// ucode compilers to avoid signature mismatch.
//
#ifndef NVDEC_1_0
/*!
* Returns the position of nth set bit in the given mask.
*
@@ -735,8 +730,6 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
return -1;
}
#endif // NVDEC_1_0
//
// Size to use when declaring variable-sized arrays
//
@@ -780,12 +773,15 @@ nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
// Returns the offset (in bytes) of 'member' in struct 'type'.
#ifndef NV_OFFSETOF
#if defined(__GNUC__) && (__GNUC__ > 3)
#define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
#define NV_OFFSETOF(type, member) ((NvUPtr) __builtin_offsetof(type, member))
#else
#define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
#define NV_OFFSETOF(type, member) ((NvUPtr) &(((type *)0)->member))
#endif
#endif
// Given a pointer and the member it is of the parent struct, return a pointer to the parent struct
#define NV_CONTAINEROF(ptr, type, member) ((type *) (((NvUPtr) ptr) - NV_OFFSETOF(type, member)))
//
// Performs a rounded division of b into a (unsigned). For SIGNED version of
// NV_ROUNDED_DIV() macro check the comments in bug 769777.

7
kernel-open/common/inc/nvstatuscodes.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -159,7 +159,11 @@ NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabri
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed")
NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed")
NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
NV_STATUS_CODE(NV_ERR_THRESHOLD_CROSSED, 0x00000085, "A fatal threshold has been crossed")
NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occurred while trying to retire a resource")
NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabric state cached by the driver is out of sync")
NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full")
NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
@@ -170,5 +174,6 @@ NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More
NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do")
NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found")
NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range")
NV_STATUS_CODE(NV_WARN_THRESHOLD_CROSSED, 0x00010009, "WARNING Threshold has been crossed")
#endif /* SDK_NVSTATUSCODES_H */

1
kernel-open/common/inc/os-interface.h
View File

@@ -229,6 +229,7 @@ extern NvU64 os_page_mask;
extern NvU8 os_page_shift;
extern NvBool os_cc_enabled;
extern NvBool os_cc_sev_snp_enabled;
extern NvBool os_cc_sme_enabled;
extern NvBool os_cc_snp_vtom_enabled;
extern NvBool os_cc_tdx_enabled;
extern NvBool os_dma_buf_enabled;

387
kernel-open/common/inc/os_dsi_panel_props.h Normal file
View File

@@ -0,0 +1,387 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OS_DSI_PANEL_PARAMS_H_
#define _OS_DSI_PANEL_PARAMS_H_
#define DSI_GENERIC_LONG_WRITE 0x29
#define DSI_DCS_LONG_WRITE 0x39
#define DSI_GENERIC_SHORT_WRITE_1_PARAMS 0x13
#define DSI_GENERIC_SHORT_WRITE_2_PARAMS 0x23
#define DSI_DCS_WRITE_0_PARAM 0x05
#define DSI_DCS_WRITE_1_PARAM 0x15
#define DSI_DCS_READ_PARAM 0x06
#define DSI_DCS_COMPRESSION_MODE 0x07
#define DSI_DCS_PPS_LONG_WRITE 0x0A
#define DSI_DCS_SET_ADDR_MODE 0x36
#define DSI_DCS_EXIT_SLEEP_MODE 0x11
#define DSI_DCS_ENTER_SLEEP_MODE 0x10
#define DSI_DCS_SET_DISPLAY_ON 0x29
#define DSI_DCS_SET_DISPLAY_OFF 0x28
#define DSI_DCS_SET_TEARING_EFFECT_OFF 0x34
#define DSI_DCS_SET_TEARING_EFFECT_ON 0x35
#define DSI_DCS_NO_OP 0x0
#define DSI_NULL_PKT_NO_DATA 0x9
#define DSI_BLANKING_PKT_NO_DATA 0x19
#define DSI_DCS_SET_COMPRESSION_METHOD 0xC0
/* DCS commands for command mode */
#define DSI_ENTER_PARTIAL_MODE 0x12
#define DSI_SET_PIXEL_FORMAT 0x3A
#define DSI_AREA_COLOR_MODE 0x4C
#define DSI_SET_PARTIAL_AREA 0x30
#define DSI_SET_PAGE_ADDRESS 0x2B
#define DSI_SET_ADDRESS_MODE 0x36
#define DSI_SET_COLUMN_ADDRESS 0x2A
#define DSI_WRITE_MEMORY_START 0x2C
#define DSI_WRITE_MEMORY_CONTINUE 0x3C
#define PKT_ID0(id) ((((id) & 0x3f) << 3) | \
(((DSI_ENABLE) & 0x1) << 9))
#define PKT_LEN0(len) (((len) & 0x7) << 0)
#define PKT_ID1(id) ((((id) & 0x3f) << 13) | \
(((DSI_ENABLE) & 0x1) << 19))
#define PKT_LEN1(len) (((len) & 0x7) << 10)
#define PKT_ID2(id) ((((id) & 0x3f) << 23) | \
(((DSI_ENABLE) & 0x1) << 29))
#define PKT_LEN2(len) (((len) & 0x7) << 20)
#define PKT_ID3(id) ((((id) & 0x3f) << 3) | \
(((DSI_ENABLE) & 0x1) << 9))
#define PKT_LEN3(len) (((len) & 0x7) << 0)
#define PKT_ID4(id) ((((id) & 0x3f) << 13) | \
(((DSI_ENABLE) & 0x1) << 19))
#define PKT_LEN4(len) (((len) & 0x7) << 10)
#define PKT_ID5(id) ((((id) & 0x3f) << 23) | \
(((DSI_ENABLE) & 0x1) << 29))
#define PKT_LEN5(len) (((len) & 0x7) << 20)
#define PKT_LP (((DSI_ENABLE) & 0x1) << 30)
#define NUMOF_PKT_SEQ 12
/* DSI pixel data format, enum values should match with dt-bindings in tegra-panel.h */
typedef enum
{
DSI_PIXEL_FORMAT_16BIT_P,
DSI_PIXEL_FORMAT_18BIT_P,
DSI_PIXEL_FORMAT_18BIT_NP,
DSI_PIXEL_FORMAT_24BIT_P,
DSI_PIXEL_FORMAT_8BIT_DSC,
DSI_PIXEL_FORMAT_12BIT_DSC,
DSI_PIXEL_FORMAT_16BIT_DSC,
DSI_PIXEL_FORMAT_10BIT_DSC,
DSI_PIXEL_FORMAT_30BIT_P,
DSI_PIXEL_FORMAT_36BIT_P,
} DSIPIXELFORMAT;
/* DSI virtual channel number */
typedef enum
{
DSI_VIRTUAL_CHANNEL_0,
DSI_VIRTUAL_CHANNEL_1,
DSI_VIRTUAL_CHANNEL_2,
DSI_VIRTUAL_CHANNEL_3,
} DSIVIRTUALCHANNEL;
/* DSI transmit method for video data */
typedef enum
{
DSI_VIDEO_TYPE_VIDEO_MODE,
DSI_VIDEO_TYPE_COMMAND_MODE,
} DSIVIDEODATAMODE;
/* DSI HS clock mode */
typedef enum
{
DSI_VIDEO_CLOCK_CONTINUOUS,
DSI_VIDEO_CLOCK_TX_ONLY,
} DSICLOCKMODE;
/* DSI burst mode setting in video mode. Each mode is assigned with a
* fixed value. The rationale behind this is to avoid change of these
* values, since the calculation of dsi clock depends on them. */
typedef enum
{
DSI_VIDEO_NON_BURST_MODE = 0,
DSI_VIDEO_NON_BURST_MODE_WITH_SYNC_END = 1,
DSI_VIDEO_BURST_MODE_LOWEST_SPEED = 2,
DSI_VIDEO_BURST_MODE_LOW_SPEED = 3,
DSI_VIDEO_BURST_MODE_MEDIUM_SPEED = 4,
DSI_VIDEO_BURST_MODE_FAST_SPEED = 5,
DSI_VIDEO_BURST_MODE_FASTEST_SPEED = 6,
} DSIVIDEOBURSTMODE;
/* DSI Ganged Mode */
typedef enum
{
DSI_GANGED_SYMMETRIC_LEFT_RIGHT = 1,
DSI_GANGED_SYMMETRIC_EVEN_ODD = 2,
DSI_GANGED_SYMMETRIC_LEFT_RIGHT_OVERLAP = 3,
} DSIGANGEDTYPE;
typedef enum
{
DSI_LINK0,
DSI_LINK1,
} DSILINKNUM;
/* DSI Command Packet type */
typedef enum
{
DSI_PACKET_CMD,
DSI_DELAY_MS,
DSI_GPIO_SET,
DSI_SEND_FRAME,
DSI_PACKET_VIDEO_VBLANK_CMD,
DSI_DELAY_US,
} DSICMDPKTTYPE;
/* DSI Phy type */
typedef enum
{
DSI_DPHY,
DSI_CPHY,
} DSIPHYTYPE;
enum {
DSI_GPIO_LCD_RESET,
DSI_GPIO_PANEL_EN,
DSI_GPIO_PANEL_EN_1,
DSI_GPIO_BL_ENABLE,
DSI_GPIO_BL_PWM,
DSI_GPIO_AVDD_AVEE_EN,
DSI_GPIO_VDD_1V8_LCD_EN,
DSI_GPIO_TE,
DSI_GPIO_BRIDGE_EN_0,
DSI_GPIO_BRIDGE_EN_1,
DSI_GPIO_BRIDGE_REFCLK_EN,
DSI_N_GPIO_PANEL, /* add new gpio above this entry */
};
enum
{
DSI_DISABLE,
DSI_ENABLE,
};
typedef struct
{
NvU8 cmd_type;
NvU8 data_id;
union
{
NvU16 data_len;
NvU16 delay_ms;
NvU16 delay_us;
NvU32 gpio;
NvU16 frame_cnt;
struct
{
NvU8 data0;
NvU8 data1;
} sp;
} sp_len_dly;
NvU32 *pdata;
NvU8 link_id;
NvBool club_cmd;
} DSI_CMD, *PDSICMD;
typedef struct
{
NvU16 t_hsdexit_ns;
NvU16 t_hstrail_ns;
NvU16 t_datzero_ns;
NvU16 t_hsprepare_ns;
NvU16 t_hsprebegin_ns;
NvU16 t_hspost_ns;
NvU16 t_clktrail_ns;
NvU16 t_clkpost_ns;
NvU16 t_clkzero_ns;
NvU16 t_tlpx_ns;
NvU16 t_clkprepare_ns;
NvU16 t_clkpre_ns;
NvU16 t_wakeup_ns;
NvU16 t_taget_ns;
NvU16 t_tasure_ns;
NvU16 t_tago_ns;
} DSI_PHY_TIMING_IN_NS;
typedef struct
{
NvU32 hActive;
NvU32 vActive;
NvU32 hFrontPorch;
NvU32 vFrontPorch;
NvU32 hBackPorch;
NvU32 vBackPorch;
NvU32 hSyncWidth;
NvU32 vSyncWidth;
NvU32 hPulsePolarity;
NvU32 vPulsePolarity;
NvU32 pixelClkRate;
} DSITIMINGS, *PDSITIMINGS;
typedef struct
{
NvU8 n_data_lanes; /* required */
NvU8 pixel_format; /* required */
NvU8 refresh_rate; /* required */
NvU8 rated_refresh_rate;
NvU8 panel_reset; /* required */
NvU8 virtual_channel; /* required */
NvU8 dsi_instance;
NvU16 dsi_panel_rst_gpio;
NvU16 dsi_panel_bl_en_gpio;
NvU16 dsi_panel_bl_pwm_gpio;
NvU16 even_odd_split_width;
NvU8 controller_vs;
NvBool panel_has_frame_buffer; /* required*/
/* Deprecated. Use DSI_SEND_FRAME panel command instead. */
NvBool panel_send_dc_frames;
DSI_CMD *dsi_init_cmd; /* required */
NvU16 n_init_cmd; /* required */
NvU32 *dsi_init_cmd_array;
NvU32 init_cmd_array_size;
NvBool sendInitCmdsEarly;
DSI_CMD *dsi_early_suspend_cmd;
NvU16 n_early_suspend_cmd;
NvU32 *dsi_early_suspend_cmd_array;
NvU32 early_suspend_cmd_array_size;
DSI_CMD *dsi_late_resume_cmd;
NvU16 n_late_resume_cmd;
NvU32 *dsi_late_resume_cmd_array;
NvU32 late_resume_cmd_array_size;
DSI_CMD *dsi_postvideo_cmd;
NvU16 n_postvideo_cmd;
NvU32 *dsi_postvideo_cmd_array;
NvU32 postvideo_cmd_array_size;
DSI_CMD *dsi_suspend_cmd; /* required */
NvU16 n_suspend_cmd; /* required */
NvU32 *dsi_suspend_cmd_array;
NvU32 suspend_cmd_array_size;
NvU8 video_data_type; /* required */
NvU8 video_clock_mode;
NvU8 video_burst_mode;
NvU8 ganged_type;
NvU16 ganged_overlap;
NvBool ganged_swap_links;
NvBool ganged_write_to_all_links;
NvU8 split_link_type;
NvU8 suspend_aggr;
NvU16 panel_buffer_size_byte;
NvU16 panel_reset_timeout_msec;
NvBool hs_cmd_mode_supported;
NvBool hs_cmd_mode_on_blank_supported;
NvBool enable_hs_clock_on_lp_cmd_mode;
NvBool no_pkt_seq_eot; /* 1st generation panel may not
* support eot. Don't set it for
* most panels.*/
const NvU32 *pktSeq;
NvU32 *pktSeq_array;
NvU32 pktSeq_array_size;
NvBool skip_dsi_pkt_header;
NvBool power_saving_suspend;
NvBool suspend_stop_stream_late;
NvBool dsi2lvds_bridge_enable;
NvBool dsi2edp_bridge_enable;
NvU32 max_panel_freq_khz;
NvU32 lp_cmd_mode_freq_khz;
NvU32 lp_read_cmd_mode_freq_khz;
NvU32 hs_clk_in_lp_cmd_mode_freq_khz;
NvU32 burst_mode_freq_khz;
NvU32 fpga_freq_khz;
NvU32 te_gpio;
NvBool te_polarity_low;
NvBool dsiEnVRR;
NvBool dsiVrrPanelSupportsTe;
NvBool dsiForceSetTePin;
int panel_gpio[DSI_N_GPIO_PANEL];
NvBool panel_gpio_populated;
NvU32 dpd_dsi_pads;
DSI_PHY_TIMING_IN_NS phyTimingNs;
NvU8 *bl_name;
NvBool lp00_pre_panel_wakeup;
NvBool ulpm_not_supported;
NvBool use_video_host_fifo_for_cmd;
NvBool dsi_csi_loopback;
NvBool set_max_timeout;
NvBool use_legacy_dphy_core;
// Swap P/N pins polarity of all data lanes
NvBool swap_data_lane_polarity;
// Swap P/N pins polarity of clock lane
NvBool swap_clock_lane_polarity;
// Reverse clock polarity for partition A/B. 1st SOT bit goes on negedge of Clock lane
NvBool reverse_clock_polarity;
// DSI Lane Crossbar. Allocating xbar array for max number of lanes
NvBool lane_xbar_exists;
NvU32 lane_xbar_ctrl[8];
NvU32 refresh_rate_adj;
NvU8 dsiPhyType;
NvBool en_data_scrambling;
NvU32 dsipll_vco_rate_hz;
NvU32 dsipll_clkoutpn_rate_hz;
NvU32 dsipll_clkouta_rate_hz;
NvU32 vpll0_rate_hz;
DSITIMINGS dsiTimings;
// DSC Parameters
NvBool dsiDscEnable;
NvU32 dsiDscBpp;
NvU32 dsiDscNumSlices;
NvU32 dsiDscSliceWidth;
NvU32 dsiDscSliceHeight;
NvBool dsiDscEnBlockPrediction;
NvBool dsiDscEnDualDsc;
NvU32 dsiDscDecoderMajorVersion;
NvU32 dsiDscDecoderMinorVersion;
NvBool dsiDscUseCustomPPS;
NvU32 dsiDscCustomPPSData[32];
// Driver allocates memory for PPS cmd to be sent to Panel
NvBool ppsCmdMemAllocated;
} DSI_PANEL_INFO;
#endif

32
kernel-open/common/inc/os_gpio.h Normal file
View File

@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef _OS_GPIO_H_
#define _OS_GPIO_H_
typedef enum
{
NV_OS_GPIO_FUNC_HOTPLUG_A,
NV_OS_GPIO_FUNC_HOTPLUG_B,
} NV_OS_GPIO_FUNC_NAMES;
#endif

2
kernel-open/common/inc/rm-gpu-ops.h
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@@ -83,7 +83,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvg
NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool);
NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, const nvgpuAccessCntrConfig_t *);
NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32);
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32, NvU64 *);
NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
NV_STATUS NV_API_CALL rm_gpu_ops_get_nvlink_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuNvlinkInfo_t);
NV_STATUS NV_API_CALL rm_gpu_ops_p2p_object_create(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuDeviceHandle_t, NvHandle *);