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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-09 01:29:57 +00:00
575.51.02
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@@ -250,15 +250,6 @@ static inline NvBool uvm_ranges_overlap(NvU64 a_start, NvU64 a_end, NvU64 b_star
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return a_end >= b_start && b_end >= a_start;
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}
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static int debug_mode(void)
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{
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#ifdef DEBUG
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return 1;
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#else
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return 0;
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#endif
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}
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static inline void kmem_cache_destroy_safe(struct kmem_cache **ppCache)
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{
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if (ppCache)
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@@ -336,22 +327,6 @@ typedef struct
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NvHandle user_object;
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} uvm_rm_user_object_t;
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typedef enum
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{
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UVM_FD_UNINITIALIZED,
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UVM_FD_INITIALIZING,
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UVM_FD_VA_SPACE,
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UVM_FD_MM,
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UVM_FD_COUNT
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} uvm_fd_type_t;
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// This should be large enough to fit the valid values from uvm_fd_type_t above.
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// Note we can't use order_base_2(UVM_FD_COUNT) to define this because our code
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// coverage tool fails due when the preprocessor expands that to a huge mess of
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// ternary operators.
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#define UVM_FD_TYPE_BITS 2
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#define UVM_FD_TYPE_MASK ((1UL << UVM_FD_TYPE_BITS) - 1)
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// Macro used to compare two values for types that support less than operator.
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// It returns -1 if a < b, 1 if a > b and 0 if a == 0
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#define UVM_CMP_DEFAULT(a,b) \
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@@ -374,37 +349,13 @@ typedef enum
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// file. A NULL input returns false.
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bool uvm_file_is_nvidia_uvm(struct file *filp);
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// Returns the type of data filp->private_data contains to and if ptr_val !=
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// NULL returns the value of the pointer.
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uvm_fd_type_t uvm_fd_type(struct file *filp, void **ptr_val);
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// Returns the pointer stored in filp->private_data if the type
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// matches, otherwise returns NULL.
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void *uvm_fd_get_type(struct file *filp, uvm_fd_type_t type);
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// Reads the first word in the supplied struct page.
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static inline void uvm_touch_page(struct page *page)
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{
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char *mapping;
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UVM_ASSERT(page);
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mapping = (char *) kmap(page);
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(void)READ_ONCE(*mapping);
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kunmap(page);
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}
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// Like uvm_file_is_nvidia_uvm(), but further requires that the input file
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// represent a UVM VA space (has fd type UVM_FD_VA_SPACE).
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bool uvm_file_is_nvidia_uvm_va_space(struct file *filp);
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// Return true if the VMA is one used by UVM managed allocations.
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bool uvm_vma_is_managed(struct vm_area_struct *vma);
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static bool uvm_platform_uses_canonical_form_address(void)
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{
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if (NVCPU_IS_PPC64LE)
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return false;
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return true;
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}
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// Similar to the GPU MMU HAL num_va_bits(), it returns the CPU's num_va_bits().
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static NvU32 uvm_cpu_num_va_bits(void)
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{
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@@ -420,7 +371,7 @@ static void uvm_get_unaddressable_range(NvU32 num_va_bits, NvU64 *first, NvU64 *
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// Maxwell GPUs (num_va_bits == 40b) do not support canonical form address
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// even when plugged into platforms using it.
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if (uvm_platform_uses_canonical_form_address() && num_va_bits > 40) {
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if (num_va_bits > 40) {
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*first = 1ULL << (num_va_bits - 1);
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*outer = (NvU64)((NvS64)(1ULL << 63) >> (64 - num_va_bits));
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}
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