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575.51.02

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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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22
src/common/inc/nvBldVer.h
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@@ -36,26 +36,26 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r572_77
#define NV_BUILD_BRANCH r575_92
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r572_77
#define NV_PUBLIC_BRANCH r575_92
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r572_77-389"
#define NV_BUILD_CHANGELIST_NUM (35826456)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r575/r575_92-147"
#define NV_BUILD_CHANGELIST_NUM (35813551)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r572_77-389"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35826456)
#define NV_BUILD_NAME "rel/gpu_drv/r575/r575_92-147"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35813551)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r572_77-4"
#define NV_BUILD_CHANGELIST_NUM (35784913)
#define NV_BUILD_BRANCH_VERSION "r575_92-4"
#define NV_BUILD_CHANGELIST_NUM (35813551)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "572.95"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35784913)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#define NV_BUILD_NAME "575.98"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35813551)
#define NV_BUILD_BRANCH_BASE_VERSION R575
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.133.20"
#define NV_VERSION_STRING "575.51.02"
#else

40
src/common/inc/nv_mig_types.h Normal file
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@@ -0,0 +1,40 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_MIG_TYPES_H__
#define __NV_MIG_TYPES_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
typedef NvU32 MIGDeviceId;
#define NO_MIG_DEVICE 0L
#ifdef __cplusplus
}
#endif
#endif /* __NV_MIG_TYPES_H__ */

97
src/common/inc/nv_smg.h Normal file
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@@ -0,0 +1,97 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_SMG_H__
#define __NV_SMG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "nvlimits.h"
#include "nvrmcontext.h"
#include "nv_mig_types.h"
/*
* In the context of SMG a MIG device description is the global identity or
* fingerprint for one MIG device partition that the system has available.
* These are queried through RM and thus they will be the same in
* kernelspace and userspace, and remain immutable and cached for the
* lifetime of the process or kernel module.
*
* For now, the graphics driver does NOT support SMG if the MIG partitions
* change on the fly. RM supports reconfiguring partitions that are not in
* use but, for now, the kernel and userspace graphics drivers expect the
* topology of all physical and MIG devices to remain unchanged throughout
* so that they can agree on the same set of known MIG devices. This is not
* an unreasonable requirement.
*
* Each MIG device description is referred to by a semi-opaque MIGDeviceId.
* The device id is actually the 0-based index to the table of MIG device
* descriptions but with bits flipped so that null value is an invalid
* device. This makes boolean interpretation work more naturally and makes
* structs from calloc() initialize to an invalid device by default.
*/
typedef struct nvMIGDeviceDescriptionRec {
/* The globally unique MIG device ID */
MIGDeviceId migDeviceId;
/* RM sub/device instance of the physical device hosting the MIG device */
NvU32 deviceInstance;
NvU32 subDeviceInstance;
/* These three uniquely identify a particular MIG device */
NvU32 gpuId;
NvU32 gpuInstanceId;
NvU32 computeInstanceId;
/* Whether this device is accessible to the calling process */
NvBool migAccessOk;
/* MIG exec partition UUID string */
char migUuid[NV_MIG_DEVICE_UUID_STR_LENGTH];
} nvMIGDeviceDescription;
NvBool nvSMGSubscribeSubDevToPartition(nvRMContextPtr rmctx,
NvU32 subdevHandle,
MIGDeviceId migDevice,
NvU32 gpuInstSubscriptionHdl,
NvU32 computeInstSubscriptionHdl);
NvU32 nvSMGGetDeviceByUUID(nvRMContextPtr rmctx,
const char *migUuid,
const nvMIGDeviceDescription **uniDev);
NvU32 nvSMGGetDeviceById(nvRMContextPtr rmctx,
MIGDeviceId migDev,
const nvMIGDeviceDescription **uniDev);
NvU32 nvSMGGetDeviceList(nvRMContextPtr rmctx,
nvMIGDeviceDescription **devices,
NvU32 *deviceCount);
NvU32 nvSMGGetDefaultDeviceForDeviceInstance(nvRMContextPtr rmctx,
NvU32 deviceInstance,
const nvMIGDeviceDescription **uniDev);
#ifdef __cplusplus
}
#endif
#endif /* __NV_SMG_H__ */

2
src/common/inc/nvlog_defs.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2012-2021 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2012-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

73
src/common/inc/nvrmcontext.h Normal file
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@@ -0,0 +1,73 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NVRMCONTEXT_H__
#define __NVRMCONTEXT_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
#include "rs_access.h"
/*
* An RM wrapping structure to make RMAPI accessible from the RM abstraction
* in one location/context to other locations/contexts in a unified way.
*
* An nvRMContext can be created on the fly or stored preinitialized in
* objects. It has no mutable state, it's just a collection of static
* parameters to make access to RM possible.
*
* This is a C interface for maximal compatibility, and it is intended to be
* used both in kernel and userspace.
*
*/
typedef struct nvRMContextRec nvRMContext, *nvRMContextPtr;
struct nvRMContextRec {
/*
* The RM client of the calling context. In normal circumstances, the
* callee should pass this as the hClient argument.
*/
NvU32 clientHandle;
/* User data field for the caller: to be freely used. */
void *owner;
/*
* RMAPI function wrappers: it's enough to only fill in those functions
* that the caller will know that will be needed in each case. For now,
* we list function pointers needed by nv_smg.c -- feel free to add more
* RMAPI functions when necessary.
*/
NvU32 (*allocRoot) (nvRMContextPtr rmctx, NvU32 *phClient);
NvU32 (*alloc) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hParent, NvU32 hObject, NvU32 hClass, void *pAllocParms);
NvU32 (*free) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hParent, NvU32 hObject);
NvU32 (*control) (nvRMContextPtr rmctx, NvU32 hClient, NvU32 hObject, NvU32 cmd, void *pParams, NvU32 paramsSize);
};
#ifdef __cplusplus
} // extern "C"
#endif
#endif // __NVRMCONTEXT_H__

4
src/common/inc/swref/published/ampere/ga100/dev_fuse.h
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@@ -23,6 +23,10 @@
#ifndef __ga100_dev_fuse_h__
#define __ga100_dev_fuse_h__
#define NV_FUSE_FEATURE_READOUT 0x00823814 /* R--4R */
#define NV_FUSE_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
#define NV_FUSE_FEATURE_READOUT_ECC_DRAM_ENABLED 0x00000001 /* R---V */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */

3
src/common/inc/swref/published/ampere/ga100/dev_vm.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -128,5 +128,6 @@
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#endif // __ga100_dev_vm_h__

2
src/common/inc/swref/published/ampere/ga10b/dev_ram.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/common/inc/swref/published/blackwell/gb100/dev_boot_addendum.h
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@@ -31,5 +31,8 @@
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED 1:1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_FALSE 0x0
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED 6:6
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_NVLE_MODE_ENABLED_FALSE 0x0
#endif // gb100_dev_boot_addendum_h

2
src/common/inc/swref/published/blackwell/gb100/dev_fsp_pri.h
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@@ -34,4 +34,6 @@
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_MNOC_BASE (0x008f1e00) /* -W-4A */
#endif // __gb100_dev_fsp_pri_h__

79
src/common/inc/swref/published/blackwell/gb100/dev_mnoc_pri_zb.h Normal file
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@@ -0,0 +1,79 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_mnoc_pri_zb_h__
#define __gb100_dev_mnoc_pri_zb_h__
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX(i) (0x00000104 + (i)*0xC) /* RW-4A */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_SENDMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_SIZE 19:0 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_SIZE_INIT 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY 24:24 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_MESSAGE_READY_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR 25:25 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_ERR_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE 30:30 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS 31:31 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS__ONWRITE "oneToClear" /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_CLEARED 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_SET 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_SENDMBOX_INTR_STATUS_W1CLR 0x00000001 /* -W--V */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX(i) (0x00000108 + (i)*0xC) /* R--4A */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_SENDMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX_RDATA 31:0 /* R-IVF */
#define NV_MNOC_ZB_PRI_RDATA_0_SENDMBOX_RDATA_INIT 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX(i) (0x00000184 + (i)*0xC) /* RW-4A */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_RECEIVEMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_SIZE 19:0 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_SIZE_INIT 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_TRIGGER 20:20 /* -WXVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_MESSAGE_TRIGGER_SET 0x1 /* -W--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY 24:24 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_RECEIVE_READY_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR 25:25 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_ERR_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE 26:26 /* R-IVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE_FALSE 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_CREDIT_AVAILABLE_TRUE 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE 30:30 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE_DISABLED 0x00000000 /* RWI-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_ENABLE_ENABLED 0x00000001 /* RW--V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS 31:31 /* RWIVF */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS__ONWRITE "oneToClear" /* */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_CLEARED 0x00000000 /* R-I-V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_SET 0x00000001 /* R---V */
#define NV_MNOC_ZB_PRI_MESSAGE_INFO_0_RECEIVEMBOX_INTR_STATUS_W1CLR 0x00000001 /* -W--V */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX(i) (0x00000188 + (i)*0xC) /* -W-4A */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX__SIZE_1 4 /* */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX__PRIV_LEVEL_MASK NV_MNOC_ZB_PRI_RECEIVEMBOX_PRIV_LEVEL_MASK /* */
#define NV_MNOC_ZB_PRI_WDATA_0_RECEIVEMBOX_WDATA 31:0 /* -WXVF */
#endif // __gb100_dev_mnoc_pri_zb_h__

6
src/common/inc/swref/published/blackwell/gb100/dev_pcfg_pf0.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -90,7 +90,11 @@
#define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00001e98 /* R-I-V */
#define NV_PF0_DVSEC0_CXL_HEADER_1_DVSEC_LENGTH_DEFAULT 0x0000003c /* R-I-V */
#define NV_PF0_DVSEC0_CAPABILITY_HEADER 0x00000af0 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1 0x00000af4 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_LENGTH_DEFAULT 0x0000001c /* R-I-V */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL 0x00000af8 /* R--4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_BAR_FIREWALL_STATUS 20:20 /* R-IVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_BAR_FIREWALL_STATUS_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DVSEC8_CAP_HEADER 0x000003b8 /* R--4R */
#define NV_PF0_DVSEC8_REGISTER_BLOCK_3_REGISTER_OFFSET_HIGH 0x000003d8 /* R--4R */
#define NV_PF0_DVSEC8_HEADER_1_DVSEC_VENDOR_ID_DEFAULT 0x00001e98 /* R-I-V */

30
src/common/inc/swref/published/blackwell/gb100/dev_vm_addendum.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_vm_addendum_h__
#define __gb100_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb100_dev_vm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb102_dev_vm_h__
#define __gb102_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb102_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb102_dev_vm_addendum_h__
#define __gb102_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb102_dev_vm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb10b_dev_ce_base_h__
#define __gb10b_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb10b_dev_ce_base_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb110_dev_vm_h__
#define __gb110_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb110_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb110_dev_vm_addendum_h__
#define __gb110_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb110_dev_vm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb112_dev_vm_h__
#define __gb112_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#endif // __gb112_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb112_dev_vm_addendum_h__
#define __gb112_dev_vm_addendum_h__
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO
#define NV_VIRTUAL_FUNCTION_PRIV_NON_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT_PTR NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE
#define NV_VIRTUAL_FUNCTION_PRIV_REPLAYABLE_FAULT_SHADOW_BUFFER_PUT NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI
#endif // __gb112_dev_vm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_boot_h__
#define __gb20b_dev_boot_h__
#define NV_PMC_SCRATCH_RESET_PLUS_2 0x000005e0 /* RW-4R */
#define NV_PMC_SCRATCH_RESET_PLUS_2__SAFETY "parity" /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2__PRIV_LEVEL_MASK 0x000005e4 /* */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_SCRATCH_RESET_PLUS_2_VALUE_INIT 0 /* RWB-V */
#define NV_SYSCTRL_SEC_FAULT 0x3:0x0 /* R---M */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_DCLS 2:2 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SEC2_L5_WDT 3:3 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_DCLS 4:4 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GSP_L5_WDT 5:5 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_DCLS 6:6 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_PMU_L5_WDT 7:7 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPMVDD_VMON 8:8 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_GPCVDD_VMON 9:9 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_SOC2GPU_SEC_FAULT_FUNCTION_LOCKDOWN_REQ 10:10 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_FUNCTION_LOCKDOWN 11:11 /* R-XUF */
#define NV_SYSCTRL_SEC_FAULT_BIT_POSITION_DEVICE_LOCKDOWN 12:12 /* R-XUF */
#endif // __gb20b_dev_boot_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_ce_base_h__
#define __gb20b_dev_ce_base_h__
#define NV_CE_BASE_GRCE_CONFIG__SIZE_1 1
#define NV_CE_BASE_PCE2LCE_CONFIG__SIZE_1 2
#define NV_CE_BASE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_BASE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb20b_dev_ce_base_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_mmu_h__
#define __gb20b_dev_mmu_h__
#define NV_MMU_PTE_KIND_INVALID 0x07 /* R---V */
#define NV_MMU_PTE_KIND_PITCH 0x00 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_PTE_KIND_Z16 0x1 /* R---V */
#define NV_MMU_PTE_KIND_S8 0x2 /* R---V */
#define NV_MMU_PTE_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_PTE_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE 0x8 /* R---V */
#define NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC 0x9 /* R---V */
#define NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC 0xA /* R---V */
#define NV_MMU_PTE_KIND_Z16_COMPRESSIBLE_DISABLE_PLC 0xB /* R---V */
#define NV_MMU_PTE_KIND_S8Z24_COMPRESSIBLE_DISABLE_PLC 0xC /* R---V */
#define NV_MMU_PTE_KIND_ZF32_X24S8_COMPRESSIBLE_DISABLE_PLC 0xD /* R---V */
#define NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC 0xE /* R---V */
#define NV_MMU_PTE_KIND_SMSKED_MESSAGE 0xF /* R---V */
#define NV_MMU_CLIENT_KIND 2:0 /* RWXVF */
#define NV_MMU_CLIENT_KIND_Z16 0x1 /* R---V */
#define NV_MMU_CLIENT_KIND_S8 0x2 /* R---V */
#define NV_MMU_CLIENT_KIND_S8Z24 0x3 /* R---V */
#define NV_MMU_CLIENT_KIND_ZF32_X24S8 0x4 /* R---V */
#define NV_MMU_CLIENT_KIND_Z24S8 0x5 /* R---V */
#define NV_MMU_CLIENT_KIND_GENERIC_MEMORY 0x6 /* R---V */
#define NV_MMU_CLIENT_KIND_INVALID 0x7 /* R---V */
#endif // __gb20b_dev_mmu_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_perf_h__
#define __gb20b_dev_perf_h__
#define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_2 2 /* */
#define NV_PERF_PMASYS_CBLOCK_BPC_CONFIG_SECURE__SIZE_1 2 /* */
#endif // __gb20b_dev_perf_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_sec_pri_h__
#define __gb20b_dev_sec_pri_h__
#define NV_PSEC_EMEMC(i) (0x00840ac0+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMC__SIZE_1 8 /* */
#define NV_PSEC_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PSEC_EMEMC_OFFS_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PSEC_EMEMC_BLK_INIT 0x00 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PSEC_EMEMC_AINCW_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCW_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCW_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PSEC_EMEMC_AINCR_INIT 0x0 /* RWI-V */
#define NV_PSEC_EMEMC_AINCR_TRUE 0x1 /* RW--V */
#define NV_PSEC_EMEMC_AINCR_FALSE 0x0 /* RW--V */
#define NV_PSEC_EMEMD(i) (0x00840ac4+(i)*8) /* RW-4A */
#define NV_PSEC_EMEMD__SIZE_1 8 /* */
#define NV_PSEC_EMEMD_DATA 31:0 /* RWXVF */
#define NV_PSEC_QUEUE_HEAD(i) (0x00840c00+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_HEAD__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_QUEUE_TAIL(i) (0x00840c04+(i)*8) /* RW-4A */
#define NV_PSEC_QUEUE_TAIL__SIZE_1 8 /* */
#define NV_PSEC_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
#define NV_PSEC_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_MSGQ_HEAD(i) (0x00840c80+(i)*8) /* RW-4A */
#define NV_PSEC_MSGQ_HEAD__SIZE_1 8 /* */
#define NV_PSEC_MSGQ_HEAD_VAL 31:0 /* RWIUF */
#define NV_PSEC_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PSEC_MSGQ_TAIL(i) (0x00840c84+(i)*8) /* RW-4A */
#define NV_PSEC_MSGQ_TAIL__SIZE_1 8 /* */
#define NV_PSEC_MSGQ_TAIL_VAL 31:0 /* RWIUF */
#define NV_PSEC_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb20b_dev_sec_pri_h__

36
src/common/inc/swref/published/blackwell/gb20b/dev_xtl_ep_pcfg_gpu.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2025 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb20b_dev_xtl_ep_pcfg_gpu_h__
#define __gb20b_dev_xtl_ep_pcfg_gpu_h__
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC 0x000002B4 /* R--4R */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC__SAFETY "parity" /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR 15:0 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_FAULT_ERROR_OVERRIDEABLE 0 /* */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS 22:16 /* R-CVF */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_INIT 0x00000000 /* R-C-V */
#define NV_EP_PCFG_GPU_VSEC_DEBUG_SEC_IFF_POS_OVERRIDEABLE 0 /* */
#endif // __gb20b_dev_xtl_ep_pcfg_gpu_h__

36
src/common/inc/swref/published/blackwell/gb20b/kind_macros.h Normal file
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@@ -0,0 +1,36 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GB20B_KIND_MACROS_H_INCLUDED
#define GB20B_KIND_MACROS_H_INCLUDED
#define KIND_INVALID(k) ( ((k) ==NV_MMU_CLIENT_KIND_INVALID))
#define PTEKIND_PITCH(k) ( ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define PTEKIND_COMPRESSIBLE(k) ( ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_DISALLOWS_PLC(k) ( !((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE))
#define PTEKIND_SUPPORTED(k) ( ((k) ==NV_MMU_PTE_KIND_INVALID)|| ((k) ==NV_MMU_PTE_KIND_PITCH)|| ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_S8Z24)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC)|| ((k) ==NV_MMU_PTE_KIND_SMSKED_MESSAGE))
#define KIND_Z(k) ( ((k) >=NV_MMU_CLIENT_KIND_Z16 && (k) <= NV_MMU_CLIENT_KIND_Z24S8))
#define PTEKIND_Z(k) ( ((k) >=NV_MMU_PTE_KIND_Z16 && (k) <= NV_MMU_PTE_KIND_Z24S8)|| ((k) >=NV_MMU_PTE_KIND_S8_COMPRESSIBLE_DISABLE_PLC && (k) <= NV_MMU_PTE_KIND_Z24S8_COMPRESSIBLE_DISABLE_PLC))
#define PTEKIND_GENERIC_MEMORY(k) ( ((k) ==NV_MMU_PTE_KIND_GENERIC_MEMORY)|| ((k) >=NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE && (k) <= NV_MMU_PTE_KIND_GENERIC_MEMORY_COMPRESSIBLE_DISABLE_PLC))
#endif // GB20B_KIND_MACROS_H_INCLUDED

140
src/common/inc/swref/published/disp/v03_00/dev_disp.h
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@@ -30,9 +30,149 @@
#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */
#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */
#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */
#define NV_PDISP_FE_DEBUG_CTL(i) (0x00610800+(i)*8) /* RW-4A */
#define NV_PDISP_FE_DEBUG_CTL__SIZE_1 73 /* */
#define NV_PDISP_FE_DEBUG_CTL_MODE 0:0 /* RWIVF */
#define NV_PDISP_FE_DEBUG_CTL_MODE_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */
#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */
#define NV_PDISP_FE_SW 0x00640FFF:0x00640000 /* RW--D */
#define NV_PDISP_SF_USER_0 0x006F03FF:0x006F0000 /* RW--D */
#define NV_UDISP_HASH_BASE 0x00000000 /* */

13
src/common/inc/swref/published/disp/v04_01/dev_disp.h
View File

@@ -43,4 +43,17 @@
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(i) (0x00611C00+(i)*4) /* R--4A */
#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING__SIZE_1 8 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING__SIZE_1 8 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_RESET 0x00000001 /* */
#endif // __v04_01_dev_disp_h__

6
src/common/inc/swref/published/disp/v05_01/dev_disp.h
View File

@@ -32,12 +32,6 @@
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */
#define NV_PDISP_POSTCOMP_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#define NV_PDISP_FE_INTR_RETRIGGER(i) (0x00611F30+(i)*4) /* RW-4A */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER 0:0 /* RWIVF */
#define NV_PDISP_FE_INTR_RETRIGGER_TRIGGER_NONE 0x00000000 /* RWI-V */

33
src/common/inc/swref/published/disp/v05_02/dev_disp.h Normal file
View File

@@ -0,0 +1,33 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __v05_02_dev_disp_h__
#define __v05_02_dev_disp_h__
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING(i) (0x00611EF0+(i)*4) /* RW-4A */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
#define NV_PDISP_FE_RM_INTR_EN1_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
#endif

6
src/common/inc/swref/published/nv_arch.h
View File

@@ -108,6 +108,10 @@
#define GPU_IMPLEMENTATION_GB10B 0x0B
#define GPU_IMPLEMENTATION_GB110 0x03
#define GPU_IMPLEMENTATION_GB112 0x04
#define GPU_IMPLEMENTATION_GB202 0x02
#define GPU_IMPLEMENTATION_GB203 0x03
@@ -120,6 +124,8 @@
#define GPU_IMPLEMENTATION_GB207 0x07
#define GPU_IMPLEMENTATION_GB20B 0x0B
#define GPU_IMPLEMENTATION_T124 0x00
#define GPU_IMPLEMENTATION_T132 0x00
#define GPU_IMPLEMENTATION_T210 0x00

30
src/common/inc/swref/published/volta/gv100/dev_graphics_nobundle.h Normal file
View File

@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gv100_dev_graphics_nobundle_h__
#define __gv100_dev_graphics_nobundle_h__
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT 0x00409660 /* R--4R */
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
#define NV_PGRAPH_PRI_FECS_FEATURE_READOUT_ECC_DRAM_ENABLED 0x1 /* R---V */
#endif // __gv100_dev_graphics_nobundle_h__