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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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575.51.02
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Bernhard Stoeckner
@@ -1911,6 +1911,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_MSCG 0x0009
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// Parameter/characteristics of Display ALPM
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
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@@ -2031,6 +2032,66 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
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/*!
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* Property specifies current state of the specified clock
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* i.e. Gated ot not Gated
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_STATUS (0x0004)
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/*!
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* @brief Parameter/characteristics of MSCG
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*
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* Following are the Parameter/characteristics for MSCG
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_INVALID (0x0000)
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/*!
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* Property specifies if DPS1 is supported
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_SUPPORT (0x0001)
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/*!
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* Property specifies if DPS2 is supported
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_SUPPORT (0x0002)
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/*!
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* Property specifies if MSCG is enabled
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* (This property allows Get/SET operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_ENABLED (0x0003)
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/*!
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* Property specifies the time(in US) for which DPS1 was enabled
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* in ACTIVE region
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_ACTIVE_TIME_US (0x0004)
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/*!
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* Property specifies the time(in US) for which DPS1 was enabled
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* in VBLANK region
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS1_VBLANK_TIME_US (0x0005)
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/*!
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* Property specifies the time(in US) for which DPS2 was enabled
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* in ACTIVE region
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_ACTIVE_TIME_US (0x0006)
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/*!
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* Property specifies the time(in US) for which DPS2 was enabled
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* in VBLANK region
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_MSCG_DPS2_VBLANK_TIME_US (0x0007)
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/*!
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* @brief Structure to identify display low power feature
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*
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@@ -2203,6 +2264,143 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
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NvBool bEnableDrr;
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} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
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/*
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* NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT
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*
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* This command sets lower and/or upper bounds for a display clock (dispclk or
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* hubclk), or for the memory perf level. When this API is called, the system
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* will immediately attempt to switch the clock or perf level to a value that
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* meets the specified condition(s).
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*
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* If no lower limit is desired, the "min" input should be set to zero.
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*
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* If no upper limit is desired for a clock, the "max" input should be set to
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* NV_U32_MAX.
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*
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* This API does not allow an upper limit to be specified for perf level.
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*
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* Any perf limit set through this API will remain in effect until it updated
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* or cancelled by a subsequent call to this API. A perf limit may be
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* cancelled by setting the "min" value to NV_U32_MIN (0) and the "max" value
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* (for clocks) to NV_U32_MAX. Only one perf limit may be in effect for a
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* given clientUsageId and type at any given time.
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*
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* At any given time, multiple perf limits (with different clientUsageIds) may
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* be in effect for a given clock or perf level, and that clock or perf level
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* will be set to a value that meets the requirements of all active perf
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* limits. If there is a conflict between perf limits, the conflict will be
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* resolved by the perf limit(s) with the higher priority.
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*
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* For example, suppose the API is called with the following parameters:
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* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
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* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
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* data.clock.minFrequencyKHz = 800000
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* data.clock.maxFrequencyKHz = 800000
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* This will set dispclk to 800 MHz (or possibly a slightly higher frequency,
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* if the clock dividers do not allow 800 MHz to be set exactly).
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*
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* Then suppose this call is made:
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* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE
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* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
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* data.clock.minFrequencyKHz = 1000000
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* data.clock.maxFrequencyKHz = 0xFFFFFFFF
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* After this call, dispclk will remain set to 800 MHz, because, although the
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* min frequency was requested to be at least 1 GHz, this would conflict with
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* the "maxFrequencyKHz = 800000" value set in the previous call, which is
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* still in effect. The previous call takes priority because
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* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS has higher priority than
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* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE.
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*
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* Then suppose this call is made:
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* clientUsageId = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS
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* type = NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK
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* data.clock.minFrequencyKHz = 0
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* data.clock.maxFrequencyKHz = 0xFFFFFFFF
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* This removes the NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS perf
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* limit. At this point, dispclk will be set to 1 GHz, in accordance with the
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* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE perf limit,
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* which is still in effect. (The remaining perf limit allows the clock to be
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* higher than 1 GHz, but in practice, the clock will generally be set to the
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* lowest frequency that meets the perf limit requirement, to save power. For
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* perf level, perf monitors (which do not use the perf limit mechanism) may
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* force a higher value in order to meet performance needs.)
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*
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* This API takes an array of perf limit structures, so multiple perf limits
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* maybe set within the same call.
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*
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* This API is primarily intended for use on SOC products, where display is
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* separate from the GPU. On dGPU products, this API may not be supported;
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* instead, NV2080_CTRL_CMD_PERF_LIMITS_SET_STATUS_V2 may be used to set perf
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* limits.
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*
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* subDeviceInstance (in)
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* This parameter specifies the subdevice instance within the
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* NV04_DISPLAY_COMMON parent device to which the operation should be
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* directed. This parameter must specify a value between zero and the
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* total number of subdevices within the parent device. This parameter
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* should be set to zero for default behavior.
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*
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* numLimits (in)
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* This is the number of perf limits with lower and/or upper limits to
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* apply.
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*
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* bWaitForCompletion (in)
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* It is possible that a perf change or clock change may take some time to
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* execute. If this flag is set, the API will wait for all of the changes
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* to complete before returning. (However, it will not wait for completion
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* of any operation that is blocked by a higher priority perf limit.)
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*
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* clientUsageId (in)
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* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_xxx value
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* indicating who the client is, and/or the purpose of the perf limit. It
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* is used to establish priority between conflicting perf limits.
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*
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* whatIsToBeLimited (in)
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* This is a NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_xxx value
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* indicating which clock, or memory perf level, is to have limits applied.
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*
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* minLevelOrFreqKHz (in)
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* maxLevelOrFreqKHz (in)
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* If type is
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* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_PERF_LEVEL, then
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* minLevelOrFreqKHz specifies the zero-based index of the minimum perf
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* level to allow. maxLevelOrFreqKHz is not used.
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*
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* If type specifies a clock
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* (NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_DISPCLK or
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* NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_TYPE_HUBCLK), then
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* minLevelOrFreqKHz and maxLevelOrFreqKHz specify the lower and upper
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* limits (respectively) for the specified clock's frequency.
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*/
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#define NV0073_CTRL_CMD_SYSTEM_SET_DISPLAY_PERF_LIMIT (0x73015aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID" */
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/* valid clientUsageId values */
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_ISMODEPOSSIBLE (0U)
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MCLK_SWITCH (1U)
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_ID_MODS (2U)
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/* valid type values */
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_PERF_LEVEL (0U)
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_DISPCLK (1U)
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_LIMITING_HUBCLK (2U)
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/* Define a structure for a single perf limit */
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typedef struct NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT {
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NvU8 clientUsageId;
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NvU8 whatIsToBeLimited;
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NvU32 minLevelOrFreqKHz;
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NvU32 maxLevelOrFreqKHz;
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} NV0073_CTRL_SYSTEM_DISPLAY_PERF_LIMIT;
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#define NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS_MESSAGE_ID (0x5AU)
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typedef struct NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 numLimits;
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NvBool bWaitForCompletion;
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NV_DECLARE_ALIGNED(NvP64 limits, 8);
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} NV0073_CTRL_SYSTEM_SET_DISPLAY_PERF_LIMIT_PARAMS;
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/*
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* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
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*
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