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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

142
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -1348,6 +1348,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV_TRUE if the C2C links are present and the links are up.
* The below remaining fields are valid only if return value is
* NV_OK and bIsLinkUp is NV_TRUE.
* bLinkInHS[OUT]
* NV_TRUE if the C2C links are in high speed mode.
* nrLinks[OUT]
* Total number of C2C links that are up.
* maxNrLinks[OUT]
@@ -1382,6 +1384,7 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
NvBool bIsLinkUp;
NvBool bLinkInHS;
NvU32 nrLinks;
NvU32 maxNrLinks;
NvU32 linkMask;
@@ -1393,6 +1396,8 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_CPU 1
#define NV2080_CTRL_BUS_GET_C2C_INFO_REMOTE_TYPE_GPU 2
/*
* NV2080_CTRL_CMD_BUS_SYSMEM_ACCESS
*
@@ -1417,7 +1422,44 @@ typedef struct NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_BUS_SYSMEM_ACCESS_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO
*
* This command returns the C2C error info for a C2C links.
*
* errCnts[OUT]
* Array of structure that contains the error counts for
* number of times one of C2C fatal error interrupt has happened.
* The array size should be NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES
* * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE.
*
* nrCrcErrIntr[OUT]
* Number of times CRC error interrupt triggered.
* nrReplayErrIntr[OUT]
* Number of times REPLAY error interrupt triggered.
* nrReplayB2bErrIntr[OUT]
* Number of times REPLAY_B2B error interrupt triggered.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_ERR_INFO (0x2080182d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES 2
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE 7
#define NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS {
struct {
NvU32 nrCrcErrIntr;
NvU32 nrReplayErrIntr;
NvU32 nrReplayB2bErrIntr;
} errCnts[NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_NUM_C2C_INSTANCES * NV2080_CTRL_BUS_GET_C2C_ERR_INFO_MAX_C2C_LINKS_PER_INSTANCE];
} NV2080_CTRL_BUS_GET_C2C_ERR_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_SET_P2P_MAPPING
@@ -1552,3 +1594,103 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000)
/*
* NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS
*
* This command returns C2C low power statistics.
* Units for residency and latency are in microsceconds.
* c2cStateSupportMask[OUT]
Support Mask of supplrted C2C State. CL0 will always be supported (FULL_POWER)
* cl3EntryCount[OUT]
* Count of the number of times CL3 state has been entered.
* cl3ResidentTimeUs[OUT]
* Total/Average resident time in CL3 state.
* cl3AvgEntryLatencyUs[OUT]
* Average entry latency for CL3 state.
* cl3AvgExitLatencyUs[OUT]
* Average exit latency for CL3 state.
* cl3PstateSupportMask[OUT]
Pstate Support Mask for CL3 state
* cl4EntryCount[OUT]
* Count of the number of times CL4 state has been entered.
* cl4ResidentTimeUs[OUT]
* Total/Average resident time in CL4 state.
* cl4AvgEntryLatencyUs[OUT]
* Average entry latency for CL4 state.
* cl4AvgExitLatencyUs[OUT]
* Average exit latency for CL4 state.
* cl4PstateSupportMask[OUT]
Pstate Support Mask for CL4 state
* localPowerState[OUT]
* Power state of the local end of the C2C link.
* Valid values are :
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
* remotePowerState[OUT]
* Power state of the remote end of the C2C link.
* Valid values are :
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER - Full power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 - Low power state
* NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 - Low power state
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
*
* Please also review the information below for additional information on
* select fields:
*
* cl3EntryCount/cl4EntryCount[OUT]
* These may not represent current exact count, as low power transitions could have
* occured after reading the counter register.
*/
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS (0x20801831) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS {
NvU32 c2cStateSupportMask;
NvBool bCl3Support;
NvU32 cl3EntryCount;
NvU32 cl3ExitCount;
NvU32 cl3ResidentTimeUs;
NvU32 cl3AvgEntryLatencyUs;
NvU32 cl3AvgExitLatencyUs;
NvU32 cl3PstateSupportMask;
NvU32 cl3DisallowReasonMask;
NvBool bCl4Support;
NvU32 cl4EntryCount;
NvU32 cl4ExitCount;
NvU32 cl4ResidentTimeUs;
NvU32 cl4AvgEntryLatencyUs;
NvU32 cl4AvgExitLatencyUs;
NvU32 cl4PstateSupportMask;
NvU32 cl4DisallowReasonMask;
NvU32 c2cLpwrStateAllowedMask;
NvU32 localPowerState;
NvU32 remotePowerState;
} NV2080_CTRL_CMD_BUS_GET_C2C_LPWR_STATS_PARAMS;
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_FULL_POWER 0x0
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL3 0x1
#define NV2080_CTRL_CMD_BUS_GET_C2C_STATE_CL4 0x2
/*
* NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE
*
* This command sets the allow vote for C2C Lpwr States.
* c2cLpwrStateId[IN]
* C2C LowPower State Id : NV2080_CTRL_LPWR_C2C_STATE_ID_CLx
* bAllowed[in]
* State Allowed/disallowed flag
*/
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE (0x20801832) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS_MESSAGE_ID (0x32U)
typedef struct NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS {
NvU32 c2cLpwrStateId;
NvBool bAllowed;
} NV2080_CTRL_CMD_BUS_SET_C2C_LPWR_STATE_VOTE_PARAMS;

1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fan.h
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@@ -30,3 +30,4 @@
// Source file: ctrl/ctrl2080/ctrl2080fan.finn
//

117
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -1811,9 +1811,8 @@ typedef struct NV2080_CTRL_FB_PATCH_PBR_FOR_MINING_PARAMS {
*
* Get memory alignment. Replacement for NVOS32_FUNCTION_GET_MEM_ALIGNMENT
*/
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_GET_MEM_ALIGNMENT (0x20801342U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS (4U)
#define NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS_MESSAGE_ID (0x42U)
typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
@@ -1827,8 +1826,6 @@ typedef struct NV2080_CTRL_FB_GET_MEM_ALIGNMENT_PARAMS {
NvU32 alignPitch;
NvU32 alignPad;
NvU32 alignMask;
NvU32 alignOutputFlags[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
NvU32 alignBank[NV2080_CTRL_FB_GET_MEM_ALIGNMENT_MAX_BANKS];
NvU32 alignKind;
NvU32 alignAdjust; // Output -- If non-zero the amount we need to adjust the offset
NvU32 alignAttr2;
@@ -2039,6 +2036,24 @@ typedef struct NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS {
NvU32 ropEnMask;
} NV2080_CTRL_FB_FS_INFO_ROP_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_SYS_MASK.
*/
typedef struct NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS {
/*!
* [in]: swizzId
* PartitionID associated with a created smc partition. Currently used only for a
* device monitoring client to get the physical values of the sys. The client needs to pass
* 'NV2080_CTRL_GPU_PARTITION_ID_INVALID' explicitly if it wants RM to ignore the swizzId.
* RM will consider this request similar to a legacy case.
*/
NvU32 swizzId;
/*!
* [out]: physical/local sys mask.
*/
NV_DECLARE_ALIGNED(NvU64 sysEnMask, 8);
} NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS;
/*!
* Structure holding the in/out params for NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LTC_MASK.
*/
@@ -2233,6 +2248,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS {
#define NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK 0xFU
#define NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK 0x10U
#define NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK 0x11U
#define NV2080_CTRL_FB_FS_INFO_SYS_MASK 0x12U
typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NvU16 queryType;
@@ -2257,6 +2273,7 @@ typedef struct NV2080_CTRL_FB_FS_INFO_QUERY {
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_LOGICAL_LTC_MASK_PARAMS logicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_PROFILER_MON_LOGICAL_LTC_MASK_PARAMS dmLogicalLtc, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_SYSL2_FS_INFO_SYSLTS_MASK_PARAMS sysl2Lts, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_FB_FS_INFO_SYS_MASK_PARAMS sys, 8);
} queryParams;
} NV2080_CTRL_FB_FS_INFO_QUERY;
@@ -2748,61 +2765,6 @@ typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
NvU32 newConfiguration;
} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_STATUS
*
* This control command is used by clients to get the FB availabilty status,
* i.e whether the GPU Memory is ready for use or not for MIG and non-MIG cases
*
* fbStatus[OUT]
* This parameter returns the various values of FB availability status.
* Valid values include:
* NV2080_CTRL_FB_STATUS_FAILED
* On Non Self hosted (Non NUMA) systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - this status indicates that either
* the memory onlining has failed or fabric probe response has failed.
* GPU reset maybe required in such a case.
* NV2080_CTRL_FB_STATUS_READY
* On Non Self hosted systems - this status is always returned as memory is ready
* after GPU initialization is complete.
* On Self hosted systems - this status indicates that the FB memory has been onlined
* successfully and is available for client/user allocations.
* NV2080_CTRL_FB_STATUS_PENDING
* On Non Self hosted systems - this status is not expected
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - This status indicates memory is yet to
* be onlined or is in progress since we are either still waiting for a fabric
* probe response or a fabric probe request hasn't been sent yet.
* NV2080_CTRL_FB_STATUS_NOT_APPLICABLE
* This status indicates that this is a system with no FB memory.
*
*
* @returns Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV2080_CTRL_CMD_FB_GET_STATUS (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID" */
// NUMA Memory Onlining Status
#define NV2080_CTRL_FB_STATUS_FAILED (0x00000000U)
#define NV2080_CTRL_FB_STATUS_READY (0x00000001U)
#define NV2080_CTRL_FB_STATUS_PENDING (0x00000002U)
#define NV2080_CTRL_FB_STATUS_NOT_APPLICABLE (0x00000003U)
#define NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
NvU32 fbStatus;
} NV2080_CTRL_FB_GET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
*
@@ -2818,12 +2780,12 @@ typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x58U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
NvU32 isSupported;
@@ -2842,15 +2804,44 @@ typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x59U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
NvU32 currentStatus;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS
*
* This command returns the memory boot training flags from VBIOS table.
*
* flagCollectSchmooData
* flagWrTrHybridVrefEn
* flagWrTrHybridNonVrefEn
* flagRdTrHybridVrefEn
* flagRdTrHybridNonVrefEn
* skipBootTraining
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_GET_MEMORY_BOOT_TRAINING_FLAGS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS_MESSAGE_ID (0x59U)
typedef struct NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS {
NvBool flagCollectSchmooData;
NvBool flagWrTrHybridVrefEn;
NvBool flagWrTrHybridNonVrefEn;
NvBool flagRdTrHybridVrefEn;
NvBool flagRdTrHybridNonVrefEn;
NvBool skipBootTraining;
} NV2080_CTRL_FB_GET_MEMORY_BOOT_TRAINING_FLAGS_PARAMS;
/* _ctrl2080fb_h_ */

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
View File

@@ -245,8 +245,7 @@ typedef struct NV2080_CTRL_FLCN_GET_ENGINE_ARCH_PARAMS {
* @{
*/
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_DEFAULT 0U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE_PMUMON 1U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 2U
#define NV2080_CTRL_FLCN_USTREAMER_FEATURE__COUNT 1U
/*!@}*/
/*!

90
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -111,8 +111,9 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED (0x0000003fU)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED (0x00000041U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000042U)
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
@@ -223,6 +224,10 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_RESETLESS_MIG_SUPPORTED_YES (0x00000001U)
/* valid localization supported values */
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_IS_LOCALIZATION_SUPPORTED_YES (0x00000001U)
/*
* NV2080_CTRL_CMD_GPU_GET_INFO
*
@@ -755,6 +760,8 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS {
NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
} NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_CLASSLIST
*
@@ -2634,7 +2641,14 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 90U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA 29:28
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DEFAULT 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_DISABLE 1U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA_ENABLE 2U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_DISABLE 0U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA_ENABLE 1U
@@ -3131,6 +3145,7 @@ typedef struct NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS {
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_128MB 0x08000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_256MB 0x10000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_512MB 0x20000000U
#define NV2080_CTRL_GPU_VMMU_SEGMENT_SIZE_1024MB 0x40000000U
@@ -4586,4 +4601,75 @@ typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 tpcReconfigMask;
} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_RPC_GSP_TEST
*
* This command checks a variable sized RPC for a known pattern, then
* fills the data field with another pattern. It also records the timestamp
* before and after the RPC is sent to GSP.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GPU_RPC_GSP_TEST (0x208001e8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS_MESSAGE_ID (0xe8U)
typedef struct NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS {
NvU8 test;
NvU32 dataSize;
NV_DECLARE_ALIGNED(NvU64 startTimestamp, 8);
NV_DECLARE_ALIGNED(NvU64 stopTimestamp, 8);
NV_DECLARE_ALIGNED(NvP64 data, 8);
} NV2080_CTRL_GPU_RPC_GSP_TEST_PARAMS;
#define NV2080_CTRL_GPU_RPC_GSP_TEST_SERIALIZED_INTEGRITY 0x1
#define NV2080_CTRL_GPU_RPC_GSP_TEST_UNSERIALIZED 0x2
/*
* NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES
*
* This command returns information necessary for GSP RPC integrity tests
*
* Possible status values returned are:
* NV_OK
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_GPU_RPC_GSP_QUERY_SIZES (0x208001e9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS_MESSAGE_ID (0xe9U)
typedef struct NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS {
NvU32 maxRpcSize;
NvU32 finnRmapiSize;
NvU32 rpcGspControlSize;
NvU32 rpcMessageHeaderSize;
NV_DECLARE_ALIGNED(NvU64 timestampFreq, 8);
} NV2080_CTRL_GPU_RPC_GSP_QUERY_SIZES_PARAMS;
/*
* RUSD features.
* Each feature definition equates to a bit in the supportedFeatures bitmask.
*/
#define RUSD_FEATURE_NON_POLLING 0x1
#define RUSD_FEATURE_POLLING 0x2
/*
* NV2080_CTRL_CMD_GPU_RUSD_GET_SUPPORTED_FEATURES
*
* @brief Returns bitmask of supported RUSD features.
*
* @param[out] supportedFeatures Bitmask of supported RUSD features
*
* @return NV_OK
*/
#define NV2080_CTRL_CMD_RUSD_GET_SUPPORTED_FEATURES (0x208081eaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS_MESSAGE_ID (0xeaU)
typedef struct NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS {
NvU32 supportedFeatures;
} NV2080_CTRL_RUSD_GET_SUPPORTED_FEATURES_PARAMS;
/* _ctrl2080gpu_h_ */

62
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -317,7 +317,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_03 (0x00000A03U)
/*
* TODO Bug 4333440 is introducing versions 12_*.
* Eventually once 12_* is tested and validated, another
* follow up change will be needed to remove 10_04 support.
*/
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_00 (0x00000C00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_12_01 (0x00000C01U)
@@ -340,6 +352,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_3 (NV2080_CTRL_GR_INFO_SM_VERSION_10_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
@@ -1172,6 +1187,9 @@ typedef struct NV2080_CTRL_GR_GET_CTX_BUFFER_INFO_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*
* ugpuId
* Specifies the uGPU ID on Hopper+.
*
*/
#define NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER (0x2080121bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
@@ -1189,6 +1207,7 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
NvU16 globalTpcId;
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
} globalSmId[NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER_MAX_SM_COUNT];
NvU16 numSm;
@@ -1655,6 +1674,47 @@ typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
NvU8 imla4;
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE (0xFFU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA16 (0x0U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DP (0x1U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FMLA32 (0x2U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FFMA (0x3U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA0 (0x4U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA1 (0x5U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA2 (0x6U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA3 (0x7U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_IMLA4 (0x8U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP16 (0x9U)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_FP32 (0xAU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DFMA (0xBU)
#define NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_DMLA (0xCU)
/*
* NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
*
* This command provides an interface to retrieve the speed select values of
* various instruction types.
*
* smIssueRateModifierListSize
* This field specifies the number of entries on the caller's
* smIssueRateModifierList.
* When caller passes smIssueRateModifierListSize = 0, all fuse
* values are returned.
* smIssueRateModifierList
* This field specifies a pointer in the caller's address space
* to the buffer into which the speed select values are to be returned.
*/
#define NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x2080123cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2;
#define NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x3CU)
typedef struct NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
NvU32 smIssueRateModifierListSize;
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
} NV2080_CTRL_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
/*
* NV2080_CTRL_CMD_GR_FECS_BIND_EVTBUF_FOR_UID
*

86
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -229,6 +229,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
NvU16 globalTpcId;
NvU16 virtualGpcId;
NvU16 migratableTpcId;
NvU16 ugpuId;
} globalSmId[NV2080_CTRL_INTERNAL_GR_MAX_SM];
NvU16 numSm;
@@ -1003,7 +1004,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_SETUP_RG_LINE_INTR_PARAMS {
* validGfxCTSIdMask [OUT]
* # mask of CTS IDs that contain Gfx capable Grs which can be assigned under this profile
*/
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 60
#define NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES 90
@@ -1671,17 +1672,6 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS
*/
#define NV2080_CTRL_CMD_INTERNAL_RC_WATCHDOG_TIMEOUT (0x20800a6a) /* finn: Evaluated from "((FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x6a)" */
/* !
* This command disables cuda limit activation at teardown of the client.
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_CUDA_LIMIT_DISABLE (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
/*
* This command is cleaning up OPTP when a client is found to have
* been terminated unexpectedly.
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_OPTP_CLI_CLEAR (0x20800a7c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7C" */
/* !
* This command is used to get the current AUX power state of the sub-device.
*/
@@ -2914,6 +2904,8 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
NvU32 bRasterSyncGpioDirection;
} NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FBSR_INIT
*
@@ -3438,7 +3430,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK
* NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK
*
* This command checks if all the dependant modules to PRH have been initialized.
*
@@ -3447,7 +3439,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_PRH_DEPENDENCY_CHECK (0x20800a18) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x18" */
#define NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_DEPENDENCY_CHECK (0x20800a7a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7A" */
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
@@ -3466,7 +3458,7 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
@@ -4004,8 +3996,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
/*
* NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA
*
* @brief Initialize RM User Shared Data memory mapping on physical RM
* @brief Initialize/Destroy RM User Shared Data memory mapping on physical RM
*
* @param[in] bInit If this is an init or a destroy request
* @param[in] physAddr Physical address of memdesc to link physical to kernel
* 0 to de-initialize
*
@@ -4015,6 +4008,7 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_GET_EDPP_LIMIT_INFO_P
#define NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID (0xFEU)
typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
NvBool bInit;
NV_DECLARE_ALIGNED(NvU64 physAddr, 8);
} NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_INIT_USER_SHARED_DATA (0x20800afe) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS_MESSAGE_ID" */
@@ -4680,7 +4674,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_HSHUB_MUX_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS {
NvU32 peerId;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
NvBool bEgmPeer;
NvBool bNvswitchConn;
} NV2080_CTRL_INTERNAL_NVLINK_PRE_SETUP_NVLINK_PEER_PARAMS;
@@ -4796,7 +4790,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
@@ -4829,7 +4823,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
NV_DECLARE_ALIGNED(NvU64 peerLinkMask, 8);
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
@@ -4962,6 +4956,8 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] maxSupportedLinks
* Maximum number of links supported for a given arch
* [Out] linkInfo
* Per link information
*/
@@ -4974,6 +4970,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlSize;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 ipVerNvlink;
NvU32 maxSupportedLinks;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
@@ -5264,6 +5261,28 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO
*
* Send CMC gsplite the address and size of log buffer allocated on sysmem
*
* [In] PublicId
* ID of the gsplite engine
* [In] logBufferSize
* Size of the log buffer allocated on sysmem
* [In] logBufferAddr
* Start address of the log buffer
*/
#define NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS {
NvU32 PublicId;
NV_DECLARE_ALIGNED(NvU64 logBufferSize, 8);
NV_DECLARE_ALIGNED(NvU64 logBufferAddr, 8);
} NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO (0x20800a89U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_SEND_CMC_LIBOS_BUFFER_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS
@@ -5271,6 +5290,31 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
* Request from CPU-RM to proccess supressed errors during boot on GSP
* This command accepts no parameters.
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REPLAY_SUPPRESSED_ERRORS (0x20800b01U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | 0x1" */
/*!
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER_V2
*/
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 {
NvU32 smIssueRateModifierListSize;
NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierList[NV2080_CTRL_GR_SM_ISSUE_RATE_MODIFIER_V2_MAX_LIST_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER_V2 smIssueRateModifierV2[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2 (0x20800b03) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_2_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS_MESSAGE_ID (0x03U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_V2_PARAMS;
/* ctrl2080internal_h */

8
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -71,7 +71,6 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
/* valid architecture values */
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_T23X (0xE0000023)
@@ -133,17 +132,22 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB100 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB110 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB112 (0x00000004)
/* valid ARCHITECTURE_GB20x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB20B (0x0000000B)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -306,7 +306,8 @@ typedef struct NV2080_CTRL_NVD_GET_NOCAT_JOURNAL_PARAMS {
#define NV2080_CTRL_NOCAT_TDR_TYPE_GC6_RESET 4
#define NV2080_CTRL_NOCAT_TDR_TYPE_SURPRISE_REMOVAL 5
#define NV2080_CTRL_NOCAT_TDR_TYPE_UCODE_RESET 6
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_GPU_RC_RESET 7
#define NV2080_CTRL_NOCAT_TDR_TYPE_TEST 8
typedef struct NV2080CtrlNocatJournalDataTdrReason {
NvU32 flags;

71
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2574,11 +2574,17 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool test_mode;
NvBool plr_vld;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool plr_reject_mode_vld;
NvBool plr_margin_th_override_to_default;
NvU8 plr_reject_mode;
NvU8 tx_crc_plr;
NvU8 plr_margin_th;
NvU8 fec_override_admin_10g_40g;
NvU8 fec_override_admin_25g;
NvU8 fec_override_admin_50g;
@@ -3288,7 +3294,8 @@ typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_FATAL = 21,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 22,
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
@@ -3298,6 +3305,51 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
/*
* NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY
*
* This command is used to update the NVLE topology in GSP RM
*
* [in] localGpuAlid
* ALID of local GPU in P2P object
* [in] localGpuClid
* CLID of local GPU in P2P object
* [in] remoteGpuAlid
* ALID of remote GPU in P2P object
* [in] remoteGpuClid
* CLID of remote GPU in P2P object
*/
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY (0x2080308cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS_MESSAGE_ID (0x8cU)
typedef struct NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS {
NvU32 localGpuAlid;
NvU32 localGpuClid;
NvU32 remoteGpuAlid;
NvU32 remoteGpuClid;
} NV2080_CTRL_NVLINK_UPDATE_NVLE_TOPOLOGY_PARAMS;
/*
* NV2080_CTRL_NVLINK_GET_NVLE_LIDS
*
* This command is used to get the alid and clid of a GPU from the remap table.
*
* [in] probeClid
* CLID from probe response
* [out] clid
* CLID of GPU from remap table
* [out] alid
* ALID of gpu
*/
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS (0x2080308dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS_MESSAGE_ID (0x8dU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS {
NvU32 probeClid;
NvU32 clid;
NvU32 alid;
} NV2080_CTRL_NVLINK_GET_NVLE_LIDS_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
*
@@ -3353,6 +3405,23 @@ typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO
*
* This command is used to get the ENCRYPT_EN register info
*
* [out] bEncyptEnSet
* Boolean that shows if ENCRYPT_EN is enabled or not.
*/
#define NV2080_CTRL_CMD_NVLINK_GET_NVLE_ENCRYPT_EN_INFO (0x2080308bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS_MESSAGE_ID (0x8bU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS {
NvBool bEncryptEnSet;
} NV2080_CTRL_NVLINK_GET_NVLE_ENCRYPT_EN_INFO_PARAMS;
/* _ctrl2080nvlink_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080pmumon.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

387
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080thermal.h
View File

@@ -23,8 +23,395 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080thermal.finn
//
/*
* Thermal System rmcontrol api versioning
*/
#define THERMAL_SYSTEM_API_VER 1U
#define THERMAL_SYSTEM_API_REV 0U
/*
* NV2080_CTRL_THERMAL_SYSTEM constants
*
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET
*
* Targets (ie the things the thermal system can observe). Target mask
* have to be in sync with corresponding element of NVAPI_THERMAL_TARGET
* enum, until there is a translation layer between these two.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
* There is no target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
* The GPU is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
* The memory is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
* The power supply is the target.
*
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
* The board (PCB) is the target.
*/
/* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
* The target is unknown.
*/
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE (0x00000000U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU (0x00000001U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY (0x00000002U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY (0x00000004U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD (0x00000008U)
#define NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN (0xFFFFFFFFU)
/*
* executeFlags values
*/
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT (0x00000000U)
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL (0x00000001U)
/*
* NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2
*
* This command will execute a list of thermal system instructions:
*
* clientAPIVersion
* This field must be set by the client to THERMAL_SYSTEM_API_VER,
* which allows the driver to determine api compatibility.
*
* clientAPIRevision
* This field must be set by the client to THERMAL_SYSTEM_API_REV,
* which allows the driver to determine api compatibility.
*
* clientInstructionSizeOf
* This field must be set by the client to
* sizeof(NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION), which allows the
* driver to determine api compatibility.
*
* executeFlags
* This field is set by the client to control instruction execution.
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_DEFAULT
* Execute instructions normally. The first instruction
* failure will cause execution to stop.
* NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_FLAGS_IGNORE_FAIL
* Execute all instructions, ignoring individual instruction failures.
*
* successfulInstructions
* This field is set by the driver and is the number of instructions
* that returned NV_OK on execution. If this field
* matches instructionListSize, all instructions executed successfully.
*
* instructionListSize
* This field is set by the client to the number of instructions in
* instruction list.
*
* instructionList
* This field is set an array of thermal system instructions
* (NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION) to execute, filled in by the
* client.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2 (0x20800513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_THERMAL_SYSTEM_EXECUTE_V2_PHYSICAL (0x20808513U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_THERMAL_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO instructions...
*
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE instruction
*
* Get the number of available targets.
*
* availableTargets
* Returns the number of available targets. Targets are
* identified by an index, starting with 0.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPCODE (0x00000100U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS {
NvU32 availableTargets;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE instruction
*
* Get a target's type.
*
* targetIndex
* Set by the client to the desired target index.
*
* type
* Returns a target's type.
* Possible values returned are:
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_NONE
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_GPU
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_MEMORY
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_POWER_SUPPLY
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_BOARD
* NV2080_CTRL_THERMAL_SYSTEM_TARGET_UNKNOWN
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE (0x00000101U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS {
NvU32 targetIndex;
NvU32 type;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE instruction
*
* Get a providers's type.
*
* providerIndex
* Set by the client to the desired provider index.
*
* type
* Returns a provider's type.
*/
/*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE (0x00000301U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS {
NvU32 providerIndex;
NvU32 type;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE instruction
*
* Get the number of available sensors.
*
* availableSensors
* Returns the number of available sensors. Sensors are
* identified by an index, starting with 0.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE (0x00000500U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS {
NvU32 availableSensors;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER instruction
*
* Get a sensor's provider index.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* providerIndex
* Returns a sensor's provider index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE (0x00000510U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS {
NvU32 sensorIndex;
NvU32 providerIndex;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS;
/*!
* Union of mode-specific arguments.
*/
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING instruction
*
* Get a sensor's current reading.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* value
* Returns a sensor's current reading.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE (0x00001500U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS {
NvU32 sensorIndex;
NvS32 value;
} NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET instruction
*
* Get a sensor's target index.
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* targetIndex
* Returns a sensor's target index.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE (0x00000520U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS {
NvU32 sensorIndex;
NvU32 targetIndex;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE instruction
*
* Get a sensor's readings range (ie min, max).
*
* sensorIndex
* Set by the client to the desired sensor index.
*
* minimum
* Returns a sensor's range minimum.
*
* maximum
* Returns a sensor's range maximum.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE (0x00000540U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS {
NvU32 sensorIndex;
NvS32 minimum;
NvS32 maximum;
} NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS;
/*
* Thermal System instruction operand
*/
typedef union NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS {
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGETS_AVAILABLE_OPERANDS getInfoTargetsAvailable;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS getInfoTargetType;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS getInfoProviderType;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS getInfoSensorsAvailable;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS getInfoSensorProvider;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS getInfoSensorTarget;
NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS getInfoSensorReadingRange;
NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS getStatusSensorReading;
NvU32 space[8];
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS;
/*
* NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION
*
* All thermal system instructions have the following layout:
*
* result
* This field is set by the driver, and is the result of the
* instruction's execution. This value is only valid if the
* executed field is not 0 upon return.
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*
* executed
* This field is set by the driver, and
* indicates if the instruction was executed.
* Possible status values returned are:
* 0: Not executed
* 1: Executed
*
* opcode
* This field is set by the client to the desired instruction opcode.
* Possible values are:
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPCODE
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPCODE
*/
/*
* operands
* This field is actually a union of all of the available operands.
* The interpretation of this field is opcode context dependent.
* Possible values are:
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_TARGET_TYPE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_PROVIDER_TYPE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSORS_AVAILABLE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_PROVIDER_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_TARGET_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_INFO_SENSOR_READING_RANGE_OPERANDS
* NV2080_CTRL_THERMAL_SYSTEM_GET_STATUS_SENSOR_READING_OPERANDS
*/
typedef struct NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION {
NvU32 result;
NvU32 executed;
NvU32 opcode;
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_OPERANDS operands;
} NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION;
#define NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT 0x20U
#define NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS_MESSAGE_ID (0x13U)
typedef struct NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS {
NvU32 clientAPIVersion;
NvU32 clientAPIRevision;
NvU32 clientInstructionSizeOf;
NvU32 executeFlags;
NvU32 successfulInstructions;
NvU32 instructionListSize;
NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION instructionList[NV2080_CTRL_THERMAL_SYSTEM_INSTRUCTION_MAX_COUNT];
} NV2080_CTRL_THERMAL_SYSTEM_EXECUTE_V2_PARAMS;
/* _ctrl2080thermal_h_ */

25
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -468,6 +468,9 @@ typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_STATE
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
@@ -476,4 +479,24 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS
NvBool bHeterogeneousMode;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE
*
* This command will set MIG timeslice mode in GSP RM
*
* bMigTimeslicingModeEnabled
* Mode of MIG timeslice
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE (0x2080400f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS {
NvBool bMigTimeslicingModeEnabled;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_MIG_TIMESLICE_MODE_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */