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This commit is contained in:
Bernhard Stoeckner
2025-04-17 19:35:38 +02:00
parent e8113f665d
commit 4159579888
1142 changed files with 309085 additions and 272273 deletions
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2
src/nvidia/inc/kernel/gpu/ce/kernel_ce_shared.h
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@@ -33,5 +33,7 @@
NvBool ceIsCeGrce(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType);
NvBool ceIsPartneredWithGr(OBJGPU *pGpu, RM_ENGINE_TYPE ceEngineType, RM_ENGINE_TYPE grEngineType);
NvU32 ceCountGrCe(OBJGPU *pGpu);
void cePauseCeUtilsScheduling(OBJGPU *pGpu);
void ceResumeCeUtilsScheduling(OBJGPU *pGpu);
#endif

49
src/nvidia/inc/kernel/gpu/disp/kern_disp_type.h
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@@ -30,6 +30,21 @@
*
******************************************************************************/
#define NV_PDISP_CHN_NUM_ANY 0x7F
#define DISP_ACCL_NONE (0x00)
#define DISP_ACCL_IGNORE_PI NVBIT(0)
#define DISP_ACCL_SKIP_NOTIF NVBIT(1)
#define DISP_ACCL_SKIP_SEMA NVBIT(2)
#define DISP_ACCL_IGNORE_INTERLOCK NVBIT(3)
#define DISP_ACCL_IGNORE_FLIPLOCK NVBIT(4)
#define DISP_ACCL_TRASH_ONLY NVBIT(5)
#define DISP_ACCL_TRASH_AND_ABORT NVBIT(6)
#define DISP_ACCL_SKIP_SYNCPOINT NVBIT(7)
#define DISP_ACCL_IGNORE_TIMESTAMP NVBIT(8)
#define DISP_ACCL_IGNORE_MGI NVBIT(9)
#define DISP_ACCL_DISABLE_PUTPTR_WRITE NVBIT(16)
#define DISP_ACCL_LOCK_PIO_FIFO NVBIT(16)
#define DISP_ACCL_DISABLE_INTR_DURING_SHTDWN NVBIT(17)
#define DISP_ACCL_ALL ~(DISP_ACCL_NONE)
typedef enum
{
@@ -44,6 +59,31 @@ typedef enum
dispChnClass_Supported
} DISPCHNCLASS;
typedef enum
{
dispChnState_Idle,
dispChnState_Wrtidle,
dispChnState_Empty,
dispChnState_Flushed,
dispChnState_Busy,
dispChnState_Dealloc,
dispChnState_DeallocLimbo,
dispChnState_Limbo1,
dispChnState_Limbo2,
dispChnState_Fcodeinit1,
dispChnState_Fcodeinit2,
dispChnState_Fcode,
dispChnState_Vbiosinit1,
dispChnState_Vbiosinit2,
dispChnState_Vbiosoper,
dispChnState_Unconnected,
dispChnState_Initialize1,
dispChnState_Initialize2,
dispChnState_Shutdown1,
dispChnState_Shutdown2,
dispChnState_Supported
} DISPCHNSTATE;
enum DISPLAY_ICC_BW_CLIENT
{
DISPLAY_ICC_BW_CLIENT_RM,
@@ -65,4 +105,13 @@ typedef struct
NvBool valid;
} VGAADDRDESC;
//
// Map HW channel state to SW channel state
//
typedef struct
{
NvU32 hwChannelState;
DISPCHNSTATE dispChnState;
} CHNSTATEMAP;
#endif // #ifndef KERN_DISP_TYPE_H

1
src/nvidia/inc/kernel/gpu/disp/vblank_callback/vblank.h
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@@ -63,7 +63,6 @@ typedef struct VBLANKCALLBACK
#define VBLANK_CALLBACK_FLAG_PROMOTE_TO_FRONT 0x00000080 // Promotes to being 'first', while still honoring VBlankCount
#define VBLANK_CALLBACK_FLAG_RELEASES_SEMAPHORE 0x00000100 // A flag for deadlock detection to check if this callback could release a semaphore
#define VBLANK_CALLBACK_FLAG_GUARANTEE_SAFETY 0x00000200 // This callback absolutely needs to run during vertical blank, even if it runs late as a consequence.
#define VBLANK_CALLBACK_FLAG_LOW_LATENCY__ISR_ONLY 0x08000000 // This means always process during ISR (never DPC.) Be careful!
#define VBLANK_CALLBACK_FLAG_LOW_LATENCY 0x10000000 // This now means ASAP, which could be ISR or DPC, depending on which happens first
#define VBLANK_CALLBACK_FLAG_MC_EXECUTE_ONCE 0x40000000 // A special flag for MultiChip configurations to have the callback execute only once
#define VBLANK_CALLBACK_FLAG_USER 0x80000000

2
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h
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@@ -34,5 +34,7 @@ NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, DACEXTERNALDEVICE *, GSYNCSTATUS
NV_STATUS gsyncSetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
NV_STATUS gsyncGetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncGetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetVRR_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
#endif // DAC_P2061_H

13
src/nvidia/inc/kernel/gpu/fsp/kern_fsp_retval.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -21,8 +21,9 @@
* DEALINGS IN THE SOFTWARE.
*/
#define FSP_OK (0x00U)
#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU)
#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU)
#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U)
#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U)
#define FSP_OK (0x00U)
#define FSP_ERR_IFS_ERR_INVALID_STATE (0x9EU)
#define FSP_ERR_IFR_FILE_NOT_FOUND (0x9FU)
#define FSP_ERR_IFS_ERR_NOT_SUPPORTED (0xA0U)
#define FSP_ERR_IFS_ERR_INVALID_DATA (0xA1U)
#define FSP_ERR_PRC_ERROR_INVALID_KNOB_ID (0x1E3U)

16
src/nvidia/inc/kernel/gpu/gpu_child_list.h
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@@ -291,18 +291,22 @@
#if GPU_CHILD_MODULE(NVJPG)
GPU_CHILD_MULTI_INST( OBJNVJPG, GPU_GET_NVJPG, GPU_MAX_NVJPGS, NV_FALSE, pNvjpg )
#endif
#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP)
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_TRUE, pKernelFsp )
#endif
#if RMCFG_MODULE_SPDM && GPU_CHILD_MODULE(SPDM)
GPU_CHILD_SINGLE_INST( Spdm, GPU_GET_SPDM, 1, NV_TRUE, pSpdm )
#endif
#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE)
GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute )
#endif
#if GPU_CHILD_MODULE(GSP)
GPU_CHILD_SINGLE_INST( Gsp, GPU_GET_GSP, 1, NV_FALSE, pGsp )
#endif
#if RMCFG_MODULE_KERNEL_FSP && GPU_CHILD_MODULE(KERNEL_FSP)
GPU_CHILD_SINGLE_INST( KernelFsp, GPU_GET_KERNEL_FSP, 1, NV_FALSE, pKernelFsp )
#endif
#if GPU_CHILD_MODULE(OFA)
GPU_CHILD_MULTI_INST( OBJOFA, GPU_GET_OFA, GPU_MAX_OFAS, NV_FALSE, pOfa )
#endif
#if RMCFG_MODULE_CONF_COMPUTE && GPU_CHILD_MODULE(CONF_COMPUTE)
GPU_CHILD_SINGLE_INST( ConfidentialCompute, GPU_GET_CONF_COMPUTE, 1, NV_TRUE, pConfCompute )
#endif
#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU)
GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu )
#endif

4
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -60,6 +60,7 @@ NV_STATUS gpuFabricProbeGetEgmGpaAddress(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, Nv
NV_STATUS gpuFabricProbeGetNumProbeReqs(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *numProbes);
NV_STATUS gpuFabricProbeGetFabricCliqueId(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricCliqueId);
NV_STATUS gpuFabricProbeGetFabricHealthStatus(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pFabricHealthStatusMask);
NV_STATUS gpuFabricProbeGetRemapTableIndex(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU32 *pRemapTableIdx);
NvBool gpuFabricProbeIsReceived(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NvBool gpuFabricProbeIsSuccess(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
@@ -78,5 +79,6 @@ NV_STATUS gpuFabricProbeReceivePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotif
NV_STATUS gpuFabricProbeReceiveUpdatePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeGetGfid(OBJGPU *pGpu, NvU32 *pGfid);
NvBool gpuFabricProbeIsInProgress(OBJGPU *pGpu);
#endif // GPU_FABRIC_PROBE_H

10
src/nvidia/inc/kernel/gpu/gpu_uuid.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,7 +35,7 @@
// UUID conversion routine:
NV_STATUS transformGidToUserFriendlyString(const NvU8 *pGidData, NvU32 gidSize, NvU8 **ppGidString,
NvU32 *pGidStrlen, NvU32 gidFlags);
NvU32 *pGidStrlen, NvU32 gidFlags, NvU8 prefix);
NV_STATUS nvGenerateGpuUuid(NvU16 chipId, NvU64 pdi, NvUuid *pUuid);
@@ -45,8 +45,10 @@ NV_STATUS nvGenerateSmcUuid(NvU16 chipId, NvU64 pdi,
// 'G' 'P' 'U' '-'(x5), '\0x0', extra = 9
#define NV_UUID_STR_LEN ((NV_UUID_LEN << 1) + 9)
void nvGetSmcUuidString(const NvUuid *pUuid, char *pUuidStr);
#define RM_UUID_PREFIX_GPU 0U
#define RM_UUID_PREFIX_MIG 1U
#define RM_UUID_PREFIX_DLA 2U
void nvGetGpuUuidString(const NvUuid *pUuid, char *pUuidStr);
void nvGetUuidString(const NvUuid *pUuid, NvU8 prefix, char *pUuidStr);
#endif // _GPUUUID_H_

8
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
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@@ -41,12 +41,12 @@
#define GSP_FW_HEAP_PARAM_BASE_RM_SIZE_GH100 (14 << 20) // Hopper+
//
// Calibrated by observing RM init heap usage on GPUs with various FB sizes.
// Calibrated by observing RM init heap usage on GPUs with various memory sizes.
// This seems to fit the data fairly well, but is likely inaccurate (differences
// in heap usage are more likely correlate with GPU architecture than FB size).
// in heap usage are more likely correlate with GPU architecture than memory size).
// TODO: this requires more detailed profiling and tuning.
//
#define GSP_FW_HEAP_PARAM_SIZE_PER_GB_FB (96 << 10) // All architectures
#define GSP_FW_HEAP_PARAM_SIZE_PER_GB (96 << 10) // All architectures
//
// This number is calibrated by profiling the WPR heap usage of a single
@@ -70,7 +70,7 @@
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (12u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (70u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (10u)
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT \
((581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)

7
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
View File

@@ -54,6 +54,13 @@ typedef struct
NvU64 pa;
NvU64 size;
} profilerArgs;
struct
{
NvU64 pa;
NvU64 size;
} sysmemHeapArgs;
} GSP_ARGUMENTS_CACHED;
#endif // GSP_INIT_ARGS_H

2
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -215,8 +215,8 @@ typedef struct GspSystemInfo
NvBool bFeatureStretchVblankCapable;
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
NvBool bRouteDispIntrsToCPU;
NvU64 hostPageSize;
NvBool bIsCmcBasedHws;
} GspSystemInfo;

8
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
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@@ -161,11 +161,11 @@
#define MC_ENGINE_IDX_GSPLITE3 174
#define MC_ENGINE_IDX_GSPLITE_MAX MC_ENGINE_IDX_GSPLITE3
#define MC_ENGINE_IDX_DPAUX 175
#define MC_ENGINE_IDX_DISP_LOW 176
#define MC_ENGINE_IDX_GPIO 176
#define MC_ENGINE_IDX_DISP_LOW 177
#define MC_ENGINE_IDX_HFRP 178
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 177
#define MC_ENGINE_IDX_MAX 179
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))

4
src/nvidia/inc/kernel/gpu/mem_mgr/mem_scrub.h
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@@ -55,6 +55,8 @@ struct OBJCHANNEL;
#define SCRUB_MAX_BYTES_PER_LINE 0xffffffffULL
#define MAX_SCRUB_ITEMS 4096 // 4K scrub items
#define SCRUBBER_SUBMIT_FLAGS_LOCALIZED_SCRUB NVBIT(0)
// structure to store the details of a scrubbing work
typedef struct SCRUB_NODE {
// The 64 bit ID assigned to each work
@@ -161,7 +163,7 @@ NV_STATUS scrubCheck(OBJMEMSCRUB *pScrubber, PSCRUB_NODE *ppList, NvU64 *size);
*/
NV_STATUS scrubSubmitPages(OBJMEMSCRUB *pScrubber, NvU64 chunkSize, NvU64* pages,
NvU64 pageCount, PSCRUB_NODE *ppList, NvU64 *size);
NvU64 pageCount, PSCRUB_NODE *ppList, NvU64 *size, NvU32 flags);
/**
* This function waits for the memory scrubber to wait for the scrubbing of

11
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/map_defines.h
View File

@@ -56,6 +56,11 @@ extern "C" {
#define _PMA_2MB (2ULL * 1024 * 1024)
#define _PMA_512MB (512ULL * 1024 * 1024)
// Localized memory chunks are 64MB split into 2 32MB chunks
#define PMA_LOCALIZED_MEMORY_ALLOC_STRIDE (32ULL * 1024 * 1024)
#define PMA_LOCALIZED_MEMORY_RESERVE_SIZE (2 * PMA_LOCALIZED_MEMORY_ALLOC_STRIDE)
typedef NvU32 PMA_PAGESTATUS;
#define MAP_IDX_ALLOC_UNPIN 0
@@ -65,6 +70,7 @@ typedef NvU32 PMA_PAGESTATUS;
#define MAP_IDX_PERSISTENT 4
#define MAP_IDX_NUMA_REUSE 5
#define MAP_IDX_BLACKLIST 6
#define MAP_IDX_LOCALIZED 7
#define STATE_FREE 0x00
#define STATE_UNPIN NVBIT(MAP_IDX_ALLOC_UNPIN)
@@ -77,15 +83,16 @@ typedef NvU32 PMA_PAGESTATUS;
#define ATTRIB_PERSISTENT NVBIT(MAP_IDX_PERSISTENT)
#define ATTRIB_NUMA_REUSE NVBIT(MAP_IDX_NUMA_REUSE)
#define ATTRIB_BLACKLIST NVBIT(MAP_IDX_BLACKLIST)
#define ATTRIB_LOCALIZED NVBIT(MAP_IDX_LOCALIZED)
#define ATTRIB_MASK (ATTRIB_EVICTING | ATTRIB_SCRUBBING \
| ATTRIB_PERSISTENT | ATTRIB_NUMA_REUSE \
| ATTRIB_BLACKLIST)
| ATTRIB_BLACKLIST | ATTRIB_LOCALIZED)
#define MAP_MASK (STATE_MASK | ATTRIB_MASK)
#define PMA_STATE_BITS_PER_PAGE 2 // Alloc & pinned state
#define PMA_ATTRIB_BITS_PER_PAGE 5 // Persistence, Scrubbing, Evicting, Reuse & Blacklisting attributes
#define PMA_ATTRIB_BITS_PER_PAGE 6 // Persistence, Scrubbing, Evicting, Reuse, Blacklisting, & Localized attributes
#define PMA_BITS_PER_PAGE (PMA_STATE_BITS_PER_PAGE + PMA_ATTRIB_BITS_PER_PAGE)

20
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.h
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@@ -100,6 +100,8 @@ typedef struct SCRUB_NODE SCRUB_NODE;
#define PMA_ALLOCATE_TURN_BLACKLIST_OFF NVBIT(11)
#define PMA_ALLOCATE_ALLOW_PARTIAL NVBIT(12)
#define PMA_ALLOCATE_REVERSE_ALLOC NVBIT(13)
#define PMA_ALLOCATE_LOCALIZED_UGPU0 NVBIT(14)
#define PMA_ALLOCATE_LOCALIZED_UGPU1 NVBIT(15)
// Output flags
#define PMA_ALLOCATE_RESULT_IS_ZERO NVBIT(0)
@@ -179,7 +181,7 @@ typedef NV_STATUS (*pmaEvictRangeCb_t)(void *ctxPtr, NvU64 physBegin, NvU64 phys
MEMORY_PROTECTION prot);
/*!
* @brief Pluggable data structure management. Currently we have regmap and address tree.
* @brief Pluggable data structure management. Currently we have regmap.
*/
typedef void *(*pmaMapInit_t)(NvU64 numFrames, NvU64 addrBase, PMA_STATS *pPmaStats, NvBool bProtected);
typedef void (*pmaMapDestroy_t)(void *pMap);
@@ -295,7 +297,7 @@ NV_STATUS pmaInitialize(PMA *pPma, NvU32 initFlags);
*
* All eviction handlers must have been unregistered by this point.
*
* @param[in] pma Pointer to PMA object being destroyed.
* @param[in] pPma Pointer to PMA object being destroyed.
*/
void pmaDestroy(PMA *pPma);
@@ -306,11 +308,23 @@ void pmaDestroy(PMA *pPma);
* Any clients of PMA can query config and state with a valid PMA object.
* Querying at different times may return different values when states change.
*
* @param[in] pma Pointer to PMA object being destroyed.
* @param[in] pPma Pointer to PMA object
* @param[in/out] pConfigs Configs/states to query. See PMA_QUERY_* above.
*/
NV_STATUS pmaQueryConfigs(PMA* pPma, NvU32 *pConfigs);
/*!
* @brief Identify if an FB range is PMA-managed
*
*
* @param[in] pPma Pointer to PMA object
* @param[in] offset FB block offset
* @param[in] limit FB block limit
*
* @return NV_TRUE offset is PMA-managed
* NV_FALSE offset is not managed by PMA
*/
NvBool pmaIsPmaManaged(PMA* pPma, NvU64 offset, NvU64 limit);
/*!
* @brief Attaches a region of physical memory to be managed by the PMA.

6
src/nvidia/inc/kernel/gpu/rpc/objrpc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -50,8 +50,8 @@ TYPEDEF_BITVECTOR(MC_ENGINE_BITVECTOR);
#include "g_rpc_hal.h" // For RPC_HAL_IFACES
#include "g_rpc_odb.h" // For RPC_HAL_IFACES
#define RPC_TIMEOUT_LIMIT_PRINT_RATE_THRESH 3 // rate limit after 3 prints
#define RPC_TIMEOUT_LIMIT_PRINT_RATE_SKIP 29 // skip 29 of 30 prints
#define RPC_TIMEOUT_GPU_RESET_THRESHOLD 3 // Reset GPU after 3 back to back GSP RPC timeout
#define RPC_TIMEOUT_PRINT_RATE_SKIP 29 // skip 29 of 30 prints
#define RPC_HISTORY_DEPTH 128