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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-14 17:47:23 +00:00
530.30.02
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@@ -633,6 +633,26 @@ static NvBool nv_numa_node_has_memory(int node_id)
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free_pages(ptr, order); \
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}
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static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra)
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{
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pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra);
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#if defined(CONFIG_AMD_MEM_ENCRYPT) && defined(NV_PGPROT_DECRYPTED_PRESENT)
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/*
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* When AMD memory encryption is enabled, device memory mappings with the
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* C-bit set read as 0xFF, so ensure the bit is cleared for user mappings.
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*
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* If cc_mkdec() is present, then pgprot_decrypted() can't be used.
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*/
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#if defined(NV_CC_MKDEC_PRESENT)
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prot = __pgprot(__sme_clr(pgprot_val(vm_prot)));
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#else
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prot = pgprot_decrypted(prot);
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#endif
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#endif
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return prot;
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}
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#if defined(PAGE_KERNEL_NOENC)
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#if defined(__pgprot_mask)
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#define NV_PAGE_KERNEL_NOCACHE_NOENC __pgprot_mask(__PAGE_KERNEL_NOCACHE)
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@@ -654,7 +674,8 @@ static inline NvUPtr nv_vmap(struct page **pages, NvU32 page_count,
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#if defined(PAGE_KERNEL_NOENC)
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if (unencrypted)
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{
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prot = cached ? PAGE_KERNEL_NOENC : NV_PAGE_KERNEL_NOCACHE_NOENC;
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prot = cached ? nv_adjust_pgprot(PAGE_KERNEL_NOENC, 0) :
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nv_adjust_pgprot(NV_PAGE_KERNEL_NOCACHE_NOENC, 0);
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}
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else
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#endif
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@@ -939,26 +960,6 @@ static inline int nv_remap_page_range(struct vm_area_struct *vma,
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return ret;
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}
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static inline pgprot_t nv_adjust_pgprot(pgprot_t vm_prot, NvU32 extra)
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{
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pgprot_t prot = __pgprot(pgprot_val(vm_prot) | extra);
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#if defined(CONFIG_AMD_MEM_ENCRYPT) && defined(NV_PGPROT_DECRYPTED_PRESENT)
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/*
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* When AMD memory encryption is enabled, device memory mappings with the
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* C-bit set read as 0xFF, so ensure the bit is cleared for user mappings.
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*
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* If cc_mkdec() is present, then pgprot_decrypted() can't be used.
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*/
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#if defined(NV_CC_MKDEC_PRESENT)
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prot = __pgprot(__sme_clr(pgprot_val(vm_prot)));
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#else
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prot = pgprot_decrypted(prot);
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#endif
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#endif
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return prot;
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}
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static inline int nv_io_remap_page_range(struct vm_area_struct *vma,
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NvU64 phys_addr, NvU64 size, NvU32 extra_prot)
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{
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@@ -1182,7 +1183,7 @@ typedef struct nv_alloc_s {
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NvBool zeroed : 1;
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NvBool aliased : 1;
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NvBool user : 1;
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NvBool node0 : 1;
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NvBool node : 1;
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NvBool peer_io : 1;
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NvBool physical : 1;
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NvBool unencrypted : 1;
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@@ -1196,6 +1197,7 @@ typedef struct nv_alloc_s {
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unsigned int pid;
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struct page **user_pages;
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NvU64 guest_id; /* id of guest VM */
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NvS32 node_id; /* Node id for memory allocation when node is set in flags */
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void *import_priv;
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struct sg_table *import_sgt;
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} nv_alloc_t;
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@@ -1436,6 +1438,24 @@ struct nv_dma_device {
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NvBool nvlink;
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};
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#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED)
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/*
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* acpi data storage structure
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*
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* This structure retains the pointer to the device,
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* and any other baggage we want to carry along
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*
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*/
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typedef struct
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{
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nvidia_stack_t *sp;
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struct acpi_device *device;
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struct acpi_handle *handle;
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void *notifier_data;
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int notify_handler_installed;
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} nv_acpi_t;
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#endif
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/* linux-specific version of old nv_state_t */
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/* this is a general os-specific state structure. the first element *must* be
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the general state structure, for the generic unix-based code */
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@@ -1530,8 +1550,13 @@ typedef struct nv_linux_state_s {
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/* Per-device notifier block for ACPI events */
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struct notifier_block acpi_nb;
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#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED)
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nv_acpi_t* nv_acpi_object;
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#endif
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/* Lock serializing ISRs for different SOC vectors */
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nv_spinlock_t soc_isr_lock;
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void *soc_bh_mutex;
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struct nv_timer snapshot_timer;
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nv_spinlock_t snapshot_timer_lock;
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@@ -1577,24 +1602,6 @@ extern struct rw_semaphore nv_system_pm_lock;
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extern NvBool nv_ats_supported;
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#if defined(NV_LINUX_ACPI_EVENTS_SUPPORTED)
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/*
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* acpi data storage structure
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*
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* This structure retains the pointer to the device,
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* and any other baggage we want to carry along
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*
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*/
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typedef struct
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{
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nvidia_stack_t *sp;
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struct acpi_device *device;
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struct acpi_handle *handle;
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int notify_handler_installed;
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} nv_acpi_t;
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#endif
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/*
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* file-private data
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* hide a pointer to our data structures in a file-private ptr
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@@ -1744,6 +1751,7 @@ static inline NV_STATUS nv_check_gpu_state(nv_state_t *nv)
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extern NvU32 NVreg_EnableUserNUMAManagement;
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extern NvU32 NVreg_RegisterPCIDriver;
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extern NvU32 NVreg_EnableResizableBar;
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extern NvU32 num_probed_nv_devices;
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extern NvU32 num_nv_devices;
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