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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-20 23:13:58 +00:00
530.30.02
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@@ -39,32 +39,6 @@ void uvm_hal_pascal_ce_offset_in_out(uvm_push_t *push, NvU64 offset_in, NvU64 of
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OFFSET_OUT_LOWER, HWVALUE(C0B5, OFFSET_OUT_LOWER, VALUE, NvOffset_LO32(offset_out)));
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}
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// Perform an appropriate membar before a semaphore operation. Returns whether
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// the semaphore operation should include a flush.
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static bool pascal_membar_before_semaphore(uvm_push_t *push)
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{
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uvm_gpu_t *gpu;
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if (uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_NONE)) {
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// No MEMBAR requested, don't use a flush.
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return false;
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}
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if (!uvm_push_get_and_reset_flag(push, UVM_PUSH_FLAG_NEXT_MEMBAR_GPU)) {
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// By default do a MEMBAR SYS and for that we can just use flush on the
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// semaphore operation.
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return true;
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}
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// MEMBAR GPU requested, do it on the HOST and skip the CE flush as CE
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// doesn't have this capability.
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gpu = uvm_push_get_gpu(push);
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gpu->parent->host_hal->wait_for_idle(push);
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gpu->parent->host_hal->membar_gpu(push);
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return false;
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}
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void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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@@ -72,7 +46,7 @@ void uvm_hal_pascal_ce_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 p
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = pascal_membar_before_semaphore(push);
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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@@ -98,7 +72,7 @@ void uvm_hal_pascal_ce_semaphore_reduction_inc(uvm_push_t *push, NvU64 gpu_va, N
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = pascal_membar_before_semaphore(push);
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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@@ -127,7 +101,7 @@ void uvm_hal_pascal_ce_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
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NvU32 launch_dma_plc_mode;
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bool use_flush;
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use_flush = pascal_membar_before_semaphore(push);
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use_flush = uvm_hal_membar_before_semaphore(push);
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if (use_flush)
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flush_value = HWCONST(C0B5, LAUNCH_DMA, FLUSH_ENABLE, TRUE);
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