NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-05-02 04:01:26 +00:00
Code Issues Packages Projects Releases Wiki Activity

530.30.02

Browse Source
This commit is contained in:
Andy Ritger
2023-02-28 11:12:44 -08:00
parent e598191e8e
commit 4397463e73
928 changed files with 124728 additions and 88525 deletions
Download Patch File Download Diff File Expand all files Collapse all files

39
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -137,10 +137,9 @@ nvswitch_init_lpwr_regs_ls10
bLpEnable = NV_TRUE;
softwareDesired = (bLpEnable) ? 0x1 : 0x0;
// TO-DO: The write to the AN1 register is not working. The logic here needs to be re-visited.
tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL);
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_CTRL_SYSTEM_LINK_AN1_CTRL, _PWRM_L1_ENABLE, softwareDesired, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _CTRL_SYSTEM_LINK_AN1_CTRL, tempRegVal);
tempRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL);
tempRegVal = FLD_SET_DRF_NUM(_NVLIPT, _LNK_PWRM_CTRL, _L1_SOFTWARE_DESIRED, softwareDesired, tempRegVal);
NVSWITCH_LINK_WR32_LS10(device, linkNum, NVLIPT_LNK, _NVLIPT_LNK, _PWRM_CTRL, tempRegVal);
}
void
@@ -1079,6 +1078,29 @@ nvswitch_store_topology_information_ls10
}
}
void
nvswitch_get_error_rate_threshold_ls10
(
nvlink_link *link
)
{
nvswitch_device *device = link->dev->pDevInfo;
NvU32 linkNumber = link->linkNumber;
NvU32 crcRegVal;
crcRegVal = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLDL,
_NVLDL_RX, _ERROR_RATE_CTRL);
link->errorThreshold.thresholdMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_MAN,
crcRegVal);
link->errorThreshold.thresholdExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_THRESHOLD_EXP,
crcRegVal);
link->errorThreshold.timescaleMan = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_MAN,
crcRegVal);
link->errorThreshold.timescaleExp = DRF_VAL(_NVLDL_RX, _ERROR_RATE_CTRL, _SHORT_TIMESCALE_EXP,
crcRegVal);
}
void
nvswitch_set_error_rate_threshold_ls10
(
@@ -1132,7 +1154,6 @@ nvswitch_set_error_rate_threshold_ls10
crcRegVal &= ~shortRateMask;
crcRegVal |= crcShortRegkeyVal;
link->errorThreshold.bUserConfig = NV_FALSE;
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
}
@@ -1204,13 +1225,11 @@ nvswitch_configure_error_rate_threshold_interrupt_ls10
if (bEnable)
{
link->errorThreshold.bInterruptTrigerred = NV_FALSE;
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 1,
intrRegVal);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _ENABLE);
}
else
{
intrRegVal = FLD_SET_DRF_NUM(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, 0,
intrRegVal);
intrRegVal |= DRF_DEF(_NVLDL_TOP, _INTR_NONSTALL_EN, _RX_SHORT_ERROR_RATE, _DISABLE);
}
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLDL,
@@ -1414,7 +1433,7 @@ nvswitch_execute_unilateral_link_shutdown_ls10
NvU32 link_state_request;
NvU32 link_state;
NvU32 stat_data = 0;
NvU32 link_intr_subcode = 0;
NvU32 link_intr_subcode;
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
{