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This commit is contained in:
Andy Ritger
2023-02-28 11:12:44 -08:00
parent e598191e8e
commit 4397463e73
928 changed files with 124728 additions and 88525 deletions
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1
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080base.h
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@@ -88,6 +88,7 @@
#define NV2080_CTRL_FLA (0x35)
#define NV2080_CTRL_GSP (0x36)
#define NV2080_CTRL_NNE (0x37)
#define NV2080_CTRL_NNE_LEGACY_NON_PRIVILEGED (0xb7) /* finn: Evaluated from "(NV2080_CTRL_NNE | NVxxxx_CTRL_LEGACY_NON_PRIVILEGED)" */
#define NV2080_CTRL_GRMGR (0x38)
#define NV2080_CTRL_UCODE_FUZZER (0x39)
#define NV2080_CTRL_DMABUF (0x3A)

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -36,10 +36,7 @@
typedef struct NV2080_CTRL_BIOS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BIOS_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BIOS_INFO;
/* Maximum number of bios infos that can be queried at once */
#define NV2080_CTRL_BIOS_INFO_MAX_SIZE (0x0000000F)

11
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
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@@ -244,10 +244,7 @@ typedef struct NV2080_CTRL_BUS_GET_PCI_INFO_PARAMS {
*
*/
typedef struct NV2080_CTRL_BUS_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_BUS_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_BUS_INFO;
/* valid bus info index values */
@@ -1397,10 +1394,14 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
* NV_OK and bIsLinkUp is NV_TRUE.
* nrLinks[OUT]
* Total number of C2C links that are up.
* maxNrLinks[OUT]
* Maximum number of C2C links that are supported.
* linkMask[OUT]
* Bitmask of the C2C links present and up.
* perLinkBwMBps[OUT]
* Theoretical per link bandwidth in MBps.
* perLinkLaneWidth[OUT]
* Lane width per link.
* remoteType[OUT]
* Type of the device connected to the remote end of the C2C link.
* Valid values are :
@@ -1427,8 +1428,10 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
typedef struct NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS {
NvBool bIsLinkUp;
NvU32 nrLinks;
NvU32 maxNrLinks;
NvU32 linkMask;
NvU32 perLinkBwMBps;
NvU32 perLinkLaneWidth;
NvU32 remoteType;
} NV2080_CTRL_CMD_BUS_GET_C2C_INFO_PARAMS;

16
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
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@@ -228,6 +228,8 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
* NV_ERR_GENERIC
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID (0x5U)
@@ -269,7 +271,11 @@ typedef struct NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS {
*
*/
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CMD_CE_GET_PHYSICAL_CAPS (0x20802a07) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0x7U)
typedef NV2080_CTRL_CE_GET_CAPS_V2_PARAMS NV2080_CTRL_CE_GET_PHYSICAL_CAPS_PARAMS;
#define NV2080_CTRL_CE_GET_FAULT_METHOD_BUFFER_SIZE_PARAMS_MESSAGE_ID (0x8U)
@@ -324,6 +330,12 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
NvU32 present;
} NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS;
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | 0xb" */
#define NV2080_CTRL_CMD_CE_GET_ALL_PHYSICAL_CAPS (0x20802a0b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS_MESSAGE_ID (0xbU)
typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
/* _ctrl2080ce_h_ */

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dma.h
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@@ -114,10 +114,7 @@ typedef struct NV2080_CTRL_DMA_INVALIDATE_TLB_PARAMS {
* NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE
* This index can be used to request the system address size in bits.
*/
typedef struct NV2080_CTRL_DMA_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_DMA_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_DMA_INFO;
/* valid dma info index values */
#define NV2080_CTRL_DMA_INFO_INDEX_SYSTEM_ADDRESS_SIZE (0x000000000)

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080event.h
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@@ -267,40 +267,6 @@ typedef struct NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS {
} NV2080_CTRL_EVENT_SET_SEMA_MEM_VALIDATION_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL
*
* hSemMemory
* This parameter specifies the handle of the memory object that
* identifies the semaphore memory associated with this subdevice
* event notification. Once this is set RM will generate an event
* only when there is a change in the semaphore value. It is
* expected that the semaphore memory value will be updated by
* the GPU indicating that there is an event pending. This
* command is used by VGX plugin to determine which virtual
* machine has generated a particular event.
*
* vmIdType
* This parameter specifies the type of guest virtual machine identifier
*
* guestVmId
* This parameter specifies the guest virtual machine identifier
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_EVENT_SET_VMBUS_CHANNEL (0x20800307) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_EVENT_INTERFACE_ID << 8) | NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS {
NvHandle hSemMemory;
VM_ID_TYPE vmIdType;
NV_DECLARE_ALIGNED(VM_ID guestVmId, 8);
} NV2080_CTRL_EVENT_SET_VMBUS_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_EVENT_SET_TRIGGER_FIFO
*

39
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -267,10 +267,7 @@
* Returns the ECC status size (corresponds to subpartitions or channels
* depending on architecture/memory type).
*/
typedef struct NV2080_CTRL_FB_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FB_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
/* valid fb info index values */
#define NV2080_CTRL_FB_INFO_INDEX_TILE_REGION_COUNT (0x00000000U) // Deprecated
@@ -686,11 +683,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
/* valid values for allocPolicy */
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS 0:0
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_READS_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES 1:1
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_NO (0x00000000U)
#define NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_WRITES_YES (0x00000001U)
/*
@@ -707,7 +704,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0xF" */
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY (0x2080130fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0xFU)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAM
@@ -773,7 +774,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x18" */
#define NV2080_CTRL_CMD_FB_SET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801318U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x18U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_SET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (deprecated; use NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 instead)
@@ -786,7 +791,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY (0x20801312U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS_MESSAGE_ID (0x12U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2
@@ -799,7 +808,11 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | 0x19" */
#define NV2080_CTRL_CMD_FB_GET_GPU_CACHE_ALLOC_POLICY_V2 (0x20801319U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS_MESSAGE_ID (0x19U)
typedef NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS NV2080_CTRL_FB_GET_GPU_CACHE_ALLOC_POLICY_V2_PARAMS;
/*
@@ -875,7 +888,7 @@ typedef struct NV2080_CTRL_FB_GPU_CACHE_ALLOC_POLICY_V2_PARAMS {
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_IS_KIND (0x20801313U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_IS_KIND_PARAMS_MESSAGE_ID (0x13U)

5
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -213,10 +213,7 @@ typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
* This index can be used too get channel groups currently in use per engine/runlist.
*
*/
typedef struct NV2080_CTRL_FIFO_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_FIFO_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
/* valid fifo info index values */
#define NV2080_CTRL_FIFO_INFO_INDEX_INSTANCE_TOTAL (0x000000000)

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080flcn.h
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@@ -332,9 +332,9 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_QUEUE_INFO_PARAMS {
*
* Get/set the event bitmask for the default queue.
*/
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_GET (0x20803122) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | 0x23" */
#define NV2080_CTRL_CMD_FLCN_USTREAMER_CONTROL_SET (0x20803123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FLCN_INTERFACE_ID << 8) | NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
//! The engine type, from NV2080_ENGINE_TYPE_*
@@ -353,6 +353,14 @@ typedef struct NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS {
NvU8 queueId;
} NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS;
#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS_MESSAGE_ID (0x22U)
typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_GET_PARAMS;
#define NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS_MESSAGE_ID (0x23U)
typedef NV2080_CTRL_FLCN_USTREAMER_CONTROL_PARAMS NV2080_CTRL_FLCN_USTREAMER_CONTROL_SET_PARAMS;
/*
* NV2080_CTRL_CMD_FLCN_GET_CTX_BUFFER_INFO
*

44
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpio.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -23,14 +23,52 @@
#pragma once
#include <nvtypes.h>
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrl2080/ctrl2080gpio.finn
//
#include "ctrl/ctrl2080/ctrl2080base.h"
#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_DIRECTION (0x20802300) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS_MESSAGE_ID (0x00U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS {
NvU32 gpioPin; // in
NvBool bInput; // in
} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_DIRECTION_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_PROGRAM_OUTPUT (0x20802301) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS_MESSAGE_ID (0x01U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS {
NvU32 gpioPin; // in
NvU32 value; // in
} NV2080_CTRL_INTERNAL_GPIO_PROGRAM_OUTPUT_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_READ_INPUT (0x20802302) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS {
NvU32 gpioPin; // in
NvU32 value; // out
} NV2080_CTRL_INTERNAL_GPIO_READ_INPUT_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION (0x20802303) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPIO_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS_MESSAGE_ID (0x03U)
typedef struct NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS {
NvU32 function; // in
NvU32 pin; // in
} NV2080_CTRL_INTERNAL_GPIO_ACTIVATE_HW_FUNCTION_PARAMS;
/* _ctrl2080gpio_h_ */
#include "ctrl/ctrl2080/ctrl2080base.h"

173
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -61,10 +61,7 @@
typedef struct NV2080_CTRL_GPU_INFO {
NvU32 index;
NvU32 data;
} NV2080_CTRL_GPU_INFO;
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
/* valid gpu info index values */
@@ -108,7 +105,9 @@ typedef struct NV2080_CTRL_GPU_INFO {
#define NV2080_CTRL_GPU_INFO_INDEX_CMP_SKU (0x0000003cU)
#define NV2080_CTRL_GPU_INFO_INDEX_DMABUF_CAPABILITY (0x0000003dU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003eU)
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x0000003fU)
/* valid minor revision extended values */
#define NV2080_CTRL_GPU_INFO_MINOR_REVISION_EXT_NONE (0x00000000U)
@@ -241,7 +240,9 @@ typedef struct NV2080_CTRL_GPU_GET_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvP64 gpuInfoList, 8);
} NV2080_CTRL_GPU_GET_INFO_PARAMS;
#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x2" */
#define NV2080_CTRL_CMD_GPU_GET_INFO_V2 (0x20800102U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_INFO_V2_PARAMS_MESSAGE_ID (0x2U)
typedef struct NV2080_CTRL_GPU_GET_INFO_V2_PARAMS {
NvU32 gpuInfoListSize;
@@ -687,7 +688,9 @@ typedef struct NV2080_CTRL_GPU_REG_OP {
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS (0x20800122U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS {
NvHandle hClientTarget;
@@ -1516,6 +1519,10 @@ typedef struct NV2080_CTRL_GPU_GET_FERMI_ZCULL_INFO_PARAMS {
* The board's 699 product part number (LSB justified ASCII field with 0x00
* denoting empty space e.g. "699-21228-0208-200").
*
* board965PartNumber
* The board's 965 product part number (LSB justified ASCII field with 0x00
* denoting empty space e.g. "965-21228-0208-200").
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
@@ -1541,6 +1548,7 @@ typedef struct NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS {
NvU8 boardRevision[3];
NvU8 boardType;
NvU8 board699PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
NvU8 board965PartNumber[NV2080_GPU_MAX_PRODUCT_PART_NUMBER_LENGTH];
} NV2080_CTRL_GPU_GET_OEM_BOARD_INFO_PARAMS;
@@ -1867,13 +1875,17 @@ typedef struct NV2080_CTRL_CMD_GPU_QUERY_ILLUM_SUPPORT_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x54" */
#define NV2080_CTRL_CMD_GPU_GET_ILLUM (0x20800154U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
NvU32 attribute;
NvU32 value;
} NV2080_CTRL_CMD_GPU_ILLUM_PARAMS;
#define NV2080_CTRL_GPU_GET_ILLUM_PARAMS_MESSAGE_ID (0x54U)
typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_GET_ILLUM_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_SET_ID_ILLUM
*
@@ -1883,7 +1895,11 @@ typedef struct NV2080_CTRL_CMD_GPU_ILLUM_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x55" */
#define NV2080_CTRL_CMD_GPU_SET_ILLUM (0x20800155U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0x55U)
typedef NV2080_CTRL_CMD_GPU_ILLUM_PARAMS NV2080_CTRL_GPU_SET_ILLUM_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_INFOROM_IMAGE_VERSION
@@ -2817,7 +2833,11 @@ typedef struct NV2080_CTRL_GPU_REPORT_NON_REPLAYABLE_FAULT_PARAMS {
* See confluence page "vGPU UMED Security" for details.
*
*/
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x78" */
#define NV2080_CTRL_CMD_GPU_EXEC_REG_OPS_VGPU (0x20800178U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS_MESSAGE_ID (0x78U)
typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_ENGINE_RUNLIST_PRI_BASE
@@ -3120,12 +3140,11 @@ typedef struct NV2080_CTRL_GPU_GET_PARTITION_CAPACITY_PARAMS {
* NV_ERR_NOT_SUPPORTED
* NV_ERR_OPERATING_SYSTEM
*/
#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0x82" */
#define NV2080_CTRL_CMD_GPU_GET_CACHED_INFO (0x20800182U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS {
NvU32 gpuInfoListSize;
NV2080_CTRL_GPU_INFO gpuInfoList[NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE];
} NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
#define NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS_MESSAGE_ID (0x82U)
typedef NV2080_CTRL_GPU_GET_INFO_V2_PARAMS NV2080_CTRL_GPU_GET_CACHED_INFO_PARAMS;
/*
* NV2080_CTRL_GPU_SET_PARTITIONING_MODE
@@ -3963,7 +3982,7 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
@@ -4025,11 +4044,11 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
/*
* NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS
*
*
* This command retrieves and constructs the GPU partnumber from the VBIOS.
*
*
* The following data are currently supported:
*
*
* pciDevId
* The PCI device ID
*
@@ -4045,8 +4064,8 @@ typedef struct NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*/
#define NV2080_CTRL_CMD_GPU_GET_CHIP_DETAILS (0x208001a4U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS_MESSAGE_ID" */
/*
* The string format for a GPU part number
/*
* The string format for a GPU part number
* The GPU part number is formatted with 4 hexadecimal digits for the PCI device ID, the chip SKU string,
* the chip major number, and then the chip minor number.
* Ordering of the fields for the string format must be synced with the NV2080_CTRL_GPU_GET_CHIP_DETAILS_PARAMS
@@ -4112,4 +4131,116 @@ typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS
#define NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS_MESSAGE_ID (0xA8U)
typedef NV2080_CTRL_GPU_MIGRATABLE_OPS_CMN_PARAMS NV2080_CTRL_GPU_MIGRATABLE_OPS_VGPU_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Marks the device for reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_RESET (0x208001a9U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xA9" */
/*
* NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Unmarks the device for reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_RESET (0x208001aaU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAA" */
/*
* NV2080_CTRL_CMD_GPU_GET_RESET_STATUS
*
* Gets the current reset status of the device.
*
* bResetNeeded
* Set to NV_TRUE if the device needs to be reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_RESET_STATUS (0x208001abU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS_MESSAGE_ID (0xABU)
typedef struct NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS {
NvBool bResetRequired;
} NV2080_CTRL_GPU_GET_RESET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Marks the device for drain and reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_MARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001acU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAC" */
/*
* NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET
*
* INTERNAL DEBUG/TESTING USE ONLY
*
* Unmarks the device for drain and reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_UNMARK_DEVICE_FOR_DRAIN_AND_RESET (0x208001adU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | 0xAD" */
/*
* NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS
*
* Gets the current drain and reset status of the device. Drain and reset is used only SMC configs.
*
* bDrainRecommended
* Set to NV_TRUE if a drain and reset is recommended for the device.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_DRAIN_AND_RESET_STATUS (0x208001aeU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS_MESSAGE_ID (0xAEU)
typedef struct NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS {
NvBool bDrainRecommended;
} NV2080_CTRL_GPU_GET_DRAIN_AND_RESET_STATUS_PARAMS;
/*
* NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2
*
* This command returns NVENC software sessions information for the associate GPU.
* This command is similar to NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO but doesn't have
* embedded pointers.
*
* Check NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO for detailed information.
*/
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID (0xAFU)
typedef struct NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS {
NvU32 sessionInfoTblEntry;
NV2080_CTRL_NVENC_SW_SESSION_INFO sessionInfoTbl[NV2080_CTRL_GPU_NVENC_SESSION_INFO_MAX_COPYOUT_ENTRIES];
} NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS;
#define NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2 (0x208001afU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVENC_SW_SESSION_INFO_V2_PARAMS_MESSAGE_ID" */
/* _ctrl2080gpu_h_ */

115
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -147,6 +147,9 @@ typedef NV0080_CTRL_GR_ROUTE_INFO NV2080_CTRL_GR_ROUTE_INFO;
* NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
* This index is used to return the number of "Tensor Cores"
* supported by the graphics pipeline
* NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
* This index is used to return the Graphics capabilities
* supported by the graphics pipeline
*/
typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
@@ -253,6 +256,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
@@ -320,6 +324,19 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
/**
* NV2080_CTRL_CMD_GR_GET_INFO
*
@@ -389,7 +406,9 @@ typedef struct NV2080_CTRL_GR_GET_INFO_PARAMS {
* ID is given (shareChID), then the 2 channels will share
* the zcull context buffers.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x5" */
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_MODE (0x20801205U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_MODE_PARAMS {
NvHandle hChannel;
@@ -494,7 +513,9 @@ typedef struct NV2080_CTRL_GR_GET_ZCULL_INFO_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x7" */
#define NV2080_CTRL_CMD_GR_CTXSW_PM_MODE (0x20801207U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
NvHandle hChannel;
@@ -542,7 +563,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_MODE_PARAMS {
* ID is given (shareChID), then the 2 channels will share
* the zcull context buffers.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x8" */
#define NV2080_CTRL_CMD_GR_CTXSW_ZCULL_BIND (0x20801208U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS_MESSAGE_ID (0x8U)
typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
NvHandle hClient;
@@ -580,7 +603,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_ZCULL_BIND_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x9" */
#define NV2080_CTRL_CMD_GR_CTXSW_PM_BIND (0x20801209U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS_MESSAGE_ID (0x9U)
typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
NvHandle hClient;
@@ -607,7 +632,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PM_BIND_PARAMS {
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_MAX_VALUES 128U
#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xA" */
#define NV2080_CTRL_CMD_GR_SET_GPC_TILE_MAP (0x2080120aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0xAU)
typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
NvU32 mapValueCount;
@@ -645,7 +672,9 @@ typedef struct NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0xE" */
#define NV2080_CTRL_CMD_GR_CTXSW_SMPC_MODE (0x2080120eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
NvHandle hChannel;
@@ -724,7 +753,9 @@ typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x10" */
#define NV2080_CTRL_CMD_GR_SET_CTXSW_PREEMPTION_MODE (0x20801210U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS_MESSAGE_ID (0x10U)
typedef struct NV2080_CTRL_GR_SET_CTXSW_PREEMPTION_MODE_PARAMS {
NvU32 flags;
@@ -809,7 +840,9 @@ typedef enum NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND_BUFFERS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_GR_CTXSW_PREEMPTION_BIND (0x20801211U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
NvU32 flags;
@@ -842,7 +875,9 @@ typedef struct NV2080_CTRL_GR_CTXSW_PREEMPTION_BIND_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_CMD_GR_PC_SAMPLING_MODE (0x20801212U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS_MESSAGE_ID (0x12U)
typedef struct NV2080_CTRL_GR_PC_SAMPLING_MODE_PARAMS {
NvHandle hChannel;
@@ -904,7 +939,9 @@ typedef struct NV2080_CTRL_GR_GET_ROP_INFO_PARAMS {
* gfxpSaveCnt
* This parameter returns the number of GfxP saves on the channel.
*/
#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x15" */
#define NV2080_CTRL_CMD_GR_GET_CTXSW_STATS (0x20801215U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS_MESSAGE_ID (0x15U)
typedef struct NV2080_CTRL_GR_GET_CTXSW_STATS_PARAMS {
NvHandle hChannel;
@@ -1120,12 +1157,14 @@ typedef struct NV2080_CTRL_GR_GET_GLOBAL_SM_ORDER_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1C" */
#define NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL (0x2080121cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
#define NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS_MESSAGE_ID (0x1CU)
typedef struct NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
NvU32 chID;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
} NV2080_CTRL_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA
@@ -1144,7 +1183,7 @@ typedef struct NV2080_CTRL_CMD_GR_GET_CURRENT_RESIDENT_CHANNEL_PARAMS {
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT 10U
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_TPC_PER_GPC_COUNT 10U
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1D" */
#define NV2080_CTRL_CMD_GR_GET_VAT_ALARM_DATA (0x2080121dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA_PER_TPC {
NV_DECLARE_ALIGNED(NvU64 errorCounter, 8);
@@ -1161,6 +1200,8 @@ typedef struct NV2080_CTRL_GR_VAT_ALARM_DATA {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA_PER_GPC gpc[NV2080_CTRL_CMD_GR_GET_VAT_ALARM_MAX_GPC_COUNT], 8);
} NV2080_CTRL_GR_VAT_ALARM_DATA;
#define NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS_MESSAGE_ID (0x1DU)
typedef struct NV2080_CTRL_GR_GET_VAT_ALARM_DATA_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_VAT_ALARM_DATA smVatAlarm, 8);
NvU32 maxGpcCount;
@@ -1209,7 +1250,9 @@ typedef struct NV2080_CTRL_GR_GET_ATTRIBUTE_BUFFER_SIZE_PARAMS {
* The number of bytes in each slot, i * slotStride gives the offset from the
* base of the pool to a given slot
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x1F" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_QUERY_SIZE (0x2080121fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS_MESSAGE_ID (0x1FU)
typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
NvU32 maxSlots;
@@ -1233,7 +1276,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_QUERY_SIZE_PARAMS {
* pControlStructure
* This input is the kernel CPU pointer to the control structure.
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x20" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_INITIALIZE (0x20801220U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1260,7 +1305,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_INITIALIZE_PARAMS {
* slots
* This input contains an array of the slots to be added to the control structure
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x21" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_ADD_SLOTS (0x20801221U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1299,7 +1346,9 @@ typedef struct NV2080_CTRL_GR_GFX_POOL_ADD_SLOTS_PARAMS {
* many. If there are not enough slots on the freelist to remove the
* requested amount, RM will return the number it was able to remove.
*/
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_CMD_GR_GFX_POOL_REMOVE_SLOTS (0x20801222U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_GR_GFX_POOL_REMOVE_SLOTS_PARAMS {
NV_DECLARE_ALIGNED(NvP64 pControlStructure, 8);
@@ -1375,21 +1424,12 @@ typedef struct NV2080_CTRL_GR_GET_TPC_MASK_PARAMS {
NvU32 tpcMask;
} NV2080_CTRL_GR_GET_TPC_MASK_PARAMS;
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x2C" */
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE (0x2080122cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS_MESSAGE_ID (0x2CU)
typedef NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS_MESSAGE_ID (0x2CU)
typedef struct NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_SET_TPC_PARTITION_MODE_PARAMS params, 8);
} NV2080_CTRL_CMD_GR_SET_TPC_PARTITION_MODE_FINN_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
*
@@ -1701,21 +1741,12 @@ typedef struct NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS {
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | 0x36" */
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP (0x20801236U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS_MESSAGE_ID (0x36U)
typedef NV2080_CTRL_GR_SET_GPC_TILE_MAP_PARAMS NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS;
// FINN PORT: The below type was generated by the FINN port to
// ensure that all API's have a unique structure associated
// with them!
#define NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS_MESSAGE_ID (0x36U)
typedef struct NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_GET_GPC_TILE_MAP_PARAMS params, 8);
} NV2080_CTRL_CMD_GR_GET_GPC_TILE_MAP_FINN_PARAMS;
/*
* NV2080_CTRL_CMD_GR_GET_ZCULL_MASK
*

17
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080i2c.h
View File

@@ -228,11 +228,18 @@ typedef struct NV2080_CTRL_I2C_RW_REG_PARAMS {
NvU8 buffer[(NV2080_CTRL_I2C_MAX_ENTRIES - 1)];
} NV2080_CTRL_I2C_RW_REG_PARAMS;
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x3" */
#define NV2080_CTRL_CMD_I2C_READ_REG (0x20800603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | 0x4" */
// provide NV2080_CTRL_I2C_READ_REG_PARAMS as the historical name
#define NV2080_CTRL_I2C_READ_REG_PARAMS_MESSAGE_ID (0x3U)
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
#define NV2080_CTRL_CMD_I2C_WRITE_REG (0x20800604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_WRITE_REG_PARAMS_MESSAGE_ID (0x4U)
typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_WRITE_REG_PARAMS;
/*
* NV006F_CTRL_CMD_SYSTEM_I2C_ACCESS
@@ -273,7 +280,7 @@ typedef NV2080_CTRL_I2C_RW_REG_PARAMS NV2080_CTRL_I2C_READ_REG_PARAMS;
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_I2C_ACCESS (0x20800610) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_I2C_INTERFACE_ID << 8) | NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_I2C_ACCESS_PARAMS_MESSAGE_ID (0x10U)

411
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -41,6 +41,7 @@
#include "ctrl/ctrl0000/ctrl0000system.h"
#include "ctrl/ctrl90f1.h"
#include "ctrl/ctrl30f1.h"
#include "nvcfg_sdk.h"
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO
@@ -206,31 +207,38 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
NvU32 bufferSize;
} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
/*!
* @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS {
NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */
#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
struct {
@@ -246,10 +254,17 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
NvU16 numTpc;
} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS;
/*!
* Retrieve BSP Static data.
@@ -288,15 +303,14 @@ typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
/*!
* @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK
* @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK
* @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */
@@ -328,6 +342,8 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
NvU32 numGfxTpc;
} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
/*!
* floorsweeping masks which are indexed via local GR index
@@ -335,6 +351,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS;
/*
* NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES
*
@@ -382,7 +404,6 @@ typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS {
* @ref NV2080_CTRL_CMD_GR_GET_INFO
* @ref NV2080_CTRL_CMD_GR_GET_INFO_V2
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */
@@ -397,14 +418,21 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INFO {
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO {
NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
} NV2080_CTRL_INTERNAL_STATIC_GR_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */
@@ -421,14 +449,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO {
NvU32 subregionHeightAlignPixels;
} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */
@@ -438,14 +473,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO {
NvU32 ropOperationsCount;
} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */
@@ -453,15 +495,22 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS {
NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
* @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */
@@ -476,14 +525,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */
@@ -499,10 +555,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER {
NvU8 imla4;
} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
/*
* NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
*
@@ -554,9 +618,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
NvBool bEnable;
} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS;
@@ -600,9 +666,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS {
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS;
#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU)
typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS;
@@ -629,6 +697,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE {
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS;
@@ -656,8 +725,6 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_C
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
NvU32 fecsRecordSize;
NvU32 timestampHiTagMask;
@@ -666,10 +733,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
NvU8 numLowerBitsZeroShift;
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8);
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS;
/**
* NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
*
@@ -739,16 +814,22 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
NvBool bPerSubCtxheaderSupported;
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U)
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM
*
@@ -933,6 +1014,8 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
* table [OUT]
* Supported profiles.
*/
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS {
NvU32 count;
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8);
@@ -973,6 +1056,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
@@ -1280,7 +1365,11 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
/*!
* @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
*/
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU)
typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE
@@ -1299,16 +1388,43 @@ typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
/*!
* NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE
*
* tableLen [OUT]
* tableLen [OUT]
* Number of valid records in table field.
*
* table [OUT]
* table [OUT]
* Interrupt table for Kernel RM.
*
* subtreeMap [OUT]
* Subtree range for each NV2080_INTR_CATEGORY.
*/
#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128
/*!
* Categories of interrupts.
*
* Each of these categories get a separate range of interrupt subtrees (top
* level bits).
*/
typedef enum NV2080_INTR_CATEGORY {
NV2080_INTR_CATEGORY_DEFAULT = 0,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
NV2080_INTR_CATEGORY_RUNLIST = 3,
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
} NV2080_INTR_CATEGORY;
#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
NvU8 subtreeStart;
NvU8 subtreeEnd;
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
NvU16 engineIdx;
NvU32 pmcIntrMask;
@@ -1321,6 +1437,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
NvU32 tableLen;
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
/* Index to retrieve the needed heap space for specific module */
@@ -1438,29 +1555,41 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
*
* This command retrieves memory config from HW
*
@@ -1479,8 +1608,9 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
* memBoundaryCfgValInit [OUT]
* Memory boundary config initial value (64KB aligned)
*/
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8);
@@ -1490,6 +1620,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
NvU32 memBoundaryCfgValInit;
} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U)
typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8
@@ -1679,6 +1815,10 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */
// Valid fault buffer types
#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000)
#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001)
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
@@ -1694,6 +1834,12 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
* shadowFaultBufferPteArray
* Pages of client shadow fault buffer.
*
* shadowFaultBufferType
* Replayable or non-replayable fault buffer
*
* faultBufferSharedMemoryPhysAddr
* Fault buffer shared memory address. Used only by the Replayable fault buffer.
*
* Possible status values returned are:
* NV_OK
*/
@@ -1706,8 +1852,29 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
NvU32 shadowFaultBufferSize;
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
NvU32 shadowFaultBufferType;
NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
* This command requests physical RM to disable the client shadow fault buffer.
*
* shadowFaultBufferType
* Replayable or non-replayable fault buffer
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU)
typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
NvU32 shadowFaultBufferType;
} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER
*
@@ -1725,16 +1892,6 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8);
} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
*
* This command requests physical RM to disable the client shadow fault buffer.
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */
/*!
* NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X
*
@@ -1764,7 +1921,7 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
@@ -1850,22 +2007,38 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
/*!
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U)
typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U)
typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U)
typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS
*/
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U)
typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
@@ -1877,7 +2050,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
*
*/
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U)
@@ -1896,8 +2069,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
* gpu instance should behave identically with respect to fragmentation and
* placement / span positioning.
*/
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE
@@ -1908,8 +2082,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
* as the exported gpu instance, but the imported gpu instance should behave
* identically with respect to fragmentation and placement / span positioning.
*/
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4
typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
@@ -1926,6 +2101,22 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU)
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT
*
@@ -2094,6 +2285,8 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
NvU8 hshubId;
} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
*
@@ -2335,7 +2528,7 @@ typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS {
* P2P Capability is disabled by a regkey.
* NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
* P2P Capability is not supported.
*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
@@ -2369,7 +2562,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
/*
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
*
* An internal call to invoke the sequence VGA register reads & writes to
* An internal call to invoke the sequence VGA register reads & writes to
* perform save and restore of VGA
*
* [in] saveOrRestore
@@ -2417,10 +2610,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
/*!
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
*/
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */
/*!
* NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
@@ -2460,7 +2652,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
* - Total Number of profiles filled
*
* profiles[OUT]
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
*/
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU)
@@ -2469,6 +2661,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU)
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS;
/*
@@ -2637,7 +2835,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
/*!
* NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC
*
* Disable the raster sync gpio on the other P2060 GPU
* Disable the raster sync gpio on the other P2060 GPU
* that's connected to master over Video bridge.
*
* [in] bEnableMaster
@@ -2647,7 +2845,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
* If raster sync GPIO direction is saved or not.
*
* [in/out] bRasterSyncGpioDirection
* During save it gets the direction.
* During save it gets the direction.
* In restores it sets the direction.
*
* Possible status values returned are:
@@ -2714,7 +2912,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
* [in] sysOffset
* Offset in SYSMEM region to save to/restore from
* [in] size
* Size of region being saved/restored
* Size of region being saved/restored
*/
#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
@@ -2805,7 +3003,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
/*!
* NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE
*
* Update the system control capability
* Update the system control capability
*
* bIsSysCtrlSupported [IN]
If the system control is supported
@@ -2843,7 +3041,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI {
NvU32 sensorId;
/*!
* PFM sensor limit value if required
* PFM sensor limit value if required
*/
NvU32 limit;
} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI;
@@ -2900,7 +3098,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Sync payload data
*
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU)
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC
@@ -2914,7 +3116,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Sync payload data
*
*/
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU)
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
@@ -2922,7 +3128,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
* Query Coherent FB Aperture Size.
*
*/
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
@@ -3168,9 +3374,94 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
NvU32 vPstateIdx;
} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
*
* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
*
* Possible status return values are:
* NV_OK Success
*/
#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
NvBool bIsSatisfied;
} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
/*
* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
*/
#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to get number of secure channels supported on SEC2 and CE
*
* maxSec2SecureChannels [OUT]
* maxCeSecureChannels [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
NvU32 maxSec2SecureChannels;
NvU32 maxCeSecureChannels;
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
*
* This command is an internal command sent from Kernel RM to Physical RM
* to disable the GPU system memory access after quiescing the GPU or
* re-enable sysmem access.
*
* bDisable [IN]
* If NV_TRUE the GPU is quiesced and system memory access is disabled .
* If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS {
NvBool bDisable;
} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU)
typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS {
NvU32 pinSetIn; // in
NvU32 pinSetOut; // in
NvBool bMasterScanLock; // out
NvU32 masterScanLockPin; // out
NvBool bSlaveScanLock; // out
NvU32 slaveScanLockPin; // out
} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */
#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU)
typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
NvU32 pinSet; // in
NvU32 gpioFunction; // out
NvU32 gpioPin; // out
NvBool gpioDirection; // out
} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
/* ctrl2080internal_h */

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -347,23 +347,7 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6E" */
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | 0x6F" */
#define NV2080_CTRL_CMD_PERF_RATED_TDP_GET_CONTROL (0x2080206e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID" */
/*!
* Structure containing the requested action for a RATED_TDP client (@ref
@@ -380,6 +364,30 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU)
typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS;
/*!
* NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL
*
* This command sets the requested RATED_TDP action corresponding to the
* specified client. @Note, however, that this command is unable to set @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_RM.
*
* See @ref NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS for documentation of
* parameters.
*
* Possible status values returned are
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_PERF_RATED_TDP_SET_CONTROL (0x2080206f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_PERF_INTERFACE_ID << 8) | NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS_MESSAGE_ID (0x6FU)
typedef NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS NV2080_CTRL_PERF_RATED_TDP_SET_CONTROL_PARAMS;
/*!
* This struct represents the GPU monitoring perfmon sample for an engine.
*/

24
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080rc.h
View File

@@ -252,9 +252,17 @@ typedef struct NV2080_CTRL_CMD_RC_RECOVERY_PARAMS {
NvU32 rcEnable;
} NV2080_CTRL_CMD_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xD" */
#define NV2080_CTRL_CMD_SET_RC_RECOVERY (0x2080220d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0xE" */
#define NV2080_CTRL_SET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xDU)
typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_SET_RC_RECOVERY_PARAMS;
#define NV2080_CTRL_CMD_GET_RC_RECOVERY (0x2080220e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GET_RC_RECOVERY_PARAMS_MESSAGE_ID (0xEU)
typedef NV2080_CTRL_CMD_RC_RECOVERY_PARAMS NV2080_CTRL_GET_RC_RECOVERY_PARAMS;
/* valid values for rcEnable */
#define NV2080_CTRL_CMD_RC_RECOVERY_DISABLED (0x00000000)
@@ -353,9 +361,17 @@ typedef struct NV2080_CTRL_CMD_RC_INFO_PARAMS {
NvU32 rcBreak;
} NV2080_CTRL_CMD_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x11" */
#define NV2080_CTRL_CMD_SET_RC_INFO (0x20802211) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | 0x12" */
#define NV2080_CTRL_SET_RC_INFO_PARAMS_MESSAGE_ID (0x11U)
typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_SET_RC_INFO_PARAMS;
#define NV2080_CTRL_CMD_GET_RC_INFO (0x20802212) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_RC_INTERFACE_ID << 8) | NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GET_RC_INFO_PARAMS_MESSAGE_ID (0x12U)
typedef NV2080_CTRL_CMD_RC_INFO_PARAMS NV2080_CTRL_GET_RC_INFO_PARAMS;
/* valid rcMode values */
#define NV2080_CTRL_CMD_RC_INFO_MODE_DISABLE (0x00000000)