mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-12 00:29:56 +00:00
530.30.02
This commit is contained in:
Andy Ritger
@@ -41,6 +41,7 @@
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#include "ctrl/ctrl0000/ctrl0000system.h"
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#include "ctrl/ctrl90f1.h"
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#include "ctrl/ctrl30f1.h"
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#include "nvcfg_sdk.h"
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/*!
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* NV2080_CTRL_CMD_INTERNAL_DISPLAY_GET_STATIC_INFO
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@@ -206,31 +207,38 @@ typedef struct NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS {
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NvU32 bufferSize;
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} NV2080_CTRL_INTERNAL_UVM_GET_ACCESS_CNTR_BUFFER_SIZE_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
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#define NV2080_CTRL_INTERNAL_GR_MAX_ENGINES 8
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_CAPS_V2
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x1F" */
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CAPS {
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NvU8 capsTbl[NV0080_CTRL_GR_CAPS_TBL_SIZE];
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} NV2080_CTRL_INTERNAL_STATIC_GR_CAPS;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS_MESSAGE_ID (0x20U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_CAPS engineCaps[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CAPS (0x20800a1f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS_MESSAGE_ID (0x1FU)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CAPS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CAPS_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_GLOBAL_SM_ORDER
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* @ref NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x22" */
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#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
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#define NV2080_CTRL_INTERNAL_GR_MAX_SM 240
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
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struct {
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@@ -246,10 +254,17 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER {
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NvU16 numTpc;
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} NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x23U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_GLOBAL_SM_ORDER globalSmOrder[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER (0x20800a22) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS_MESSAGE_ID (0x22U)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_GLOBAL_SM_ORDER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_GLOBAL_SM_ORDER_PARAMS;
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/*!
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* Retrieve BSP Static data.
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@@ -288,15 +303,14 @@ typedef struct NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS {
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} NV2080_CTRL_INTERNAL_MSENC_GET_CAPS_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
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#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
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#define NV2080_CTRL_INTERNAL_GR_MAX_GPC 12
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#define NV2080_CTRL_INTERNAL_MAX_TPC_PER_GPC_COUNT 10
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_GPC_MASK
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* @ref NV2080_CTRL_CMD_GR_GET_TPC_MASK
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* @ref NV2080_CTRL_CMD_GR_GET_PHYS_GPC_MASK
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x26" */
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@@ -328,6 +342,8 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS {
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NvU32 numGfxTpc;
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} NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x27U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
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/*!
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* floorsweeping masks which are indexed via local GR index
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@@ -335,6 +351,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_FLOORSWEEPING_MASKS floorsweepingMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS (0x20800a26) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS_MESSAGE_ID (0x26U)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FLOORSWEEPING_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FLOORSWEEPING_MASKS_PARAMS;
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/*
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* NV2080_CTRL_CMD_KGR_GET_CTX_BUFFER_PTES
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*
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@@ -382,7 +404,6 @@ typedef struct NV2080_CTRL_KGR_GET_CTX_BUFFER_PTES_PARAMS {
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* @ref NV2080_CTRL_CMD_GR_GET_INFO
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* @ref NV2080_CTRL_CMD_GR_GET_INFO_V2
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2A" */
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@@ -397,14 +418,21 @@ typedef struct NV2080_CTRL_INTERNAL_GR_INFO {
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_INFO {
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NV2080_CTRL_INTERNAL_GR_INFO infoList[NV0080_CTRL_GR_INFO_MAX_SIZE];
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} NV2080_CTRL_INTERNAL_STATIC_GR_INFO;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS_MESSAGE_ID (0x2BU)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_INFO engineInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_INFO (0x20800a2a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS_MESSAGE_ID (0x2AU)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_INFO_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_ZCULL_INFO
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2C" */
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@@ -421,14 +449,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO {
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NvU32 subregionHeightAlignPixels;
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} NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2DU)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_ZCULL_INFO engineZcullInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ZCULL_INFO (0x20800a2c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS_MESSAGE_ID (0x2CU)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ZCULL_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ZCULL_INFO_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_ROP_INFO
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x2E" */
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@@ -438,14 +473,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO {
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NvU32 ropOperationsCount;
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} NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2FU)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_ROP_INFO engineRopInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_ROP_INFO (0x20800a2e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS_MESSAGE_ID (0x2EU)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_ROP_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_ROP_INFO_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_PPC_MASK
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x30" */
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@@ -453,15 +495,22 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS {
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NvU32 mask[NV2080_CTRL_INTERNAL_GR_MAX_GPC];
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} NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x31U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_PPC_MASKS enginePpcMasks[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PPC_MASKS (0x20800a30) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS_MESSAGE_ID (0x30U)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PPC_MASKS_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PPC_MASKS_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_ENGINE_CONTEXT_PROPERTIES
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* @ref NV2080_CTRL_CMD_GR_GET_ATTRIBUTE_BUFFER_SIZE
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x32" */
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@@ -476,14 +525,21 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO {
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NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_BUFFER_INFO engine[NV2080_CTRL_INTERNAL_ENGINE_CONTEXT_PROPERTIES_ENGINE_ID_COUNT];
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} NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x33U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_CONTEXT_BUFFERS_INFO engineContextBuffersInfo[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO (0x20800a32) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS_MESSAGE_ID (0x32U)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_CONTEXT_BUFFERS_INFO_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_CONTEXT_BUFFERS_INFO_PARAMS;
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/*!
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* @ref NV2080_CTRL_CMD_GR_GET_SM_ISSUE_RATE_MODIFIER
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*/
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x34" */
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@@ -499,10 +555,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER {
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NvU8 imla4;
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} NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER;
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#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x35U)
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_SM_ISSUE_RATE_MODIFIER smIssueRateModifier[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER (0x20800a34) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS_MESSAGE_ID (0x34U)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_SM_ISSUE_RATE_MODIFIER_PARAMS;
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/*
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* NV2080_CTRL_INTERNAL_GPU_GET_CHIP_INFO_PARAMS
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*
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@@ -554,9 +618,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS {
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NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
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NvBool bEnable;
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} NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x37U)
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typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_HW_ENABLE_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS_MESSAGE_ID (0x38U)
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typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_HW_ENABLE_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_HW_ENABLE_PARAMS;
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@@ -600,9 +666,11 @@ typedef struct NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS {
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#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x39U)
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typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_RD_OFFSET_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS_MESSAGE_ID (0x3AU)
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typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_SET_FECS_TRACE_WR_OFFSET_PARAMS;
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#define NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS_MESSAGE_ID (0x3BU)
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typedef NV2080_CTRL_INTERNAL_GR_FECS_TRACE_OFFSET_PARAMS NV2080_CTRL_INTERNAL_GR_GET_FECS_TRACE_RD_OFFSET_PARAMS;
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@@ -629,6 +697,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE {
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typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS {
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NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE fecsRecordSize[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
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} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS;
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#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS_MESSAGE_ID (0x3DU)
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typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_RECORD_SIZE_PARAMS;
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@@ -656,8 +725,6 @@ typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_RECORD_SIZE_PARAMS NV2080_CTRL_C
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|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x3F" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
|
||||
NvU32 fecsRecordSize;
|
||||
NvU32 timestampHiTagMask;
|
||||
@@ -666,10 +733,18 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES {
|
||||
NvU8 numLowerBitsZeroShift;
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3EU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES fecsTraceDefines[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES], 8);
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES (0x20800a3f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS_MESSAGE_ID (0x3FU)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_FECS_TRACE_DEFINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_FECS_TRACE_DEFINES_PARAMS;
|
||||
|
||||
/**
|
||||
* NV2080_CTRL_CMD_INTERNAL_GET_DEVICE_INFO_TABLE
|
||||
*
|
||||
@@ -739,16 +814,22 @@ typedef struct NV2080_CTRL_INTERNAL_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
|
||||
|
||||
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x48" */
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
|
||||
NvBool bPerSubCtxheaderSupported;
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x47U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS {
|
||||
NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES pdbTable[NV2080_CTRL_INTERNAL_GR_MAX_ENGINES];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES (0x20800a48) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS_MESSAGE_ID (0x48U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_GR_GET_PDB_PROPERTIES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KGR_GET_PDB_PROPERTIES_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_WRITE_INST_MEM
|
||||
*
|
||||
@@ -933,6 +1014,8 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO {
|
||||
* table [OUT]
|
||||
* Supported profiles.
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x4FU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS {
|
||||
NvU32 count;
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO table[NV2080_CTRL_INTERNAL_GRMGR_PARTITION_MAX_TYPES], 8);
|
||||
@@ -973,6 +1056,8 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_PARTITIONABLE_MEM_PARAMS {
|
||||
|
||||
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x52U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
|
||||
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
|
||||
@@ -1280,7 +1365,11 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_GET_STATIC_INFO_PARAMS {
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GR_GET_CTXSW_MODES
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x5A" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GR_GET_CTXSW_MODES (0x20800a5a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS_MESSAGE_ID (0x5AU)
|
||||
|
||||
typedef NV2080_CTRL_GR_GET_CTXSW_MODES_PARAMS NV2080_CTRL_INTERNAL_GR_GET_CTXSW_MODES_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE
|
||||
@@ -1299,16 +1388,43 @@ typedef struct NV2080_CTRL_INTERNAL_FB_GET_HEAP_RESERVATION_SIZE_PARAMS {
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE
|
||||
*
|
||||
* tableLen [OUT]
|
||||
* tableLen [OUT]
|
||||
* Number of valid records in table field.
|
||||
*
|
||||
* table [OUT]
|
||||
* table [OUT]
|
||||
* Interrupt table for Kernel RM.
|
||||
*
|
||||
* subtreeMap [OUT]
|
||||
* Subtree range for each NV2080_INTR_CATEGORY.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_INTR_GET_KERNEL_TABLE (0x20800a5c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE 128
|
||||
|
||||
/*!
|
||||
* Categories of interrupts.
|
||||
*
|
||||
* Each of these categories get a separate range of interrupt subtrees (top
|
||||
* level bits).
|
||||
*/
|
||||
typedef enum NV2080_INTR_CATEGORY {
|
||||
NV2080_INTR_CATEGORY_DEFAULT = 0,
|
||||
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE = 1,
|
||||
NV2080_INTR_CATEGORY_ESCHED_DRIVEN_ENGINE_NOTIFICATION = 2,
|
||||
NV2080_INTR_CATEGORY_RUNLIST = 3,
|
||||
NV2080_INTR_CATEGORY_RUNLIST_NOTIFICATION = 4,
|
||||
NV2080_INTR_CATEGORY_UVM_OWNED = 5,
|
||||
NV2080_INTR_CATEGORY_UVM_SHARED = 6,
|
||||
NV2080_INTR_CATEGORY_ENUM_COUNT = 7,
|
||||
} NV2080_INTR_CATEGORY;
|
||||
|
||||
#define NV2080_INTR_INVALID_SUBTREE NV_U8_MAX
|
||||
|
||||
typedef struct NV2080_INTR_CATEGORY_SUBTREE_MAP {
|
||||
NvU8 subtreeStart;
|
||||
NvU8 subtreeEnd;
|
||||
} NV2080_INTR_CATEGORY_SUBTREE_MAP;
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
|
||||
NvU16 engineIdx;
|
||||
NvU32 pmcIntrMask;
|
||||
@@ -1321,6 +1437,7 @@ typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY {
|
||||
typedef struct NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS {
|
||||
NvU32 tableLen;
|
||||
NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_ENTRY table[NV2080_CTRL_INTERNAL_INTR_MAX_TABLE_SIZE];
|
||||
NV2080_INTR_CATEGORY_SUBTREE_MAP subtreeMap[NV2080_INTR_CATEGORY_ENUM_COUNT];
|
||||
} NV2080_CTRL_INTERNAL_INTR_GET_KERNEL_TABLE_PARAMS;
|
||||
|
||||
/* Index to retrieve the needed heap space for specific module */
|
||||
@@ -1438,29 +1555,41 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PROFILES
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x63" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PROFILES (0x20800a63) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS_MESSAGE_ID (0x63U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PROFILES_PARAMS;
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_VALID_SWIZZID_MASK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_VALID_SWIZZID_MASK (0x20800a64) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x64" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES
|
||||
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x65" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES (0x20800a65) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS_MESSAGE_ID (0x65U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_PARTITIONABLE_ENGINES_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
|
||||
* NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x66" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES (0x20800a66) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS_MESSAGE_ID (0x66U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_SWIZZ_ID_FB_MEM_PAGE_RANGES_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
|
||||
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG
|
||||
* NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG
|
||||
*
|
||||
* This command retrieves memory config from HW
|
||||
*
|
||||
@@ -1479,8 +1608,9 @@ typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_CHANNELS_PARAMS {
|
||||
* memBoundaryCfgValInit [OUT]
|
||||
* Memory boundary config initial value (64KB aligned)
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x67" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x68" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a68) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x68U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 memBoundaryCfgA, 8);
|
||||
@@ -1490,6 +1620,12 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS {
|
||||
NvU32 memBoundaryCfgValInit;
|
||||
} NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG (0x20800a67) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS_MESSAGE_ID (0x67U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS NV2080_CTRL_INTERNAL_KMEMSYS_GET_MIG_MEMORY_CONFIG_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE (0x20800a6b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MEMSYS_GET_MIG_MEMORY_PARTITION_TABLE_SIZE 8
|
||||
@@ -1679,6 +1815,10 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_FAULT_BUFFER (0x20800a9c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9C" */
|
||||
|
||||
// Valid fault buffer types
|
||||
#define NV2080_CTRL_FAULT_BUFFER_NON_REPLAYABLE (0x00000000)
|
||||
#define NV2080_CTRL_FAULT_BUFFER_REPLAYABLE (0x00000001)
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER
|
||||
*
|
||||
@@ -1694,6 +1834,12 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_FAULT_BUFFER_PARAMS {
|
||||
* shadowFaultBufferPteArray
|
||||
* Pages of client shadow fault buffer.
|
||||
*
|
||||
* shadowFaultBufferType
|
||||
* Replayable or non-replayable fault buffer
|
||||
*
|
||||
* faultBufferSharedMemoryPhysAddr
|
||||
* Fault buffer shared memory address. Used only by the Replayable fault buffer.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
@@ -1706,8 +1852,29 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PAR
|
||||
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferQueuePhysAddr, 8);
|
||||
NvU32 shadowFaultBufferSize;
|
||||
NV_DECLARE_ALIGNED(NvU64 shadowFaultBufferPteArray[NV2080_CTRL_INTERNAL_GMMU_CLIENT_SHADOW_FAULT_BUFFER_MAX_PAGES], 8);
|
||||
NvU32 shadowFaultBufferType;
|
||||
NV_DECLARE_ALIGNED(NvU64 faultBufferSharedMemoryPhysAddr, 8);
|
||||
} NV2080_CTRL_INTERNAL_GMMU_REGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
|
||||
*
|
||||
* This command requests physical RM to disable the client shadow fault buffer.
|
||||
*
|
||||
* shadowFaultBufferType
|
||||
* Replayable or non-replayable fault buffer
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS_MESSAGE_ID (0x9EU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS {
|
||||
NvU32 shadowFaultBufferType;
|
||||
} NV2080_CTRL_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER
|
||||
*
|
||||
@@ -1725,16 +1892,6 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
|
||||
NV_DECLARE_ALIGNED(NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS PdeCopyParams, 8);
|
||||
} NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SERVER_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER
|
||||
*
|
||||
* This command requests physical RM to disable the client shadow fault buffer.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GMMU_UNREGISTER_CLIENT_SHADOW_FAULT_BUFFER (0x20800a9e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x9E" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X
|
||||
*
|
||||
@@ -1764,7 +1921,7 @@ typedef struct NV2080_CTRL_INTERNAL_GMMU_COPY_RESERVED_SPLIT_GVASPACE_PDES_TO_SE
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PERF_BOOST_SET_3X (0x20800aa0) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_PERF_BOOST_SET_PARAMS_3X_MESSAGE_ID (0xA0U)
|
||||
|
||||
@@ -1850,22 +2007,38 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONING_MODE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA3" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_PARTITIONING_MODE (0x20800aa3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS_MESSAGE_ID (0xA3U)
|
||||
|
||||
typedef NV2080_CTRL_GPU_SET_PARTITIONING_MODE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_PARTITIONING_MODE_PARAMS;
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GPU_CONFIGURE_PARTITION
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA4" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE (0x20800aa4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA4U)
|
||||
|
||||
typedef NV2080_CTRL_GPU_CONFIGURE_PARTITION_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_CONFIGURE_GPU_INSTANCE_PARAMS;
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GPU_SET_PARTITIONS
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA5" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_SET_GPU_INSTANCES (0x20800aa5) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA5U)
|
||||
|
||||
typedef NV2080_CTRL_GPU_SET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_SET_GPU_INSTANCES_PARAMS;
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_GPU_GET_PARTITIONS
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA6" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_GET_GPU_INSTANCES (0x20800aa6) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS_MESSAGE_ID (0xA6U)
|
||||
|
||||
typedef NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_GET_GPU_INSTANCES_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED
|
||||
@@ -1877,7 +2050,7 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_GRMGR_GET_SKYLINE_INFO_PARAMS {
|
||||
* NV_TRUE -> ZBC-kind (and no _SKIP_ZBCREFCOUNT flag) are allocated in Kernel RM
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MEMSYS_SET_ZBC_REFERENCED (0x20800a69) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS_MESSAGE_ID (0x69U)
|
||||
|
||||
@@ -1896,8 +2069,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
|
||||
* gpu instance should behave identically with respect to fragmentation and
|
||||
* placement / span positioning.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA7" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA8" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE (0x20800aa7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE (0x20800aa8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE
|
||||
@@ -1908,8 +2082,9 @@ typedef struct NV2080_CTRL_INTERNAL_MEMSYS_SET_ZBC_REFERENCED_PARAMS {
|
||||
* as the exported gpu instance, but the imported gpu instance should behave
|
||||
* identically with respect to fragmentation and placement / span positioning.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xA9" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xAA" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE (0x20800aa9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE (0x20800aaa) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_MAX_ENGINES_MASK_SIZE 4
|
||||
typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO {
|
||||
@@ -1926,6 +2101,22 @@ typedef struct NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_INTERNAL_KMIGMGR_EXPORTED_GPU_INSTANCE_INFO info, 8);
|
||||
} NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA7U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA8U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_EXPORT_GPU_INSTANCE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xA9U)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS_MESSAGE_ID (0xAAU)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_KMIGMGR_IMPORT_EXPORT_GPU_INSTANCE_PARAMS NV2080_CTRL_INTERNAL_MIGMGR_IMPORT_GPU_INSTANCE_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_MEMSYS_L2_INVALIDATE_EVICT
|
||||
*
|
||||
@@ -2094,6 +2285,8 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS {
|
||||
NvU8 hshubId;
|
||||
} NV2080_CTRL_INTERNAL_HSHUB_NEXT_HSHUB_ID_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_COMPUTE_PEER_ADDR
|
||||
*
|
||||
@@ -2335,7 +2528,7 @@ typedef struct NV2080_CTRL_INTERNAL_REMOVE_P2P_CAPS_PARAMS {
|
||||
* P2P Capability is disabled by a regkey.
|
||||
* NV0000_P2P_CAPS_STATUS_NOT_SUPPORTED
|
||||
* P2P Capability is not supported.
|
||||
*
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
@@ -2369,7 +2562,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_DISPLAY_UNIX_CONSOLE
|
||||
*
|
||||
* An internal call to invoke the sequence VGA register reads & writes to
|
||||
* An internal call to invoke the sequence VGA register reads & writes to
|
||||
* perform save and restore of VGA
|
||||
*
|
||||
* [in] saveOrRestore
|
||||
@@ -2417,10 +2610,9 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS {
|
||||
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_POST_RESTORE_PARAMS;
|
||||
|
||||
/*!
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES
|
||||
* @ref NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xba" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE
|
||||
@@ -2460,7 +2652,7 @@ typedef struct NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE {
|
||||
* - Total Number of profiles filled
|
||||
*
|
||||
* profiles[OUT]
|
||||
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
|
||||
* - NV2080_CTRL_GPU_COMPUTE_PROFILE filled with valid compute instance profiles
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBBU)
|
||||
|
||||
@@ -2469,6 +2661,12 @@ typedef struct NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS {
|
||||
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
|
||||
} NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES (0x20800aba) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xBAU)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_STATIC_MIGMGR_GET_COMPUTE_PROFILES_PARAMS NV2080_CTRL_INTERNAL_STATIC_KMIGMGR_GET_COMPUTE_PROFILES_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
@@ -2637,7 +2835,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC
|
||||
*
|
||||
* Disable the raster sync gpio on the other P2060 GPU
|
||||
* Disable the raster sync gpio on the other P2060 GPU
|
||||
* that's connected to master over Video bridge.
|
||||
*
|
||||
* [in] bEnableMaster
|
||||
@@ -2647,7 +2845,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_IS_DISPLAYID_VALID_PARAMS {
|
||||
* If raster sync GPIO direction is saved or not.
|
||||
*
|
||||
* [in/out] bRasterSyncGpioDirection
|
||||
* During save it gets the direction.
|
||||
* During save it gets the direction.
|
||||
* In restores it sets the direction.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
@@ -2714,7 +2912,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
|
||||
* [in] sysOffset
|
||||
* Offset in SYSMEM region to save to/restore from
|
||||
* [in] size
|
||||
* Size of region being saved/restored
|
||||
* Size of region being saved/restored
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_FBSR_SEND_REGION_INFO (0x20800ac3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FBSR_SEND_REGION_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
@@ -2805,7 +3003,7 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_TOTAL_NUM_LINK_PER_IOCTRL_PARAMS
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_SMBPBI_PFM_REQ_HNDLR_CAP_UPDATE
|
||||
*
|
||||
* Update the system control capability
|
||||
* Update the system control capability
|
||||
*
|
||||
* bIsSysCtrlSupported [IN]
|
||||
If the system control is supported
|
||||
@@ -2843,7 +3041,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI {
|
||||
NvU32 sensorId;
|
||||
|
||||
/*!
|
||||
* PFM sensor limit value if required
|
||||
* PFM sensor limit value if required
|
||||
*/
|
||||
NvU32 limit;
|
||||
} NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_DATA_SMBPBI;
|
||||
@@ -2900,7 +3098,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
|
||||
* Sync payload data
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCC" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC (0x20800acc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS_MESSAGE_ID (0xCCU)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_PMGR_PFM_REQ_HNDLR_STATE_LOAD_SYNC_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC
|
||||
@@ -2914,7 +3116,11 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
|
||||
* Sync payload data
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xCD" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC (0x20800acd) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS_MESSAGE_ID (0xCDU)
|
||||
|
||||
typedef NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS NV2080_CTRL_INTERNAL_THERM_PFM_REQ_HNDLR_STATE_INIT_SYNC_PARAMS;
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE
|
||||
@@ -2922,7 +3128,7 @@ typedef struct NV2080_CTRL_INTERNAL_PFM_REQ_HNDLR_STATE_SYNC_PARAMS {
|
||||
* Query Coherent FB Aperture Size.
|
||||
*
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE (0x20800ada) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GET_COHERENT_FB_APERTURE_SIZE_PARAMS_MESSAGE_ID (0xDAU)
|
||||
|
||||
@@ -3168,9 +3374,94 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS {
|
||||
NvU32 vPstateIdx;
|
||||
} NV2080_CTRL_CMD_INTERNAL_PERF_PFM_REQ_HNDLR_SET_VPSTATE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE
|
||||
*
|
||||
* This command gets if GPU is in a proper state (P8 and engine idle) to be ready to enter RTD3
|
||||
*
|
||||
* Possible status return values are:
|
||||
* NV_OK Success
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GC6_ENTRY_PREREQUISITE (0x2080a7d7) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_POWER_LEGACY_NON_PRIVILEGED_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS_MESSAGE_ID (0xD7U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS {
|
||||
NvBool bIsSatisfied;
|
||||
} NV2080_CTRL_INTERNAL_GC6_ENTRY_PREREQUISITE_PARAMS;
|
||||
|
||||
/*
|
||||
* This command unsets Dynamic Boost limit when nvidia-powerd is terminated unexpectedly.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_PMGR_UNSET_DYNAMIC_BOOST_LIMIT (0x20800a7b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0x7B" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS
|
||||
*
|
||||
* This command is an internal command sent from Kernel RM to Physical RM
|
||||
* to get number of secure channels supported on SEC2 and CE
|
||||
*
|
||||
* maxSec2SecureChannels [OUT]
|
||||
* maxCeSecureChannels [OUT]
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS (0x20800ad8) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS_MESSAGE_ID (0xD8U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS {
|
||||
NvU32 maxSec2SecureChannels;
|
||||
NvU32 maxCeSecureChannels;
|
||||
} NV2080_CTRL_INTERNAL_FIFO_GET_NUM_SECURE_CHANNELS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS
|
||||
*
|
||||
* This command is an internal command sent from Kernel RM to Physical RM
|
||||
* to disable the GPU system memory access after quiescing the GPU or
|
||||
* re-enable sysmem access.
|
||||
*
|
||||
* bDisable [IN]
|
||||
* If NV_TRUE the GPU is quiesced and system memory access is disabled .
|
||||
* If NV_FALSE the GPU system memory access is re-enabled and the GPU is resumed.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_PARAM_STRUCT
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS (0x20800adb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS_MESSAGE_ID (0xDBU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS {
|
||||
NvBool bDisable;
|
||||
} NV2080_CTRL_INTERNAL_BIF_DISABLE_SYSTEM_MEMORY_ACCESS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISP_PINSETS_TO_LOCKPINS (0x20800adc) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS_MESSAGE_ID (0xDCU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS {
|
||||
NvU32 pinSetIn; // in
|
||||
NvU32 pinSetOut; // in
|
||||
NvBool bMasterScanLock; // out
|
||||
NvU32 masterScanLockPin; // out
|
||||
NvBool bSlaveScanLock; // out
|
||||
NvU32 slaveScanLockPin; // out
|
||||
} NV2080_CTRL_INTERNAL_DISP_PINSETS_TO_LOCKPINS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DETECT_HS_VIDEO_BRIDGE (0x20800add) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xDD" */
|
||||
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL (0x20800ade) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS_MESSAGE_ID (0xDEU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS {
|
||||
NvU32 pinSet; // in
|
||||
NvU32 gpioFunction; // out
|
||||
NvU32 gpioPin; // out
|
||||
NvBool gpioDirection; // out
|
||||
} NV2080_CTRL_INTERNAL_DISP_SET_SLI_LINK_GPIO_SW_CONTROL_PARAMS;
|
||||
|
||||
/* ctrl2080internal_h */
|
||||
|
||||
Reference in New Issue
Block a user