530.30.02

src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h

@@ -0,0 +1,32 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: MIT
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef GSP_FW_HEAP_H
+#define GSP_FW_HEAP_H
+
+// Static defines for the GSP FW WPR Heap
+#define GSP_FW_HEAP_SIZE_LIBOS2            (64u << 20)
+#define GSP_FW_HEAP_SIZE_LIBOS3_BAREMETAL  (84u << 20)
+#define GSP_FW_HEAP_SIZE_LIBOS3_VGPU      (549u << 20)
+
+#endif // GSP_FW_HEAP_H

src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h

@@ -35,6 +35,8 @@ typedef struct {
     NvU32 pageTableEntryCount;
     NvLength cmdQueueOffset;
     NvLength statQueueOffset;
+    NvLength locklessCmdQueueOffset;
+    NvLength locklessStatQueueOffset;
 } MESSAGE_QUEUE_INIT_ARGUMENTS;
 
 typedef struct {

src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h

@@ -98,6 +98,8 @@ typedef struct GspStaticConfigInfo_t
     NvBool bIsTitan;
     NvBool bIsTesla;
     NvBool bIsMobile;
+    NvBool bIsGc6Rtd3Allowed;
+    NvBool bIsGcOffRtd3Allowed;
 
     NvU64 bar1PdeBase;
     NvU64 bar2PdeBase;

src/nvidia/inc/kernel/gpu/gsp/message_queue.h

@@ -27,12 +27,18 @@
 #ifndef _MESSAGE_QUEUE_H_
 #define _MESSAGE_QUEUE_H_
 
+// Used for indexing into the MESSAGE_QUEUE_COLLECTION array.
+#define RPC_TASK_RM_QUEUE_IDX      0
+#define RPC_TASK_ISR_QUEUE_IDX     1
+#define RPC_QUEUE_COUNT            2
+
 typedef struct _message_queue_info MESSAGE_QUEUE_INFO;
+typedef struct MESSAGE_QUEUE_COLLECTION MESSAGE_QUEUE_COLLECTION;
 
 // CPU-side calls
-NV_STATUS GspMsgQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI);
+NV_STATUS GspMsgQueuesInit(OBJGPU *pGpu, MESSAGE_QUEUE_COLLECTION **ppMQCollection);
+void      GspMsgQueuesCleanup(MESSAGE_QUEUE_COLLECTION **ppMQCollection);
 NV_STATUS GspStatusQueueInit(OBJGPU *pGpu, MESSAGE_QUEUE_INFO **ppMQI);
-void GspMsgQueueCleanup(MESSAGE_QUEUE_INFO **ppMQI);
 NV_STATUS GspMsgQueueSendCommand(MESSAGE_QUEUE_INFO *pMQI, OBJGPU *pGpu);
 NV_STATUS GspMsgQueueReceiveStatus(MESSAGE_QUEUE_INFO *pMQI);
 

src/nvidia/inc/kernel/gpu/gsp/message_queue_priv.h

@@ -50,21 +50,14 @@ typedef struct GSP_MSG_QUEUE_ELEMENT
 typedef struct _message_queue_info
 {
     // Parameters
-    NvLength               pageTableEntryCount;
-    NvLength               pageTableSize;
     NvLength               commandQueueSize;
     NvLength               statusQueueSize;
 
     // Shared memory area.
-    MEMORY_DESCRIPTOR     *pSharedMemDesc;
-    RmPhysAddr             sharedMemPA;   // Page table for all of shared mem.
     void                  *pCommandQueue;
     void                  *pStatusQueue;
     rpc_message_header_v  *pRpcMsgBuf;    // RPC message buffer VA.
 
-    void                  *pInitMsgBuf;   // RPC message buffer VA.
-    RmPhysAddr             initMsgBufPA;  // RPC message buffer PA.
-
     // Other CPU-side fields
     void                  *pWorkArea;
     GSP_MSG_QUEUE_ELEMENT *pCmdQueueElement;    // Working copy of command queue element.
@@ -72,8 +65,22 @@ typedef struct _message_queue_info
     msgqHandle             hQueue;              // Do not allow requests when hQueue is null.
     NvU32                  txSeqNum;            // Next sequence number for tx.
     NvU32                  rxSeqNum;            // Next sequence number for rx.
+    NvU32                  queueIdx;            // QueueIndex used to identify which task the message is supposed to be sent to.
 } MESSAGE_QUEUE_INFO;
 
+typedef struct MESSAGE_QUEUE_COLLECTION
+{
+    // Parameters
+    NvLength               pageTableEntryCount;
+    NvLength               pageTableSize;
+
+    // Shared memory area.
+    MEMORY_DESCRIPTOR     *pSharedMemDesc;
+    RmPhysAddr             sharedMemPA;   // Page table for all of shared mem.
+
+    MESSAGE_QUEUE_INFO rpcQueues[RPC_QUEUE_COUNT];
+} MESSAGE_QUEUE_COLLECTION;
+
 //
 // Most of the following defines resolve to compile-time constants.
 //