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530.30.02

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This commit is contained in:
Andy Ritger
2023-02-28 11:12:44 -08:00
parent e598191e8e
commit 4397463e73
928 changed files with 124728 additions and 88525 deletions
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15
src/nvidia/inc/kernel/rmapi/control.h
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@@ -37,8 +37,8 @@ typedef RS_RES_CONTROL_PARAMS_INTERNAL RmCtrlParams;
// RMCTRL_API_COPPY_FLAGS is used to specify control api copy behavior.
#define RMCTRL_API_COPY_FLAGS_NONE 0x00000000
// skip memory copy in api copy in
#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN NVBIT(0)
// skip memory copy in api copy in and zero the buffer
#define RMCTRL_API_COPY_FLAGS_SKIP_COPYIN_ZERO_BUFFER NVBIT(0)
// set control cache on api copy out
#define RMCTRL_API_COPY_FLAGS_SET_CONTROL_CACHE NVBIT(1)
@@ -291,6 +291,17 @@ NV_STATUS embeddedParamCopyOut(RMAPI_PARAM_COPY *pParamCopy, RmCtrlParams *pRmC
//
#define RMCTRL_FLAGS_GSP_PLUGIN_FOR_VGPU_GSP 0x000100000
//
// This flag specifies that the control output depends on the input
// parameters but can be cached on receiving end. Since the control
// result depends on the input and the input varifies with controls,
// the cache should be handled in a per-control bases.
//
#define RMCTRL_FLAGS_CACHEABLE_BY_INPUT 0x000200000
// The combination of cacheable flags
#define RMCTRL_FLAGS_CACHEABLE_ANY (RMCTRL_FLAGS_CACHEABLE | RMCTRL_FLAGS_CACHEABLE_BY_INPUT)
//
// 'ACCESS_RIGHTS' Attribute
// ------------------------

20
src/nvidia/inc/kernel/rmapi/mapping_list.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -50,7 +50,6 @@ typedef struct _def_client_dma_alloc_map_info CLI_DMA_ALLOC_MAP_INFO;
//
struct _def_client_dma_mapping_info
{
NvHandle hDevice;
NvU64 DmaOffset;
void* KernelVAddr[NV_MAX_SUBDEVICES]; // Kernel's virtual address, if required
void* KernelPriv; // Token required to unmap the kernel mapping
@@ -60,11 +59,11 @@ struct _def_client_dma_mapping_info
NvU32 Flags;
NvBool bP2P;
NvU32 gpuMask;
NvU64 mapPageSize; // Page size at which the memory is mapped.
ADDRESS_TRANSLATION addressTranslation;
MEMORY_DESCRIPTOR *pBar1P2PVirtMemDesc; // The peer GPU mapped BAR1 region
MEMORY_DESCRIPTOR *pBar1P2PPhysMemDesc; // The peer GPU vidmem sub region
PCLI_DMA_MAPPING_INFO Next;
PCLI_DMA_MAPPING_INFO Prev;
CLI_DMA_MAPPING_INFO *pNext;
};
//
@@ -72,8 +71,7 @@ struct _def_client_dma_mapping_info
//
struct _def_client_dma_mapping_info_iterator
{
PNODE pDmaMappingList; // list of hDevices
PNODE pCurrentList; // current hDevice list entry, is list of pDmaMappings
PNODE pDmaMappingList; // list of pDmaMappings
PNODE pNextDmaMapping; // next pDmaMapping while iterating over the DmaOffsets
};
@@ -159,16 +157,14 @@ CliUpdateDeviceMemoryMapping
RsCpuMapping *CliFindMappingInClient (NvHandle, NvHandle, NvP64);
// DMA Mappings
NV_STATUS intermapCreateDmaMapping (RsClient *, RsResourceRef *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO *, NvU32);
NV_STATUS intermapRegisterDmaMapping (RsClient *, NvHandle, NvHandle, PCLI_DMA_MAPPING_INFO, NvU64, NvU32);
NV_STATUS intermapDelDmaMapping (RsClient *, NvHandle, NvHandle, NvU64, NvU32, NvBool*);
NV_STATUS intermapCreateDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO *, NvU32);
NV_STATUS intermapRegisterDmaMapping (RsClient *, VirtualMemory *, PCLI_DMA_MAPPING_INFO, NvU64, NvU32);
NV_STATUS intermapDelDmaMapping (RsClient *, VirtualMemory *, NvU64, NvU32);
void intermapFreeDmaMapping (PCLI_DMA_MAPPING_INFO);
CLI_DMA_MAPPING_INFO *intermapGetDmaMapping (VirtualMemory *pVirtualMemory, NvU64 dmaOffset, NvU32 gpuMask);
NvBool CliGetDmaMappingInfo (NvHandle, NvHandle, NvHandle, NvU64, NvU32, PCLI_DMA_MAPPING_INFO*);
void CliGetDmaMappingIterator (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR, PNODE pDmaMappingList);
void CliGetDmaMappingNext (PCLI_DMA_MAPPING_INFO *, PCLI_DMA_MAPPING_INFO_ITERATOR);
// Unmap all DMA mappings between a memory resource and any DynamicMemory
NV_STATUS intermapUnmapDeviceMemoryDma (RsClient *, RsResourceRef *, NvHandle);
#endif

12
src/nvidia/inc/kernel/rmapi/nv_gpu_ops.h
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@@ -76,26 +76,26 @@ NV_STATUS nvGpuOpsMemoryAllocSys (gpuAddressSpaceHandle vaSpace,
NV_STATUS nvGpuOpsPmaAllocPages(void *pPma,
NvLength pageCount,
NvU32 pageSize,
NvU64 pageSize,
gpuPmaAllocationOptions *pPmaAllocOptions,
NvU64 *pPages);
void nvGpuOpsPmaFreePages(void *pPma,
NvU64 *pPages,
NvLength pageCount,
NvU32 pageSize,
NvU64 pageSize,
NvU32 flags);
NV_STATUS nvGpuOpsPmaPinPages(void *pPma,
NvU64 *pPages,
NvLength pageCount,
NvU32 pageSize,
NvU64 pageSize,
NvU32 flags);
NV_STATUS nvGpuOpsPmaUnpinPages(void *pPma,
NvU64 *pPages,
NvLength pageCount,
NvU32 pageSize);
NvU64 pageSize);
NV_STATUS nvGpuOpsChannelAllocate(gpuAddressSpaceHandle vaSpace,
const gpuChannelAllocParams *params,
@@ -112,7 +112,7 @@ void nvGpuOpsMemoryFree(gpuAddressSpaceHandle vaSpace,
NV_STATUS nvGpuOpsMemoryCpuMap(gpuAddressSpaceHandle vaSpace,
NvU64 memory, NvLength length,
void **cpuPtr, NvU32 pageSize);
void **cpuPtr, NvU64 pageSize);
void nvGpuOpsMemoryCpuUnMap(gpuAddressSpaceHandle vaSpace,
void* cpuPtr);
@@ -270,4 +270,6 @@ NV_STATUS nvGpuOpsPagingChannelPushStream(UvmGpuPagingChannel *channel,
char *methodStream,
NvU32 methodStreamSize);
NV_STATUS nvGpuOpsFlushReplayableFaultBuffer(struct gpuDevice *device);
#endif /* _NV_GPU_OPS_H_*/

11
src/nvidia/inc/kernel/rmapi/rmapi.h
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@@ -63,6 +63,7 @@ void rmapiShutdown(void);
// already held then return error
#define RMAPI_LOCK_FLAGS_READ NVBIT(1) // Acquire API lock for READ
#define RMAPI_LOCK_FLAGS_WRITE (0x00000000) // Acquire API lock for WRITE - Default
#define RMAPI_LOCK_FLAGS_LOW_PRIORITY NVBIT(2) // Deprioritize lock acquire
/**
* Acquire the RM API Lock
@@ -147,11 +148,11 @@ struct _RM_API
NV_STATUS (*FreeWithSecInfo)(struct _RM_API *pRmApi, NvHandle hClient, NvHandle hObject,
NvU32 flags, API_SECURITY_INFO *pSecInfo);
// Free a list of clients with default security attributes
NV_STATUS (*FreeClientList)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients);
// Disables all clients in the list, with default security attributes
NV_STATUS (*DisableClients)(struct _RM_API *pRmApi, NvHandle *phClientList, NvU32 numClients);
// Free a list of clients
NV_STATUS (*FreeClientListWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList,
// Disables all clients in the list
NV_STATUS (*DisableClientsWithSecInfo)(struct _RM_API *pRmApi, NvHandle *phClientList,
NvU32 numClients, API_SECURITY_INFO *pSecInfo);
// Invoke a control with default security attributes and local pointers (no NvP64)
@@ -269,7 +270,7 @@ NvBool rmapiCmdIsCacheable(NvU32 cmd, NvBool bAllowInternal);
NV_STATUS rmapiControlCacheGet(NvHandle hClient, NvHandle hObject, NvU32 cmd,
void* params, NvU32 paramsSize);
NV_STATUS rmapiControlCacheSet(NvHandle hClient, NvHandle hObject, NvU32 cmd,
const void* params, NvU32 paramsSize);
void* params, NvU32 paramsSize);
NV_STATUS rmapiControlCacheSetGpuInstForObject(NvHandle hClient, NvHandle hObject, NvU32 gpuInst);
void rmapiControlCacheFreeAllCacheForGpu(NvU32 gpuInst);
void rmapiControlCacheSetMode(NvU32 mode);