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This commit is contained in:
Maneet Singh
2025-06-17 11:52:54 -07:00
parent d5cb404571
commit 443ace971f
36 changed files with 302 additions and 112 deletions
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6
src/nvidia/generated/g_gsync_nvoc.h
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@@ -14,7 +14,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -140,7 +140,7 @@ typedef NV_STATUS GsyncSetInterlaceMode (struct OBJGPU *, PDACEXTERNALDEVICE, N
typedef NV_STATUS GsyncRefSwapBarrier (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *);
typedef NV_STATUS GsyncRefSignal (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, GSYNCSYNCSIGNAL, NvBool TestRate, NvU32 *);
typedef NV_STATUS GsyncRefMaster (struct OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *, NvU32 *, NvBool, NvBool);
typedef NV_STATUS GsyncRefSlaves (struct OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *, NvU32 *);
typedef NV_STATUS GsyncRefSlaves (struct OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *, NvU32 *);
typedef NV_STATUS GsyncGetCplStatus (struct OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
typedef NV_STATUS GsyncSetWatchdog (struct OBJGPU *, PDACEXTERNALDEVICE, NvU32);
typedef NV_STATUS GsyncGetRevision (struct OBJGPU *, OBJGSYNC *, GSYNCCAPSPARAMS *);
@@ -154,7 +154,7 @@ typedef NV_STATUS GsyncGetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, N
typedef NV_STATUS GsyncSetHouseSyncMode (struct OBJGPU *, PDACEXTERNALDEVICE, NvU8);
typedef NV_STATUS GsyncGetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *);
typedef NV_STATUS GsyncSetMulDiv (struct OBJGPU *, DACEXTERNALDEVICE *, NV30F1_CTRL_GSYNC_MULTIPLY_DIVIDE_SETTINGS *);
typedef NV_STATUS GsyncSetRasterSyncDecodeMode (struct OBJGPU *, DACEXTERNALDEVICE *);
typedef NV_STATUS GsyncSetRasterSyncDecodeMode (struct OBJGPU *, struct OBJGPU *, DACEXTERNALDEVICE *);
typedef struct GSYNC_HAL_IFACES {

9
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5432,13 +5432,22 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2C05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti" },
{ 0x2C18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
{ 0x2C19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
{ 0x2C38, 0x0000, 0x0000, "NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU" },
{ 0x2C39, 0x0000, 0x0000, "NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU" },
{ 0x2C58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5090 Laptop GPU" },
{ 0x2C59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5080 Laptop GPU" },
{ 0x2D04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Ti" },
{ 0x2D05, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060" },
{ 0x2D18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D19, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },
{ 0x2F58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x13BD, 0x11cc, 0x10DE, "GRID M10-0B" },
{ 0x13BD, 0x11cd, 0x10DE, "GRID M10-1B" },

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -238,7 +238,7 @@ NV_STATUS gsyncRefSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFT
NV_STATUS gsyncRefMaster_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask,
NvU32 *Refresh, NvBool retainMaster,
NvBool skipSwapBarrierWar);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncRefSlaves_P2060 (OBJGPU *, OBJGSYNC *, REFTYPE, NvU32 *DisplayMask_s, NvU32 *Refresh);
NV_STATUS gsyncGetCplStatus_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncGetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetEmitTestSignal_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);

4
src/nvidia/inc/kernel/gpu/external_device/dac_p2061.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -33,6 +33,6 @@ NV_STATUS gsyncSetHouseSyncMode_P2061(OBJGPU *, DACEXTERNALDEVICE *, NvU8);
NV_STATUS gsyncGetCplStatus_P2061 (OBJGPU *, DACEXTERNALDEVICE *, GSYNCSTATUS, NvU32 *);
NV_STATUS gsyncSetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32);
NV_STATUS gsyncGetSyncSkew_P2061_V204(OBJGPU *, DACEXTERNALDEVICE *, NvU32 *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, DACEXTERNALDEVICE *);
NV_STATUS gsyncSetRasterSyncDecodeMode_P2061_V300(OBJGPU *, OBJGPU *, DACEXTERNALDEVICE *);
#endif // DAC_P2061_H

6
src/nvidia/inc/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.h
View File

@@ -183,16 +183,12 @@ void pmaFreeList(PMA *pPma, PRANGELISTTYPE *ppList);
* @param[in] physAddrBase The base address of this address tree
* @param[in] pBlacklistPageBase Structure that contains the blacklisted pages
* @param[in] blacklistCount Number of blacklisted pages
* @param[in] bBlacklistFromInforom Whether the blacklisted pages are coming from
* inforom (i.e., from heap/PMA init) or not
* (i.e., from ECC interrupt handling)
*
* @return NV_OK
* NV_ERR_NO_MEMORY if memory allocation fails
*/
NV_STATUS pmaRegisterBlacklistInfo(PMA *pPma, NvU64 physAddrBase,
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount,
NvBool bBlacklistFromInforom);
PPMA_BLACKLIST_ADDRESS pBlacklistPageBase, NvU32 blacklistCount);
/*!
* @brief Query blacklisting states tracked by PMA

2
src/nvidia/inc/kernel/rmapi/rmapi_utils.h
View File

@@ -63,6 +63,6 @@ NvBool rmapiutilIsExternalClassIdInternalOnly(NvU32 externalClassId);
NV_STATUS rmapiutilGetControlInfo(NvU32 cmd, NvU32 *pFlags,
NvU32 *pAccessRight, NvU32 *pParamsSize);
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd);
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(OBJGPU *pGpu, NvU32 cmd);
#endif /* RMAPI_UTILS_H */

10
src/nvidia/interface/nvrm_registry.h
View File

@@ -2719,4 +2719,14 @@
#define NV_REG_STR_RM_FB_SANITY_CHECK_DISABLE (0x00000000)
#define NV_REG_STR_RM_FB_SANITY_CHECK_DEFAULT NV_REG_STR_RM_FB_SANITY_CHECK_DISABLE
//
// Type DWORD
// Enable GR debug dump for CTXSW timeouts.
//
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP "RmCtxswTimeoutDebugDump"
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP_VAL 0:0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP_VAL_ENABLE 0x1
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP_VAL_DISABLE 0x0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP_VAL_DEFAULT NV_REG_STR_RM_CTXSW_TIMEOUT_DEBUG_DUMP_VAL_DISABLE
#endif // NVRM_REGISTRY_H

86
src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c
View File

@@ -53,7 +53,7 @@ static void gsyncProgramFramelockEnable_P2060(OBJGPU *, PDACP2060EXTERNALD
static NvBool gsyncIsStereoEnabled_p2060 (OBJGPU *, PDACEXTERNALDEVICE);
static NV_STATUS gsyncProgramExtStereoPolarity_P2060 (OBJGPU *, PDACEXTERNALDEVICE);
static NV_STATUS gsyncProgramSlaves_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE, NvU32);
static NV_STATUS gsyncProgramSlaves_P2060(OBJGPU *, OBJGSYNC *, NvU32);
static NvU32 gsyncReadSlaves_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE);
static NV_STATUS gsyncProgramMaster_P2060(OBJGPU *, OBJGSYNC *, NvU32, NvBool, NvBool);
static NvU32 gsyncReadMaster_P2060(OBJGPU *, PDACP2060EXTERNALDEVICE);
@@ -2444,9 +2444,10 @@ gsyncProgramMaster_P2060
//
// Set the RasterSync Decode Mode
// This may return an error if the FW and GPU combination is invalid
// In this case, the ServerGpu is the same Gpu
//
NV_CHECK_OK_OR_RETURN(LEVEL_WARNING,
pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pGsync->pExtDev));
pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pGpu, pGsync->pExtDev));
//
// GPU will now be TS - Mark sync source for GPU on derived index.
@@ -2631,7 +2632,7 @@ gsyncProgramMaster_P2060
Slaves = gsyncReadSlaves_P2060(pOtherGpu, pThis);
if (Slaves)
{
rmStatus = gsyncProgramSlaves_P2060(pOtherGpu, pThis, Slaves);
rmStatus = gsyncProgramSlaves_P2060(pOtherGpu, pGsync, Slaves);
if (NV_OK != rmStatus)
{
NV_PRINTF(LEVEL_ERROR,
@@ -2716,17 +2717,20 @@ static NV_STATUS
gsyncProgramSlaves_P2060
(
OBJGPU *pGpu,
PDACP2060EXTERNALDEVICE pThis,
OBJGSYNC *pGsync,
NvU32 Slaves
)
{
DACP2060EXTERNALDEVICE *pThis = (DACP2060EXTERNALDEVICE *)pGsync->pExtDev;
KernelDisplay *pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu);
NvU32 DisplayIds[OBJ_MAX_HEADS];
NvU32 iface, head, index;
NvU8 ctrl = 0, ctrl3 = 0;
NvBool bCoupled, bHouseSelect, bLocalMaster, bEnableSlaves = (0 != Slaves);
NV_STATUS rmStatus = NV_OK;
NvU32 numHeads = kdispGetNumHeads(pKernelDisplay);
NvU32 numHeads = kdispGetNumHeads(pKernelDisplay);
OBJSYS *pSys = SYS_GET_INSTANCE();
OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys);
// This utility fn returns display id's associated with each head.
extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds);
@@ -2811,6 +2815,72 @@ gsyncProgramSlaves_P2060
}
}
//
// The RasterSyncDecodeMode of this Gsync board needs to get written if
// the server GPU is not on it. Find the server GPU and write based on that
// GPU's RasterSyncDecodeMode value.
//
if (bEnableSlaves && !bLocalMaster && pGsyncMgr->gsyncCount > 1)
{
OBJGPU *pServerGpu = NULL;
NvU32 otherGsyncIndex;
// Loops only need to go until we find pServerGpu
for (otherGsyncIndex = 0;
(otherGsyncIndex < pGsyncMgr->gsyncCount) && (pServerGpu == NULL);
otherGsyncIndex++)
{
DACP2060EXTERNALDEVICE *pOtherExtDev =
(DACP2060EXTERNALDEVICE *)pGsyncMgr->gsyncTable[otherGsyncIndex].pExtDev;
NvU32 otherIfaceIndex;
if (pOtherExtDev == pThis)
{
//
// If the server GPU is on this same GSync board, we don't need
// to write anything, so don't bother checking
//
continue;
}
for (otherIfaceIndex = 0;
(otherIfaceIndex < NV_P2060_MAX_IFACES_PER_GSYNC) && (pServerGpu == NULL);
otherIfaceIndex++)
{
NvU32 otherHeadIndex;
NvU32 serverBitmask = 0;
if (!pOtherExtDev->Iface[otherIfaceIndex].GpuInfo.connected)
{
continue;
}
for (otherHeadIndex = 0; otherHeadIndex < OBJ_MAX_HEADS; otherHeadIndex++)
{
serverBitmask |= pOtherExtDev->Iface[otherIfaceIndex].Sync.Master[otherHeadIndex];
}
if (serverBitmask == 0)
{
continue;
}
// This GPU is the server!
pServerGpu = gpumgrGetGpuFromId(pOtherExtDev->Iface[otherIfaceIndex].GpuInfo.gpuId);
}
}
if (pServerGpu != NULL)
{
//
// Set the RasterSync Decode Mode
// This may return an error if the FW and GPU combination is invalid
//
NV_CHECK_OK_OR_RETURN(LEVEL_WARNING,
pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pServerGpu, pGsync->pExtDev));
}
}
//
// With House sync enabled the crashlocking still need some investigations.
// So filter out Housesyced systems before doing local crashlocks.
@@ -3926,13 +3996,13 @@ NV_STATUS
gsyncRefSlaves_P2060
(
OBJGPU *pGpu,
PDACEXTERNALDEVICE pExtDev,
OBJGSYNC *pGsync,
REFTYPE rType,
NvU32 *pDisplayMasks,
NvU32 *pRefresh
)
{
PDACP2060EXTERNALDEVICE pThis = (PDACP2060EXTERNALDEVICE)pExtDev;
PDACP2060EXTERNALDEVICE pThis = (DACP2060EXTERNALDEVICE *)pGsync->pExtDev;
NV_STATUS status = NV_OK;
NvU32 Slaves = pThis->Slaves;
NvU32 RefreshRate = pThis->RefreshRate;
@@ -3952,7 +4022,7 @@ gsyncRefSlaves_P2060
switch ( rType )
{
case refSetCommit:
status = gsyncProgramSlaves_P2060(pGpu, pThis, Slaves);
status = gsyncProgramSlaves_P2060(pGpu, pGsync, Slaves);
break;
case refFetchGet:

15
src/nvidia/src/kernel/gpu/external_device/arch/pascal/kern_gsync_p2061.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2016-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -256,25 +256,30 @@ gsyncGetSyncSkew_P2061_V204
return NV_OK;
}
//
// Determine and write the proper RasterSync Decode Mode to the CONTROL5 register
// The RasterSync Decode Mode will be queried from the Server GPU, which may
// not be the same GPU that we are writing this register via.
//
NV_STATUS
gsyncSetRasterSyncDecodeMode_P2061_V300
(
OBJGPU *pGpu,
OBJGPU *pServerGpu,
DACEXTERNALDEVICE *pExtDev
)
{
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS
rasterSyncDecodeModeParams;
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pServerGpu);
NvU8 old_data, data;
//
// Get the raster sync mode flag from the GPU
// Get the raster sync mode flag from the server GPU
// This is only used in P2061 v3.00+ for gsyncSetRasterDecodeMode()
//
NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient,
pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE,
NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pServerGpu->hInternalClient,
pServerGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE,
&rasterSyncDecodeModeParams, sizeof(rasterSyncDecodeModeParams)));
NV_ASSERT_OK_OR_RETURN(readregu008_extdeviceTargeted(pGpu, pExtDev, (NvU8)NV_P2061_CONTROL5, &data));

23
src/nvidia/src/kernel/gpu/external_device/gsync.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -1178,7 +1178,7 @@ gsyncIsAnyHeadFramelocked(OBJGSYNC *pGsync)
{
// Check if assigned slaves displays are there.
if ((NV_OK == pGsync->gsyncHal.gsyncRefSlaves(pGpu,
pGsync->pExtDev, refRead, &assigned, &refresh)) &&
pGsync, refRead, &assigned, &refresh)) &&
(assigned != 0))
{
return NV_TRUE;
@@ -1469,7 +1469,7 @@ gsyncGetControlSync(OBJGSYNC *pGsync,
}
else
{
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev, refFetchGet,
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync, refFetchGet,
&pParams->displays, &pParams->refresh);
}
}
@@ -1545,10 +1545,10 @@ gsyncSetControlSync(OBJGSYNC *pGsync,
}
else
{
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev,
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync,
refRead, &assigned, &refresh);
pParams->displays |= assigned;
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev,
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync,
refSetCommit, &pParams->displays, &pParams->refresh);
}
@@ -1599,10 +1599,10 @@ gsyncSetControlUnsync(OBJGSYNC *pGsync,
}
else
{
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev,
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync,
refRead, &assigned, &refresh);
pParams->displays = assigned & ~pParams->displays;
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync->pExtDev,
status |= pGsync->gsyncHal.gsyncRefSlaves(pGpu, pGsync,
refSetCommit, &pParams->displays, &refresh);
}
@@ -2385,7 +2385,7 @@ static NV_STATUS
gsyncNullRefSlaves
(
OBJGPU *pGpu,
PDACEXTERNALDEVICE pExtDev,
OBJGSYNC *pGsync,
REFTYPE rType,
NvU32 *pDisplayMasks,
NvU32 *pRefresh
@@ -2498,6 +2498,7 @@ static NV_STATUS
gsyncNullSetRasterSyncDecodeMode
(
OBJGPU *pGpu,
OBJGPU *pServerGpu,
DACEXTERNALDEVICE *pExtDev
)
{
@@ -2507,11 +2508,11 @@ gsyncNullSetRasterSyncDecodeMode
//
NV2080_CTRL_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE_PARAMS
rasterSyncDecodeModeParams;
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pGpu);
RM_API *pRmApi = GPU_GET_PHYSICAL_RMAPI(pServerGpu);
// Pre-3.00 FW can only use NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE
NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pGpu->hInternalClient,
pGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE,
NV_ASSERT_OK_OR_RETURN(pRmApi->Control(pRmApi, pServerGpu->hInternalClient,
pServerGpu->hInternalSubdevice, NV2080_CTRL_CMD_INTERNAL_GSYNC_GET_RASTER_SYNC_DECODE_MODE,
&rasterSyncDecodeModeParams, sizeof(rasterSyncDecodeModeParams)));
NV_CHECK_OR_RETURN(LEVEL_WARNING,

1
src/nvidia/src/kernel/gpu/gsp/arch/blackwell/kernel_gsp_ecc_gb100.c
View File

@@ -137,4 +137,5 @@ kgspEccServiceUncorrError_GB100
gpuNotifySubDeviceEvent(pGpu, NV2080_NOTIFIERS_ECC_DBE, NULL, 0, 0,
(NvU16)NV2080_CTRL_GPU_ECC_UNIT_GSP);
nvErrorLog_va((void *)pGpu, errorType, "GSP-RISCV uncorrectable ECC error");
nvErrorLog_va((void *)pGpu, UNCORRECTABLE_SRAM_ERROR, "GSP-RISCV, Uncorrectable SRAM error");
}

4
src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator.c
View File

@@ -534,7 +534,7 @@ pmaRegisterRegion
PMA_SCRUB_INITIALIZE);
}
status = pmaRegisterBlacklistInfo(pPma, physBase, pBlacklistPageBase, blacklistCount, NV_TRUE);
status = pmaRegisterBlacklistInfo(pPma, physBase, pBlacklistPageBase, blacklistCount);
if (status != NV_OK)
{
pPma->pMapInfo->pmaMapDestroy(pMap);
@@ -1971,7 +1971,7 @@ pmaAddToBlacklistTracking
{
blacklistPages.physOffset = physAddr;
blacklistPages.bIsDynamic = NV_TRUE;
status = pmaRegisterBlacklistInfo(pPma, 0, &blacklistPages, 1, NV_FALSE);
status = pmaRegisterBlacklistInfo(pPma, 0, &blacklistPages, 1);
}
return status;
}

43
src/nvidia/src/kernel/gpu/mem_mgr/phys_mem_allocator/phys_mem_allocator_util.c
View File

@@ -1239,8 +1239,7 @@ pmaRegisterBlacklistInfo
PMA *pPma,
NvU64 physAddrBase,
PMA_BLACKLIST_ADDRESS *pBlacklistPageBase,
NvU32 blacklistCount,
NvBool bBlacklistFromInforom
NvU32 blacklistCount
)
{
NvU32 i;
@@ -1288,34 +1287,24 @@ pmaRegisterBlacklistInfo
// This is only needed for NUMA systems that auto online NUMA memory.
// Other systems (e.g., P9) already do blacklisting in nvidia-persistenced.
//
// Page blacklisting is done regardless of whether it will also be done by
// CPU RAS_FW via CPER handling (which is done in non-vGPU cases).
// This is fine, because multiple simultaneous calls to page blacklisting
// API memory_failure() do not cause any issues.
//
if (pPma->bNuma && pPma->bNumaAutoOnline)
{
//
// Only blacklist pages from inforom (i.e., during heap/PMA init) need
// to be blacklisted with kernel here. The blacklist pages stored in
// inforom need to remain blacklisted persistently across GPU resets -
// kernel won't automatically blacklist these so RM must do it
// explicitly here.
//
// Blacklist pages not from inforom (i.e., from ECC interrupt handling)
// do not need to be blacklisted with kernel. This is because the ECC
// interrupt will automatically trigger kernel itself to blacklist the page.
//
if (bBlacklistFromInforom)
NV_STATUS status;
NV_PRINTF(LEVEL_INFO,
"NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n",
pBlacklistPageBase[blacklistEntryIn].physOffset,
pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase);
status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase);
if (status != NV_OK)
{
NV_STATUS status;
// Use physOffset without 64K alignment, because kernel may use a different page size.
NV_PRINTF(LEVEL_INFO,
"NUMA enabled - blacklisting page through kernel at address 0x%llx (GPA) 0x%llx (SPA)\n",
pBlacklistPageBase[blacklistEntryIn].physOffset,
pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase);
status = osOfflinePageAtAddress(pBlacklistPageBase[blacklistEntryIn].physOffset + pPma->coherentCpuFbBase);
if (status != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status);
}
NV_PRINTF(LEVEL_ERROR, "osOfflinePageAtAddress() failed with status: %d\n", status);
}
}

5
src/nvidia/src/kernel/gpu/mig_mgr/arch/ampere/kmigmgr_ga100.c
View File

@@ -173,6 +173,11 @@ kmigmgrIsGPUInstanceFlagValid_GA100
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG,
_GFX_SIZE, gpuInstanceFlag);
if (!FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag))
{
return NV_FALSE;
}
switch (memSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL:

5
src/nvidia/src/kernel/gpu/mig_mgr/arch/blackwell/kmigmgr_gb100.c
View File

@@ -50,6 +50,11 @@ kmigmgrIsGPUInstanceFlagValid_GB100
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG,
_GFX_SIZE, gpuInstanceFlag);
if (!FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag))
{
return NV_FALSE;
}
switch (memSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL:

5
src/nvidia/src/kernel/gpu/mig_mgr/arch/blackwell/kmigmgr_gb10b.c
View File

@@ -145,6 +145,11 @@ kmigmgrIsGPUInstanceFlagValid_GB10B
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG,
_GFX_SIZE, gpuInstanceFlag);
if (!FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag))
{
return NV_FALSE;
}
switch (memSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL:

15
src/nvidia/src/kernel/gpu/mig_mgr/arch/blackwell/kmigmgr_gb202.c
View File

@@ -50,6 +50,14 @@ kmigmgrIsGPUInstanceFlagValid_GB202
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG,
_GFX_SIZE, gpuInstanceFlag);
// If incorrect all video flag, then fail
if (!(FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag) ||
FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _ENABLE, gpuInstanceFlag) ||
FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DISABLE, gpuInstanceFlag)))
{
return NV_FALSE;
}
switch (memSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL:
@@ -141,6 +149,11 @@ kmigmgrIsGPUInstanceCombinationValid_GB202
{
return NV_FALSE;
}
if (!FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag))
{
return NV_FALSE;
}
}
switch (computeSizeFlag)
@@ -148,6 +161,8 @@ kmigmgrIsGPUInstanceCombinationValid_GB202
case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_FULL:
NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL,
NV_FALSE);
NV_CHECK_OR_RETURN(LEVEL_SILENT, FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT,
gpuInstanceFlag), NV_FALSE);
break;
case NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_HALF:
NV_CHECK_OR_RETURN(LEVEL_SILENT, memSizeFlag == NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_HALF,

6
src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c
View File

@@ -51,6 +51,12 @@ kmigmgrIsGPUInstanceFlagValid_GH100
_COMPUTE_SIZE, gpuInstanceFlag);
NvU32 gfxSizeFlag = DRF_VAL(2080_CTRL_GPU, _PARTITION_FLAG,
_GFX_SIZE, gpuInstanceFlag);
if (!FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_ALL_MEDIA, _DEFAULT, gpuInstanceFlag))
{
return NV_FALSE;
}
switch (memSizeFlag)
{
case NV2080_CTRL_GPU_PARTITION_FLAG_MEMORY_SIZE_FULL:

2
src/nvidia/src/kernel/gpu/mig_mgr/gpu_instance_subscription.c
View File

@@ -442,7 +442,7 @@ gisubscriptionCtrlCmdExecPartitionsCreate_IMPL
.inst.request.requestFlags = pParams->flags
};
if (!hypervisorIsVgxHyper())
if (!gpuIsSriovEnabled(pGpu))
{
request.inst.request.requestFlags = FLD_SET_DRF(C637_CTRL, _DMA_EXEC_PARTITIONS_CREATE_REQUEST, _WITH_PART_ID, _FALSE, request.inst.request.requestFlags);
}

2
src/nvidia/src/kernel/rmapi/control.c
View File

@@ -728,7 +728,7 @@ NV_STATUS serverControl_ValidateCookie
(pRmCtrlExecuteCookie->ctrlFlags & RMCTRL_FLAGS_ROUTE_TO_PHYSICAL) &&
!(pRmCtrlExecuteCookie->ctrlFlags & (RMCTRL_FLAGS_ROUTE_TO_VGPU_HOST | RMCTRL_FLAGS_PHYSICAL_IMPLEMENTED_ON_VGPU_GUEST)))
{
if (!rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(pRmCtrlParams->cmd))
if (!rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(pRmCtrlParams->pGpu, pRmCtrlParams->cmd))
{
NV_PRINTF(LEVEL_ERROR, "Unsupported ROUTE_TO_PHYSICAL control 0x%x was called on vGPU guest\n", pRmCtrlParams->cmd);
}

7
src/nvidia/src/kernel/rmapi/rmapi_utils.c
View File

@@ -35,6 +35,7 @@
#include "ctrl/ctrl2080.h"
#include "ctrl/ctrl402c.h"
#include "ctrl/ctrl90cc.h"
#include "ctrl/ctrl90e6.h"
#include "ctrl/ctrl90e7/ctrl90e7bbx.h"
NV_STATUS
@@ -194,7 +195,7 @@ rmapiutilGetControlInfo
return NV_ERR_OBJECT_NOT_FOUND;
}
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd)
NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(OBJGPU *pGpu, NvU32 cmd)
{
switch (cmd)
{
@@ -239,6 +240,10 @@ NvBool rmapiutilSkipErrorMessageForUnsupportedVgpuGuestControl(NvU32 cmd)
case NV90E7_CTRL_CMD_BBX_GET_LAST_FLUSH_TIME:
return NV_TRUE;
case NV90E6_CTRL_CMD_MASTER_GET_ERROR_INTR_OFFSET_MASK:
if (!IsTURINGorBetter(pGpu))
return NV_TRUE;
default:
return NV_FALSE;
}

4
src/nvidia/src/kernel/vgpu/vgpu_util.c
View File

@@ -267,7 +267,7 @@ static NV_STATUS vgpuExpandSysmemPfnBitMapList(OBJGPU *pGpu, NvU64 pfn)
vgpuSysmemPfnInfo.guestMaxPfn = node->nodeEndPfn;
vgpuSysmemPfnInfo.sizeInBytes = vgpuSysmemPfnInfo.guestMaxPfn / 8;
} while (vgpuSysmemPfnInfo.guestMaxPfn < pfn);
} while (vgpuSysmemPfnInfo.guestMaxPfn <= pfn);
// Alloc the ref count buffer
temp_pfn_ref_count = portMemAllocNonPaged(sizeof(NvU16) * vgpuSysmemPfnInfo.guestMaxPfn);
@@ -445,7 +445,7 @@ NV_STATUS vgpuUpdateSysmemPfnBitMap
if (bAlloc)
{
if (pfn > vgpuSysmemPfnInfo.guestMaxPfn)
if (pfn >= vgpuSysmemPfnInfo.guestMaxPfn)
{
NV_PRINTF(LEVEL_INFO, "Update sysmem pfn bitmap for pfn: 0x%llx > guestMaxPfn: 0x%llx\n",
pfn, vgpuSysmemPfnInfo.guestMaxPfn);