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535.183.01

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This commit is contained in:
Bernhard Stoeckner
2024-06-04 10:45:14 +02:00
parent f4bdce9a0a
commit 4459285b60
43 changed files with 2447 additions and 1544 deletions
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3
src/common/displayport/inc/dp_connectorimpl.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -299,6 +299,7 @@ namespace DisplayPort
bool bDisableSSC;
bool bEnableFastLT;
NvU32 maxLinkRateFromRegkey;
bool bFlushTimeslotWhenDirty;
//
// Latency(ms) to apply between link-train and FEC enable for bug

10
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -66,7 +66,7 @@
#define NV_DP_REGKEY_POWER_DOWN_PHY "DP_POWER_DOWN_PHY"
//
// Regkey to re-assess max link if the first assessed link config
// Regkey to re-assess max link if the first assessed link config
// is lower than the panel max
//
#define NV_DP_REGKEY_REASSESS_MAX_LINK "DP_REASSESS_MAX_LINK"
@@ -77,11 +77,12 @@
//
#define NV_DP_DSC_MST_CAP_BUG_3143315 "DP_DSC_MST_CAP_BUG_3143315"
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
// Bug 4426624: Flush timeslot change to HW when dirty bit is set.
#define NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY "DP_BUG_4426624_WAR"
//
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -117,6 +118,7 @@ struct DP_REGKEY_DATABASE
bool bCheckFECForDynamicMuxDSCPanel;
bool bReassessMaxLink;
bool bMSTPCONCapsReadDisabled;
bool bFlushTimeslotWhenDirty;
};
#endif //INCLUDED_DP_REGKEYDATABASE_H

4
src/common/displayport/src/dp_connectorimpl.cpp
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@@ -172,6 +172,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
this->bFlushTimeslotWhenDirty = dpRegkeyDatabase.bFlushTimeslotWhenDirty;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -5234,7 +5235,8 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
}
}
if (linkUseMultistream() && group && group->isHeadAttached() && group->timeslot.count)
if (linkUseMultistream() && group && group->isHeadAttached() &&
(group->timeslot.count || (this->bFlushTimeslotWhenDirty && group->timeslot.hardwareDirty)))
{
// Detach all the panels from payload
for (Device * d = group->enumDevices(0); d; d = group->enumDevices(d))

5
src/common/displayport/src/dp_evoadapter.cpp
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -96,7 +96,8 @@ const struct
{NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL, &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY, &dpRegkeyDatabase.bFlushTimeslotWhenDirty, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r535_00
#define NV_BUILD_BRANCH r538_67
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r535_00
#define NV_PUBLIC_BRANCH r538_67
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r535_00-537"
#define NV_BUILD_CHANGELIST_NUM (34218726)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r535/r538_67-552"
#define NV_BUILD_CHANGELIST_NUM (34280977)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r535/r535_00-537"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
#define NV_BUILD_NAME "rel/gpu_drv/r535/r538_67-552"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34280977)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r535_00-549"
#define NV_BUILD_CHANGELIST_NUM (34218726)
#define NV_BUILD_BRANCH_VERSION "r538_67-1"
#define NV_BUILD_CHANGELIST_NUM (34280977)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "538.62"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
#define NV_BUILD_NAME "538.69"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34280977)
#define NV_BUILD_BRANCH_BASE_VERSION R535
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "535.179"
#define NV_VERSION_STRING "535.183.01"
#else

62
src/common/inc/swref/published/ampere/ga100/dev_runlist.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,4 +24,64 @@
#ifndef __ga100_dev_runlist_h__
#define __ga100_dev_runlist_h__
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#endif // __ga100_dev_runlist_h__

4
src/common/nvlink/interface/nvlink.h
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@@ -70,8 +70,8 @@ extern "C" {
// Link Transition Timeouts in miliseconds
#define NVLINK_TRANSITION_OFF_TIMEOUT 1
#define NVLINK_TRANSITION_SAFE_TIMEOUT 300
#define NVLINK_TRANSITION_HS_TIMEOUT 8000
#define NVLINK_TRANSITION_SAFE_TIMEOUT 70
#define NVLINK_TRANSITION_HS_TIMEOUT 7000
#define NVLINK_TRANSITION_ACTIVE_PENDING 2000
#define NVLINK_TRANSITION_POST_HS_TIMEOUT 70

1098
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
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File diff suppressed because it is too large Load Diff

1098
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
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File diff suppressed because it is too large Load Diff

7
src/common/uproc/os/common/include/nv-crashcat-decoder.h
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@@ -193,6 +193,13 @@ NV_CRASHCAT_CAUSE_TYPE crashcatReportV1SourceCauseType(NvCrashCatReport_V1 *pRep
pReport->sourceCause);
}
static NV_INLINE
NV_CRASHCAT_CONTAINMENT crashcatReportV1SourceCauseContainment(NvCrashCatReport_V1 *pReport)
{
return (NV_CRASHCAT_CONTAINMENT)DRF_VAL64(_CRASHCAT, _REPORT_V1_SOURCE_CAUSE, _CONTAINMENT,
pReport->sourceCause);
}
//
// CrashCat RISC-V 64-bit CSR State V1 Bitfield Accessors
//

27
src/common/uproc/os/common/include/nv-crashcat.h
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@@ -226,6 +226,16 @@ typedef enum {
NV_CRASHCAT_RISCV_MODE_LAST = 0x3,
} NV_CRASHCAT_RISCV_MODE;
typedef enum {
NV_CRASHCAT_CONTAINMENT_UNSPECIFIED = 0x0,
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_M = NV_CRASHCAT_RISCV_MODE_M,
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_S = NV_CRASHCAT_RISCV_MODE_S,
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_U = NV_CRASHCAT_RISCV_MODE_U,
NV_CRASHCAT_CONTAINMENT_RISCV_HART = 0x4,
NV_CRASHCAT_CONTAINMENT_UNCONTAINED = 0xF,
NV_CRASHCAT_CONTAINMENT_LAST = 0xF
} NV_CRASHCAT_CONTAINMENT;
//
// CrashCat Partition
// Represents a NVRISC-V microcode partition index
@@ -589,7 +599,22 @@ typedef struct NvCrashCatReport_V1 {
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_EXCEPTION NV_CRASHCAT_CAUSE_TYPE_EXCEPTION
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_TIMEOUT NV_CRASHCAT_CAUSE_TYPE_TIMEOUT
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_TYPE_PANIC NV_CRASHCAT_CAUSE_TYPE_PANIC
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_RESERVED 31:4
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT 7:4
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_UNSPECIFIED \
NV_CRASHCAT_CONTAINMENT_UNSPECIFIED
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_RISCV_MODE_M \
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_M
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_RISCV_MODE_S \
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_S
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_RISCV_MODE_U \
NV_CRASHCAT_CONTAINMENT_RISCV_MODE_U
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_RISCV_HART \
NV_CRASHCAT_CONTAINMENT_RISCV_HART
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_CONTAINMENT_UNCONTAINED \
NV_CRASHCAT_CONTAINMENT_UNCONTAINED
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_RESERVED 31:8
#define NV_CRASHCAT_REPORT_V1_SOURCE_CAUSE_IMPL_DEF 63:32
//