mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-05 15:49:58 +00:00
560.28.03
This commit is contained in:
Gaurav Juvekar
@@ -124,6 +124,10 @@ void uvm_hal_hopper_host_tlb_invalidate_all(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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NvU32 depth,
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uvm_membar_t membar);
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void uvm_hal_blackwell_host_tlb_invalidate_all(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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NvU32 depth,
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uvm_membar_t membar);
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// Issue a TLB invalidate applying to the specified VA range in a PDB.
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//
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@@ -197,6 +201,13 @@ void uvm_hal_hopper_host_tlb_invalidate_va(uvm_push_t *push,
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NvU64 size,
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NvU64 page_size,
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uvm_membar_t membar);
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void uvm_hal_blackwell_host_tlb_invalidate_va(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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NvU32 depth,
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NvU64 base,
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NvU64 size,
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NvU64 page_size,
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uvm_membar_t membar);
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typedef void (*uvm_hal_host_tlb_invalidate_test_t)(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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@@ -216,6 +227,9 @@ void uvm_hal_ampere_host_tlb_invalidate_test(uvm_push_t *push,
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void uvm_hal_hopper_host_tlb_invalidate_test(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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UVM_TEST_INVALIDATE_TLB_PARAMS *params);
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void uvm_hal_blackwell_host_tlb_invalidate_test(uvm_push_t *push,
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uvm_gpu_phys_address_t pdb,
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UVM_TEST_INVALIDATE_TLB_PARAMS *params);
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// By default all semaphore release operations include a membar sys before the
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// operation. This can be affected by using UVM_PUSH_FLAG_NEXT_* flags with
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@@ -457,6 +471,7 @@ void uvm_hal_turing_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_ampere_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_ada_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_hopper_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_blackwell_arch_init_properties(uvm_parent_gpu_t *parent_gpu);
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// Retrieve the page-tree HAL for a given big page size
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typedef uvm_mmu_mode_hal_t *(*uvm_hal_lookup_mode_hal_t)(NvU64 big_page_size);
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@@ -468,27 +483,19 @@ uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_volta(NvU64 big_page_size);
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uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_turing(NvU64 big_page_size);
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uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_ampere(NvU64 big_page_size);
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uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_hopper(NvU64 big_page_size);
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uvm_mmu_mode_hal_t *uvm_hal_mmu_mode_blackwell(NvU64 big_page_size);
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void uvm_hal_maxwell_mmu_enable_prefetch_faults_unsupported(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_maxwell_mmu_disable_prefetch_faults_unsupported(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_pascal_mmu_enable_prefetch_faults(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_pascal_mmu_disable_prefetch_faults(uvm_parent_gpu_t *parent_gpu);
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// Convert a faulted MMU engine ID to a UVM engine type. Only engines which have
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// faults serviced by UVM are handled. On Pascal the only such engine is
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// GRAPHICS, so no translation is provided.
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typedef uvm_mmu_engine_type_t (*uvm_hal_mmu_engine_id_to_type_t)(NvU16 mmu_engine_id);
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uvm_mmu_engine_type_t uvm_hal_maxwell_mmu_engine_id_to_type_unsupported(NvU16 mmu_engine_id);
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uvm_mmu_engine_type_t uvm_hal_volta_mmu_engine_id_to_type(NvU16 mmu_engine_id);
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uvm_mmu_engine_type_t uvm_hal_turing_mmu_engine_id_to_type(NvU16 mmu_engine_id);
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uvm_mmu_engine_type_t uvm_hal_ampere_mmu_engine_id_to_type(NvU16 mmu_engine_id);
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uvm_mmu_engine_type_t uvm_hal_hopper_mmu_engine_id_to_type(NvU16 mmu_engine_id);
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typedef NvU16 (*uvm_hal_mmu_client_id_to_utlb_id_t)(NvU16 client_id);
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NvU16 uvm_hal_maxwell_mmu_client_id_to_utlb_id_unsupported(NvU16 client_id);
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NvU16 uvm_hal_pascal_mmu_client_id_to_utlb_id(NvU16 client_id);
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NvU16 uvm_hal_volta_mmu_client_id_to_utlb_id(NvU16 client_id);
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NvU16 uvm_hal_ampere_mmu_client_id_to_utlb_id(NvU16 client_id);
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NvU16 uvm_hal_hopper_mmu_client_id_to_utlb_id(NvU16 client_id);
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NvU16 uvm_hal_blackwell_mmu_client_id_to_utlb_id(NvU16 client_id);
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// Replayable faults
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typedef void (*uvm_hal_enable_replayable_faults_t)(uvm_parent_gpu_t *parent_gpu);
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@@ -498,6 +505,9 @@ typedef NvU32 (*uvm_hal_fault_buffer_read_put_t)(uvm_parent_gpu_t *parent_gpu);
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typedef NvU32 (*uvm_hal_fault_buffer_read_get_t)(uvm_parent_gpu_t *parent_gpu);
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typedef void (*uvm_hal_fault_buffer_write_get_t)(uvm_parent_gpu_t *parent_gpu, NvU32 get);
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typedef NvU8 (*uvm_hal_fault_buffer_get_ve_id_t)(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type);
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typedef uvm_mmu_engine_type_t (*uvm_hal_fault_buffer_get_mmu_engine_type_t)(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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// Parse the replayable entry at the given buffer index. This also clears the
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// valid bit of the entry in the buffer.
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@@ -535,6 +545,9 @@ NvU32 uvm_hal_maxwell_fault_buffer_read_put_unsupported(uvm_parent_gpu_t *parent
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NvU32 uvm_hal_maxwell_fault_buffer_read_get_unsupported(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_maxwell_fault_buffer_write_get_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index);
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NvU8 uvm_hal_maxwell_fault_buffer_get_ve_id_unsupported(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type);
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uvm_mmu_engine_type_t uvm_hal_maxwell_fault_buffer_get_mmu_engine_type_unsupported(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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uvm_fault_type_t uvm_hal_maxwell_fault_buffer_get_fault_type_unsupported(const NvU32 *fault_entry);
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void uvm_hal_pascal_enable_replayable_faults(uvm_parent_gpu_t *parent_gpu);
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@@ -550,12 +563,31 @@ NvU32 uvm_hal_volta_fault_buffer_read_put(uvm_parent_gpu_t *parent_gpu);
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NvU32 uvm_hal_volta_fault_buffer_read_get(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_volta_fault_buffer_write_get(uvm_parent_gpu_t *parent_gpu, NvU32 index);
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NvU8 uvm_hal_volta_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type);
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uvm_mmu_engine_type_t uvm_hal_volta_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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uvm_fault_type_t uvm_hal_volta_fault_buffer_get_fault_type(const NvU32 *fault_entry);
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void uvm_hal_turing_disable_replayable_faults(uvm_parent_gpu_t *parent_gpu);
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void uvm_hal_turing_clear_replayable_faults(uvm_parent_gpu_t *parent_gpu, NvU32 get);
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uvm_mmu_engine_type_t uvm_hal_turing_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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uvm_mmu_engine_type_t uvm_hal_ampere_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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NvU8 uvm_hal_hopper_fault_buffer_get_ve_id(NvU16 mmu_engine_id, uvm_mmu_engine_type_t mmu_engine_type);
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uvm_mmu_engine_type_t uvm_hal_hopper_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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uvm_mmu_engine_type_t uvm_hal_blackwell_fault_buffer_get_mmu_engine_type(NvU16 mmu_engine_id,
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uvm_fault_client_type_t client_type,
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NvU16 client_id);
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uvm_fault_type_t uvm_hal_blackwell_fault_buffer_get_fault_type(const NvU32 *fault_entry);
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bool uvm_hal_maxwell_fault_buffer_entry_is_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index);
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void uvm_hal_maxwell_fault_buffer_entry_clear_valid_unsupported(uvm_parent_gpu_t *parent_gpu, NvU32 index);
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@@ -779,7 +811,6 @@ struct uvm_arch_hal_struct
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uvm_hal_lookup_mode_hal_t mmu_mode_hal;
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uvm_hal_mmu_enable_prefetch_faults_t enable_prefetch_faults;
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uvm_hal_mmu_disable_prefetch_faults_t disable_prefetch_faults;
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uvm_hal_mmu_engine_id_to_type_t mmu_engine_id_to_type;
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uvm_hal_mmu_client_id_to_utlb_id_t mmu_client_id_to_utlb_id;
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};
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@@ -792,6 +823,7 @@ struct uvm_fault_buffer_hal_struct
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uvm_hal_fault_buffer_read_get_t read_get;
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uvm_hal_fault_buffer_write_get_t write_get;
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uvm_hal_fault_buffer_get_ve_id_t get_ve_id;
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uvm_hal_fault_buffer_get_mmu_engine_type_t get_mmu_engine_type;
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uvm_hal_fault_buffer_parse_replayable_entry_t parse_replayable_entry;
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uvm_hal_fault_buffer_entry_is_valid_t entry_is_valid;
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uvm_hal_fault_buffer_entry_clear_valid_t entry_clear_valid;
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