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This commit is contained in:
Gaurav Juvekar
2024-07-19 15:45:15 -07:00
parent 5fdf5032fb
commit 448d5cc656
859 changed files with 165424 additions and 91129 deletions
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51
src/common/displayport/inc/dp_configcaps.h
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@@ -346,21 +346,21 @@ namespace DisplayPort
return false;
}
// Convert Link Bandwidth read from DPCD register to Linkrate
NvU64 mapLinkBandiwdthToLinkrate(NvU32 linkBandwidth)
// Convert Link Bandwidth read from DPCD 00001h/2201h 8b10b_MAX_LINK_RATE to 10M convention link rate
NvU32 mapLinkBandiwdthToLinkrate(NvU32 linkBandwidth)
{
if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _1_62_GBPS, linkBandwidth))
return RBR;
return dp2LinkRate_1_62Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _2_70_GBPS, linkBandwidth))
return HBR;
return dp2LinkRate_2_70Gbps;
else if (FLD_TEST_DRF(_DPCD, _MAX_LINK_BANDWIDTH, _VAL, _5_40_GBPS, linkBandwidth))
return HBR2;
return dp2LinkRate_5_40Gbps;
else if (FLD_TEST_DRF(_DPCD14, _MAX_LINK_BANDWIDTH, _VAL, _8_10_GBPS, linkBandwidth))
return HBR3;
return dp2LinkRate_8_10Gbps;
else
{
DP_ASSERT(0 && "Unknown link bandwidth. Assuming HBR");
return HBR;
return dp2LinkRate_2_70Gbps;
}
}
@@ -395,6 +395,7 @@ namespace DisplayPort
virtual void setDPCDOffline(bool enable) = 0;
virtual void updateDPCDOffline() = 0;
virtual bool auxAccessAvailable() = 0;
virtual void setSupportsESI(bool bIsESISupported) = 0;
virtual void setLttprSupported(bool isLttprSupported) = 0;
@@ -532,7 +533,8 @@ namespace DisplayPort
virtual bool readPsrEvtIndicator(vesaPsrEventIndicator *psrErr) = 0;
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual bool getDpTunnelBwAllocationSupported() = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual bool isDpTunnelBwAllocationEnabled() = 0;
virtual bool getDpTunnelEstimatedBw(NvU8 &estimatedBw) = 0;
virtual bool getDpTunnelGranularityMultiplier(NvU8 &granularityMultiplier) = 0;
virtual TriState getDpTunnelBwRequestStatus() = 0;
@@ -540,6 +542,9 @@ namespace DisplayPort
virtual bool hasDpTunnelEstimatedBwChanged() = 0;
virtual bool hasDpTunnelBwAllocationCapabilityChanged() = 0;
virtual bool writeDpTunnelRequestedBw(NvU8 requestedBw) = 0;
virtual bool clearDpTunnelingBwRequestStatus() = 0;
virtual bool clearDpTunnelingEstimatedBwStatus() = 0;
virtual bool clearDpTunnelingBwAllocationCapStatus() = 0;
virtual ~DPCDHAL() {}
@@ -653,7 +658,7 @@ namespace DisplayPort
struct
{
bool bIsSupported;
bool bUsb4DriverSupport;
bool bUsb4DriverBwAllocationSupport;
bool bIsPanelReplayOptimizationSupported;
bool bIsBwAllocationSupported;
NvU8 maxLaneCount;
@@ -666,7 +671,9 @@ namespace DisplayPort
} caps;
bool bIsDpTunnelBwAllocationEnabled;
// This is set by connectorImpl depending on the request from client/regkey
bool bEnableDpTunnelBwAllocationSupport;
bool bIsDpTunnelBwAllocationEnabled; // This is set to true after we succeed in enabling BW allocation
struct
{
@@ -748,7 +755,7 @@ namespace DisplayPort
: bus(bus), timer(timer), bGrantsPostLtRequest(false), uprequestEnable(false),
upstreamIsSource(false), bMultistream(false), bGpuFECSupported(false),
bBypassILREdpRevCheck(false), overrideDpcdMaxLinkRate(0),
overrideDpcdRev(0), gpuDPSupportedVersions(0), bIsDpTunnelBwAllocationEnabled(false)
overrideDpcdRev(0), gpuDPSupportedVersions(0)
{
// start with default caps.
dpcdOffline = true;
@@ -760,7 +767,7 @@ namespace DisplayPort
caps.revisionMajor = 0x1;
caps.revisionMinor = 0x1;
caps.supportsESI = false;
caps.maxLinkRate = HBR3;
caps.maxLinkRate = dp2LinkRate_8_10Gbps;
caps.maxLaneCount = 4;
caps.enhancedFraming = true;
caps.downStreamPortPresent = true;
@@ -790,6 +797,7 @@ namespace DisplayPort
}
void updateDPCDOffline();
bool auxAccessAvailable();
void setPC2Disabled(bool disabled)
{
@@ -1402,19 +1410,28 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo);
bool getDpTunnelBwAllocationSupported()
{
return false;
}
virtual void configureDpTunnelBwAllocation();
virtual bool getDpTunnelGranularityMultiplier(NvU8 &granularityMultiplier);
virtual TriState getDpTunnelBwRequestStatus();
virtual bool setDpTunnelBwAllocation(bool bEnable);
virtual void enableDpTunnelingBwAllocationSupport()
{
bEnableDpTunnelBwAllocationSupport = true;
}
virtual bool isDpTunnelBwAllocationEnabled()
{
return bIsDpTunnelBwAllocationEnabled;
}
bool getDpTunnelEstimatedBw(NvU8 &estimatedBw);
bool hasDpTunnelEstimatedBwChanged();
bool hasDpTunnelBwAllocationCapabilityChanged();
bool writeDpTunnelRequestedBw(NvU8 requestedBw);
bool clearDpTunnelingBwRequestStatus();
bool clearDpTunnelingEstimatedBwStatus();
bool clearDpTunnelingBwAllocationCapStatus();
};

10
src/common/displayport/inc/dp_connector.h
View File

@@ -416,7 +416,7 @@ namespace DisplayPort
virtual LinkConfiguration getActiveLinkConfig() = 0;
// Get Current link configuration
virtual void getCurrentLinkConfig(unsigned & laneCount, NvU64 & linkRate) = 0;
virtual void getCurrentLinkConfig(unsigned &laneCount, NvU64 &linkRate) = 0;
// Get the clock calculation supported by the panel
virtual unsigned getPanelDataClockMultiplier() = 0;
@@ -669,9 +669,10 @@ namespace DisplayPort
// Compound queries and notify attaches(link train) would use the preferred link config unless it is reset again.
// (not advisable to leave a preferred link config always ON).
//
virtual bool setPreferredLinkConfig(LinkConfiguration & lc, bool commit,
virtual bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool force = false,
LinkTrainingType forceTrainType = NORMAL_LINK_TRAINING) = 0;
LinkTrainingType forceTrainType = NORMAL_LINK_TRAINING,
bool forcePreferredLinkConfig = false) = 0;
//
// Resets the preferred link config and lets the library go back to default LT policy.
@@ -702,7 +703,7 @@ namespace DisplayPort
virtual bool getHDCPAbortCodesDP12(NvU32 &hdcpAbortCodesDP12) = 0;
virtual bool getOuiSink(unsigned &ouiId, unsigned char * modelName,
size_t modelNameBufferSize, NvU8 & chipRevision) = 0;
size_t modelNameBufferSize, NvU8 &chipRevision) = 0;
virtual bool getIgnoreSourceOuiHandshake() = 0;
virtual void setIgnoreSourceOuiHandshake(bool bIgnore) = 0;
@@ -750,6 +751,7 @@ namespace DisplayPort
virtual bool readPrSinkDebugInfo(panelReplaySinkDebugInfo *prDbgInfo) = 0;
virtual void enableDpTunnelingBwAllocationSupport() = 0;
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo) = 0;
protected:
virtual ~Connector() {}

47
src/common/displayport/inc/dp_connectorimpl.h
View File

@@ -105,9 +105,9 @@ namespace DisplayPort
NvU8 cachedSourceChipRevision;
bool bOuiCached;
unsigned ouiId; // Sink ouiId
unsigned ouiId; // Sink ouiId
unsigned char modelName[NV_DPCD_SOURCE_DEV_ID_STRING__SIZE + 1]; // Device Model-name
bool bIgnoreSrcOuiHandshake; // Skip writing source OUI
bool bIgnoreSrcOuiHandshake; // Skip writing source OUI
LinkPolicy linkPolicy;
@@ -214,6 +214,7 @@ namespace DisplayPort
// this is the link config requested by a client.
// can be set and reset by the client for a given operation.
LinkConfiguration preferredLinkConfig;
bool forcePreferredLinkConfig;
//
// Desired link configuration of single head multiple sst secondary connector.
@@ -361,13 +362,9 @@ namespace DisplayPort
// the stale messages from previous discovery.
//
bool bForceClearPendingMsg;
bool bSkipFakeDeviceDpcdAccess;
NvU64 allocatedDpTunnelBw;
NvU64 allocatedDpTunnelBwShadow;
bool bForceDisableTunnelBwAllocation;
bool bClientRequestedDpTunnelBwAllocation;
bool bIsDpTunnelBwAllocationEnabled;
Group *perHeadAttachedGroup[NV_MAX_HEADS];
NvU32 inTransitionHeadMask;
@@ -379,16 +376,16 @@ namespace DisplayPort
void setPolicyAssessLinkSafely(bool enabled);
void discoveryDetectComplete();
void discoveryNewDevice(const DiscoveryManager::Device & device);
void discoveryLostDevice(const Address & address);
void processNewDevice(const DiscoveryManager::Device & device,
const Edid & edid,
void discoveryNewDevice(const DiscoveryManager::Device &device);
void discoveryLostDevice(const Address &address);
void processNewDevice(const DiscoveryManager::Device &device,
const Edid &edid,
bool isMultistream,
DwnStreamPortType portType,
DwnStreamPortAttribute portAttribute,
bool isCompliance = false);
void applyEdidWARs(Edid & edid, DiscoveryManager::Device device);
void applyEdidWARs(Edid &edid, DiscoveryManager::Device device);
void applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatabase);
ResStatusNotifyMessage ResStatus;
@@ -566,24 +563,19 @@ namespace DisplayPort
virtual void notifyAttachEnd(bool modesetCancelled);
virtual void notifyDetachBegin(Group * target);
virtual void notifyDetachEnd(bool bKeepOdAlive = false);
virtual bool willLinkSupportModeSST(const LinkConfiguration &linkConfig, const ModesetInfo &modesetInfo);
bool performIeeeOuiHandshake();
void setIgnoreSourceOuiHandshake(bool bIgnore);
bool getIgnoreSourceOuiHandshake();
bool willLinkSupportModeSST(const LinkConfiguration & linkConfig, const ModesetInfo & modesetInfo);
void forceLinkTraining();
bool updateDpTunnelBwAllocation();
void configureDpTunnelBwAllocation();
TriState requestDpTunnelBw(NvU8 requestedBw);
bool allocateDpTunnelBw(NvU64 bandwidth);
bool allocateMaxDpTunnelBw();
NvU64 getMaxTunnelBw();
void enableDpTunnelingBwAllocationSupport()
{
bClientRequestedDpTunnelBwAllocation = true;
}
void enableDpTunnelingBwAllocationSupport();
void assessLink(LinkTrainingType trainType = NORMAL_LINK_TRAINING);
@@ -606,7 +598,7 @@ namespace DisplayPort
}
bool trainLinkOptimized(LinkConfiguration lConfig);
bool trainLinkOptimizedSingleHeadMultipleSST(GroupImpl * group);
bool getValidLowestLinkConfig(LinkConfiguration & lConfig, LinkConfiguration & lowestSelected, ModesetInfo queryModesetInfo);
bool getValidLowestLinkConfig(LinkConfiguration &lConfig, LinkConfiguration &lowestSelected, ModesetInfo queryModesetInfo);
bool postLTAdjustment(const LinkConfiguration &, bool force);
void populateUpdatedLaneSettings(NvU8* voltageSwingLane, NvU8* preemphasisLane, NvU32 *data);
void populateDscCaps(DSC_INFO* dscInfo, DeviceImpl * dev, DSC_INFO::FORCED_DSC_PARAMS* forcedParams);
@@ -616,8 +608,8 @@ namespace DisplayPort
void populateDscBranchCaps(DSC_INFO* dscInfo, DeviceImpl * dev);
void populateDscModesetInfo(MODESET_INFO * pModesetInfo, const DpModesetParams * pModesetParams);
virtual bool train(const LinkConfiguration & lConfig, bool force, LinkTrainingType trainType = NORMAL_LINK_TRAINING);
virtual bool validateLinkConfiguration(const LinkConfiguration & lConfig);
virtual bool train(const LinkConfiguration &lConfig, bool force, LinkTrainingType trainType = NORMAL_LINK_TRAINING);
virtual bool validateLinkConfiguration(const LinkConfiguration &lConfig);
virtual bool assessPCONLinkCapability(PCONLinkControl *params);
bool trainPCONFrlLink(PCONLinkControl *pConControl);
@@ -626,7 +618,7 @@ namespace DisplayPort
bool setDeviceDscState(Device * dev, bool bEnableDsc);
// the lowest level function(nearest to the hal) for the connector.
bool rawTrain(const LinkConfiguration & lConfig, bool force, LinkTrainingType linkTrainingType);
bool rawTrain(const LinkConfiguration &lConfig, bool force, LinkTrainingType linkTrainingType);
virtual bool enableFlush();
virtual bool beforeAddStream(GroupImpl * group, bool force=false, bool forFlushMode = false);
@@ -645,7 +637,7 @@ namespace DisplayPort
void freeTimeslice(GroupImpl * targetGroup);
void flushTimeslotsToHardware();
bool getHDCPAbortCodesDP12(NvU32 &hdcpAbortCodesDP12);
bool getOuiSink(unsigned &ouiId, unsigned char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision);
bool getOuiSink(unsigned &ouiId, unsigned char * modelName, size_t modelNameBufferSize, NvU8 &chipRevision);
bool hdcpValidateKsv(const NvU8 *ksv, NvU32 Size);
void cancelHdcpCallbacks();
bool handleCPIRQ();
@@ -657,7 +649,7 @@ namespace DisplayPort
void configInit();
void handlePanelReplayError();
virtual DeviceImpl* findDeviceInList(const Address & address);
virtual DeviceImpl* findDeviceInList(const Address &address);
virtual void disconnectDeviceList();
void notifyLongPulseInternal(bool statusConnected);
virtual void notifyLongPulse(bool status);
@@ -673,7 +665,10 @@ namespace DisplayPort
virtual bool isFECSupported();
virtual bool isFECCapable();
virtual NvU32 maxLinkRateSupported();
virtual bool setPreferredLinkConfig(LinkConfiguration & lc, bool commit, bool force = false, LinkTrainingType trainType = NORMAL_LINK_TRAINING);
bool setPreferredLinkConfig(LinkConfiguration &lc, bool commit,
bool force = false,
LinkTrainingType trainType = NORMAL_LINK_TRAINING,
bool forcePreferredLinkConfig = false);
virtual bool resetPreferredLinkConfig(bool force = false);
virtual void setAllowMultiStreaming(bool bAllowMST);
virtual bool getAllowMultiStreaming(void);
@@ -693,7 +688,7 @@ namespace DisplayPort
bool setTestPattern(NV0073_CTRL_DP_TESTPATTERN testPattern, NvU8 laneMask, NV0073_CTRL_DP_CSTM cstm, NvBool bIsHBR2, NvBool bSkipLaneDataOverride = false);
bool getLaneConfig(NvU32 *numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
bool setLaneConfig(NvU32 numLanes, NvU32 *data); // "data" is an array of NV0073_CTRL_MAX_LANES unsigned ints
void getCurrentLinkConfig(unsigned & laneCount, NvU64 & linkRate); // CurrentLink Configuration
void getCurrentLinkConfig(unsigned &laneCount, NvU64 &linkRate); // CurrentLink Configuration
unsigned getPanelDataClockMultiplier();
unsigned getGpuDataClockMultiplier();
void configurePowerState(bool bPowerUp);

5
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -199,11 +199,10 @@ namespace DisplayPort
TriState bAsyncSDPCapable;
bool bMSAOverMSTCapable;
bool bDscPassThroughColorFormatWar;
bool bSkipFakeDeviceDpcdAccess;
DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent, bool bSkipFakeDeviceDpcdAccess);
NvU64 maxModeBwRequired;
DeviceImpl(DPCDHAL * hal, ConnectorImpl * connector, DeviceImpl * parent);
~DeviceImpl();
virtual bool isCableOk();

13
src/common/displayport/inc/dp_evoadapter.h
View File

@@ -51,7 +51,7 @@ namespace DisplayPort
{
public:
//
// IOCTL access to RM class DISPLAY_COMMON and NV50_DISPLAY
//
virtual NvU32 rmControl0073(NvU32 command, void * params, NvU32 paramSize) = 0;
virtual NvU32 rmControl5070(NvU32 command, void * params, NvU32 paramSize) = 0;
@@ -157,7 +157,6 @@ namespace DisplayPort
bool _useDfpMaxLinkRateCaps;
bool _applyLinkBwOverrideWarRegVal;
bool _isDynamicMuxCapable;
bool _isMDMEnabled;
bool _enableMSAOverrideOverMST;
bool _isLTPhyRepeaterSupported;
bool _isMSTPCONCapsReadDisabled;
@@ -236,10 +235,9 @@ namespace DisplayPort
if ((_applyLinkBwOverrideWarRegVal || _useDfpMaxLinkRateCaps) &&
(_maxLinkRateSupportedDfp < _maxLinkRateSupportedGpu))
{
return _maxLinkRateSupportedDfp;
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedDfp));
}
return _maxLinkRateSupportedGpu;
return (LINK_RATE_TO_DATA_RATE_8B_10B(_maxLinkRateSupportedGpu));
}
virtual bool isForceRmEdidRequired()
@@ -260,11 +258,6 @@ namespace DisplayPort
return (_isDynamicMuxCapable && _isEDP);
}
virtual bool isMDMEnabled()
{
return (_isMDMEnabled && _isEDP);
}
virtual bool isDownspreadSupported()
{
return _isDownspreadSupported;

179
src/common/displayport/inc/dp_linkconfig.h
View File

@@ -36,6 +36,7 @@
#include "ctrl/ctrl0073/ctrl0073specific.h" // NV0073_CTRL_HDCP_VPRIME_SIZE
#include "displayport.h"
#define NV_SUPPORTED_DP_LINK_RATES__SIZE NV_SUPPORTED_DP1X_LINK_RATES__SIZE
namespace DisplayPort
{
typedef NvU64 LinkRate;
@@ -44,58 +45,36 @@ namespace DisplayPort
{
public:
NvU8 entries;
// Store link rate in multipler of 10MBPS to save space
NvU16 element[NV_SUPPORTED_DP_LINK_RATES__SIZE];
virtual void clear() = 0;
virtual bool import(NvU8 linkBw)
{
DP_ASSERT(0);
return false;
}
virtual LinkRate getLowerRate(LinkRate rate) = 0;
virtual LinkRate getMaxRate() = 0;
virtual NvU8 getNumElements() = 0;
NvU8 getNumLinkRates()
{
return entries;
}
};
class LinkRates1x : virtual public LinkRates
{
public:
// Store link rate in multipler of 270MBPS to save space
NvU8 element[NV_SUPPORTED_DP1X_LINK_RATES__SIZE];
LinkRates1x()
LinkRates()
{
entries = 0;
for (int i = 0; i < NV_SUPPORTED_DP1X_LINK_RATES__SIZE; i++)
for (int i = 0; i < NV_SUPPORTED_DP_LINK_RATES__SIZE; i++)
{
element[i] = 0;
}
}
virtual void clear()
void clear()
{
entries = 0;
for (int i = 0; i < NV_SUPPORTED_DP1X_LINK_RATES__SIZE; i++)
for (int i = 0; i < NV_SUPPORTED_DP_LINK_RATES__SIZE; i++)
{
element[i] = 0;
}
}
virtual bool import(NvU8 linkBw)
bool import(NvU16 linkBw)
{
if (!IS_VALID_LINKBW(linkBw))
if (!IS_VALID_LINKBW_10M(linkBw))
{
DP_ASSERT(0 && "Unsupported Link Bandwidth");
return false;
}
if (entries < NV_SUPPORTED_DP1X_LINK_RATES__SIZE)
if (entries < NV_SUPPORTED_DP_LINK_RATES__SIZE)
{
element[entries] = linkBw;
entries++;
@@ -105,47 +84,49 @@ namespace DisplayPort
return false;
}
virtual LinkRate getLowerRate(LinkRate rate)
LinkRate getLowerRate(LinkRate rate)
{
int i;
NvU8 linkBw = (NvU8)(rate / DP_LINK_BW_FREQ_MULTI_MBPS);
if ((entries == 0) || (linkBw <= element[0]))
if ((entries == 0) || (rate <= element[0]))
return 0;
for (i = entries - 1; i > 0; i--)
{
if (linkBw > element[i])
if (rate > element[i])
break;
}
rate = (LinkRate)element[i] * DP_LINK_BW_FREQ_MULTI_MBPS;
return rate;
return ((LinkRate)element[i]);
}
virtual LinkRate getMaxRate()
LinkRate getMaxRate()
{
LinkRate rate = 0;
if ((entries > 0) &&
(entries <= NV_SUPPORTED_DP1X_LINK_RATES__SIZE))
(entries <= NV_SUPPORTED_DP_LINK_RATES__SIZE))
{
rate = (LinkRate)element[entries - 1] * DP_LINK_BW_FREQ_MULTI_MBPS;
rate = (LinkRate)element[entries - 1];
}
return rate;
}
virtual NvU8 getNumElements()
NvU8 getNumElements()
{
return NV_SUPPORTED_DP1X_LINK_RATES__SIZE;
return NV_SUPPORTED_DP_LINK_RATES__SIZE;
}
NvU8 getNumLinkRates()
{
return entries;
}
};
class LinkPolicy : virtual public Object
{
protected:
bool bNoFallback; // No fallback when LT fails
LinkRates1x linkRates;
LinkRates linkRates;
public:
LinkPolicy() : bNoFallback(false)
{
@@ -281,8 +262,40 @@ namespace DisplayPort
return linkTrainCounter;
}
// Returns data rate in Bytes per second
NvU64 convertLinkRateToDataRate(LinkRate linkRate) const
{
NvU64 dataRate;
dataRate = LINK_RATE_TO_DATA_RATE_8B_10B(linkRate);
return dataRate;
}
// Returns minRate in data rate in Bytes per second
NvU64 convertMinRateToDataRate() const
{
NvU64 dataRate;
dataRate = DP_LINK_RATE_BITSPS_TO_BYTESPS(OVERHEAD_8B_10B(minRate));
return dataRate;
}
NvU64 getTotalDataRate() const
{
return (convertLinkRateToDataRate(peakRate) * lanes);
}
NvU64 linkOverhead(NvU64 rate)
{
if(IS_VALID_LINKBW_10M(rate))
{
// Converting here so that minRate from 10M is converted to bps
rate = DP_LINK_RATE_10M_TO_BPS(rate);
}
else
{
// Convert from data rate to bps
rate = DATA_RATE_8B_10B_TO_LINK_RATE_BPS(rate);
}
if(bEnableFEC)
{
@@ -356,74 +369,89 @@ namespace DisplayPort
if (TotalLinkPBN <= 90)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
peakRatePossible = dp2LinkRate_1_62Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_1_62Gbps);
lanes = 0; // FAIL
}
if (TotalLinkPBN <= 192)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
peakRatePossible = dp2LinkRate_1_62Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_1_62Gbps);
lanes = 1;
}
else if (TotalLinkPBN <= 320)
{
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
peakRatePossible = dp2LinkRate_2_70Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_2_70Gbps);
lanes = 1;
}
else if (TotalLinkPBN <= 384)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
peakRatePossible = dp2LinkRate_1_62Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_1_62Gbps);
lanes = 2;
}
else if (TotalLinkPBN <= 640)
{
// could be HBR2 x 1, but TotalLinkPBN works out same
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
peakRatePossible = dp2LinkRate_2_70Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_2_70Gbps);
lanes = 2;
}
else if (TotalLinkPBN <= 768)
{
peakRatePossible = peakRate = RBR;
minRate = linkOverhead(RBR);
peakRatePossible = dp2LinkRate_1_62Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_1_62Gbps);
lanes = 4;
}
else if (TotalLinkPBN <= 960)
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
peakRatePossible = dp2LinkRate_8_10Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_8_10Gbps);
lanes = 1;
}
else if (TotalLinkPBN <= 1280)
{
// could be HBR2 x 2
peakRatePossible = peakRate = HBR;
minRate = linkOverhead(HBR);
peakRatePossible = dp2LinkRate_2_70Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_2_70Gbps);
lanes = 4;
}
else if (TotalLinkPBN <= 1920)
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
peakRatePossible = dp2LinkRate_8_10Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_8_10Gbps);
lanes = 2;
}
else if (TotalLinkPBN <= 2560)
{
peakRatePossible = peakRate = HBR2;
minRate = linkOverhead(HBR2);
peakRatePossible = dp2LinkRate_5_40Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_5_40Gbps);
lanes = 4;
}
else if (TotalLinkPBN <= 3840)
{
peakRatePossible = peakRate = HBR3;
minRate = linkOverhead(HBR3);
peakRatePossible = dp2LinkRate_8_10Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_8_10Gbps);
lanes = 4;
}
else {
peakRatePossible = peakRate = RBR, minRate = linkOverhead(RBR), lanes = 0; // FAIL
else
{
peakRatePossible = dp2LinkRate_1_62Gbps;
peakRate = peakRatePossible;
minRate = linkOverhead(dp2LinkRate_1_62Gbps);
lanes = 0; // FAIL
DP_ASSERT(0 && "Unknown configuration");
}
}
@@ -512,7 +540,7 @@ namespace DisplayPort
NvU32 slotsForPBN(NvU32 allocatedPBN, bool usable = false)
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = peakRate * lanes / 64;
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
if (bytes_per_timeslot == 0)
return (NvU32)-1;
@@ -532,7 +560,7 @@ namespace DisplayPort
NvU32 PBNForSlots(NvU32 slots) // Rounded down
{
NvU64 bytes_per_pbn = 54 * 1000000 / 64; // this comes out exact
NvU64 bytes_per_timeslot = peakRate * lanes / 64;
NvU64 bytes_per_timeslot = getTotalDataRate() / 64;
return (NvU32)(bytes_per_timeslot * slots/ bytes_per_pbn);
}
@@ -553,8 +581,8 @@ namespace DisplayPort
bool operator< (const LinkConfiguration & right) const
{
NvU64 leftMKBps = peakRate * lanes;
NvU64 rightMKBps = right.peakRate * right.lanes;
NvU64 leftMKBps = getTotalDataRate();
NvU64 rightMKBps = right.getTotalDataRate();
if (leftMKBps == rightMKBps)
{
@@ -567,10 +595,5 @@ namespace DisplayPort
}
};
#define IS_DP2X_UHBR_LINK_DATA_RATE(val) (((NvU32)(val) == UHBR_2_50GHZ) || \
((NvU32)(val) == UHBR_2_70GHZ) || \
((NvU32)(val) == UHBR_10_0GHZ) || \
((NvU32)(val) == UHBR_13_5GHZ) || \
((NvU32)(val) == UHBR_20_0GHZ))
}
#endif //INCLUDED_DP_LINKCONFIG_H

3
src/common/displayport/inc/dp_mainlink.h
View File

@@ -141,9 +141,6 @@ namespace DisplayPort
// Return if Internal panel is Dynamic Mux capable
virtual bool isInternalPanelDynamicMuxCapable() = 0;
// Return if MDM is enabled on internal panel
virtual bool isMDMEnabled() = 0;
// Check if we should skip power down eDP when head detached.
virtual bool skipPowerdownEdpPanelWhenHeadDetach() = 0;

8
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -43,6 +43,7 @@
#define NV_DP_REGKEY_ENABLE_OCA_LOGGING "ENABLE_OCA_LOGGING"
#define NV_DP_REGKEY_REPORT_DEVICE_LOST_BEFORE_NEW "HP_WAR_1707690"
#define NV_DP_REGKEY_APPLY_LINK_BW_OVERRIDE_WAR "APPLY_LINK_BW_OVERRIDE_WAR"
// For DP2x, the regkey value needs to be in 10M convention
#define NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES "APPLY_OVERRIDES_FOR_BUG_2489143"
#define NV_DP_REGKEY_DISABLE_DSC "DISABLE_DSC"
#define NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP "HP_WAR_2189772"
@@ -80,9 +81,6 @@
// Bug 4426624: Flush timeslot change to HW when dirty bit is set.
#define NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY "DP_BUG_4426624_WAR"
// Bug 4459839 : This regkey will enable DSC irrespective of LT status.
#define NV_DP_REGKEY_FORCE_DSC_ON_SINK "DP_FORCE_DSC_ON_SINK"
#define NV_DP_REGKEY_ENABLE_SKIP_DPCD_READS_WAR "DP_BUG_4478047_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
//
@@ -118,8 +116,6 @@ struct DP_REGKEY_DATABASE
bool bPowerDownPhyBeforeD3;
bool bReassessMaxLink;
bool bMSTPCONCapsReadDisabled;
bool bForceDscOnSink;
bool bSkipFakeDeviceDpcdAccess;
bool bFlushTimeslotWhenDirty;
bool bForceDisableTunnelBwAllocation;
};