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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-02 03:39:50 +00:00
560.28.03
This commit is contained in:
Gaurav Juvekar
@@ -48,6 +48,20 @@
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#define DP2HDMI_DONGLE_DDC_BUFFER_ID_LEN 16
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#define DP2HDMI_DONGLE_CAP_BUFFER_LEN 32
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// For 8b/10b link rate to data rate, linkRate * 8/10 * 1/8 * 10M -> (linkRate * 1000000)
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// For 8b/10b data rate to link rate, dataRate * 10/8 * 8 * 1/10M -> (dataRate / 1000000)
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#define LINK_RATE_TO_DATA_RATE_8B_10B(linkRate) (linkRate * 1000000UL)
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#define DATA_RATE_8B_10B_TO_LINK_RATE(dataRate) (dataRate / 1000000UL)
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// To calculate the effective link rate with channel encoding accounted
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#define OVERHEAD_8B_10B(linkRate) ((linkRate * 8) * 1/10)
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// Convert data rate to link rate in bps
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#define DATA_RATE_8B_10B_TO_LINK_RATE_BPS(dataRate) (dataRate * 10)
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// Convert data rate to link rate in bps
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#define LINK_RATE_BPS_TO_DATA_RATE_8B_10B(linkRate) (linkRate / 10)
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// Offset to read the dongle identifier
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#define NV_DP2HDMI_DONGLE_IDENTIFIER (0x00000010)
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#define NV_DP2HDMI_DONGLE_IDENTIFIER_ADAPTER_REV 2:0
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@@ -115,6 +129,20 @@ typedef enum
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linkBW_8_10Gbps = 0x1E,
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linkBW_Supported
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} DP_LINK_BANDWIDTH;
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typedef enum
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{
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// enum value unit = 10M
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dp2LinkRate_1_62Gbps = 0x00A2, // 162
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dp2LinkRate_2_16Gbps = 0x00D8, // 216
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dp2LinkRate_2_43Gbps = 0x00F3, // 243
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dp2LinkRate_2_50Gbps = 0x00FA, // 250
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dp2LinkRate_2_70Gbps = 0x010E, // 270
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dp2LinkRate_3_24Gbps = 0x0144, // 324
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dp2LinkRate_4_32Gbps = 0x01B0, // 432
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dp2LinkRate_5_40Gbps = 0x021C, // 540
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dp2LinkRate_8_10Gbps = 0x032A, // 810
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dp2LinkRate_Supported
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} DP2X_LINKRATE_10M;
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typedef enum
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{
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@@ -528,6 +556,17 @@ typedef struct
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// Multiplier constant to get link rate table's in KHZ
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#define DP_LINK_RATE_TABLE_MULTIPLIER_KHZ 200
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// Macro to convert link rate table to 10M convention
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#define LINK_RATE_200KHZ_TO_10MHZ(linkRate) (linkRate / 50)
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//
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// Get link rate in multiplier of 10MHz from KHz:
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// a * 1000(KHz) / 10 * 1000 * 1000(10Mhz)
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//
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#define LINK_RATE_KHZ_TO_10MHZ(a) ((a) / 10000)
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#define LINK_RATE_270MHZ_TO_10MHZ(a) ((a) * 27)
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#define LINK_RATE_10MHZ_TO_270MHZ(a) ((a) / 27)
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//
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// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
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// a * 270 * 1000 * 1000(270Mhz) * (8 / 10)(8b/10b) / 8(Byte)
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@@ -535,6 +574,12 @@ typedef struct
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//
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#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
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// Convert link rate in 10M to its value in bps
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#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
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// Convert link rate from bps to Bps
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#define DP_LINK_RATE_BITSPS_TO_BYTESPS(linkRate) (linkRate / 8)
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//
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// Get link rate in multiplier of 270MHz from KHz:
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// a * 1000(KHz) / 270 * 1000 * 1000(270Mhz)
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@@ -604,6 +649,9 @@ typedef struct
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#define IS_VALID_LINKBW(val) (IS_STANDARD_LINKBW(val) || \
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IS_INTERMEDIATE_LINKBW(val))
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#define IS_VALID_LINKBW_10M(val) IS_VALID_LINKBW(LINK_RATE_10MHZ_TO_270MHZ(val))
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#define IS_INTERMEDIATE_LINKBW_10M(val) IS_INTERMEDIATE_LINKBW(LINK_RATE_10MHZ_TO_270MHZ(val))
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#define IS_STANDARD_LINKBW_10M(val) IS_STANDARD_LINKBW(LINK_RATE_10MHZ_TO_270MHZ(val))
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//
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// Phy Repeater count read from DPCD offset F0002h is an
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// 8 bit value where each bit represents the total count
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@@ -447,9 +447,6 @@ number of Downstream ports will be limited to 32.
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
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#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
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#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE 6:6 /* RWXUF */
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#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_NO (0x00000000) /* RWXUV */
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#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_YES (0x00000001) /* RWXUV */
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#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
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#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
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#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
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@@ -732,28 +729,13 @@ number of Downstream ports will be limited to 32.
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#define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN 3:3 /* R-XUF */
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#define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN_NO (0x00000000) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_TEST_PHY_TEST_PATTERN_YES (0x00000001) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING 5:4 /* R-XUF */
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#define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_8B10B (0x00000000) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_128B132B (0x00000001) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ 6:6 /* R-XUF */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_NO (0x00000000) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_YES (0x00000001) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO 7:7 /* R-XUF */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_NO (0x00000000) /* R-XUV */
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#define NV_DPCD_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_YES (0x00000001) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE (0x00000219) /* R-XUR */
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#define NV_DPCD_TEST_LINK_RATE_TYPE 7:0 /* R-XUF */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_1_62G (0x00000006) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_2_70G (0x0000000A) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_5_40G (0x00000014) /* R-XUV */
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//
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// For PHY Test 128b/132b channel coding (PHY_TEST_CHANNEL_CODING field in
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// the TEST_REQUEST register (DPCD Address 00218h, bits 5:4) is programmed to 01b)
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//
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#define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR10 (0x00000001) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR20 (0x00000002) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_UHBR135 (0x00000004) /* R-XUV */
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#define NV_DPCD_TEST_LINK_RATE_TYPE_8_10G (0x0000001E) /* R-XUV */
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// 0021Ah - 0021Fh: RESERVED. Read all 0s
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@@ -187,5 +187,4 @@
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#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_NO (0x00000000) /* R-XUV */
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#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_YES (0x00000001) /* R-XUV */
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#endif // #ifndef _DISPLAYPORT20_H_
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