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This commit is contained in:
Gaurav Juvekar
2024-07-19 15:45:15 -07:00
parent 5fdf5032fb
commit 448d5cc656
859 changed files with 165424 additions and 91129 deletions
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29
src/common/inc/swref/published/blackwell/gb100/dev_access_counter.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_access_counter_h__
#define __gb100_dev_access_counter_h__
#define NV_ACCESS_COUNTER_NOTIFY_BUF_SIZE 32 /* */
#endif // __gb100_dev_access_counter_h__

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src/common/inc/swref/published/blackwell/gb100/dev_boot.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_boot_h
#define gb100_dev_boot_h
#define NV_PMC_SCRATCH_RESET_2(i) (0x00000580+(i)*4) /* RW-4A */
#define NV_PMC_SCRATCH_RESET_2__SIZE_1 16 /* */
#define NV_PMC_SCRATCH_RESET_2_VALUE 31:0 /* RWBVF */
#define NV_PMC_SCRATCH_RESET_2_VALUE_INIT 0 /* RWB-V */
#endif // gb100_dev_boot_h

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src/common/inc/swref/published/blackwell/gb100/dev_boot_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_boot_addendum_h
#define gb100_dev_boot_addendum_h
#define NV_PMC_SCRATCH_RESET_2_CC NV_PMC_SCRATCH_RESET_2(4)
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED 0:0
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_MODE_ENABLED_FALSE 0x0
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED 1:1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_TRUE 0x1
#define NV_PMC_SCRATCH_RESET_2_CC_DEV_ENABLED_FALSE 0x0
#endif // gb100_dev_boot_addendum_h

40
src/common/inc/swref/published/blackwell/gb100/dev_bus.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_bus_h__
#define __gb100_dev_bus_h__
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#define NV_PBUS0_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS0_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS0_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS0_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#define NV_PBUS1_SW_SCRATCH(i) (0x00031400+(i)*4) /* RW-4A */
#define NV_PBUS1_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS1_SW_SCRATCH_FIELD 31:0 /* RWBVF */
#define NV_PBUS1_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWB-V */
#endif // __gb100_dev_bus_h__

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src/common/inc/swref/published/blackwell/gb100/dev_bus_addendum.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_nv_bus_addendum_h
#define gb100_dev_nv_bus_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_SW_SCRATCH(0x3D)
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_SW_SCRATCH(0x3E)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG NV_PBUS_SW_SCRATCH(0x3F)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gb100_dev_nv_bus_addendum_h

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src/common/inc/swref/published/blackwell/gb100/dev_ce_base.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_ce_base_h__
#define __gb100_dev_ce_base_h__
#define NV_CE_PCE2LCE_CONFIG__SIZE_1 24
#define NV_CE_GRCE_CONFIG__SIZE_1 2
#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
#endif // __gb100_dev_ce_base_h__

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src/common/inc/swref/published/blackwell/gb100/dev_ctxsw_prog.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_ctxsw_prog_h__
#define __gb100_dev_ctxsw_prog_h__
#define NV_CTXSW_TIMESTAMP_BUFFER_RD_WR_POINTER 30:0 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE 31:31 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_ENABLED 0x1 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_DISABLED 0x0 /* */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_PREEMPT_OFFSET 0x00000000 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SPILL_OFFSET 0x00000004 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_CB_OFFSET 0x00000008 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_PAGEPOOL_OFFSET 0x0000000c /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_STRIDE 0x00000010 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_BETA_SIZE 0x00000014 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_ALPHA_SIZE 0x00000018 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GLOBAL_PAGEPOOL_SIZE 0x0000001c /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_BETA_SIZE 0x00000020 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_ALPHA_SIZE 0x00000024 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_PAGEPOOL_SIZE 0x00000028 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_GFXP_SPILL_SIZE 0x0000002c /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_NUM_SLICES 0x00000030 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY1 0x00000034 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY2 0x00000038 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY3 0x0000003c /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_SLICE_ARRAY4 0x00000040 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY1 0x00000044 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY2 0x00000048 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY3 0x0000004c /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_RM_SLICE_ARRAY4 0x00000050 /* RW-4R */
#define NV_CTXSW_GFXP_POOL_CTRL_BLK_MAX_SLICES 0x00000054 /* RW-4R */
#endif // __gb100_dev_ctxsw_prog_h__

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src/common/inc/swref/published/blackwell/gb100/dev_fault.h Normal file
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/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_fault_h__
#define __gb100_dev_fault_h__
#define NV_PFAULT /* ----G */
#define NV_PFAULT_MMU_ENG_ID_GRAPHICS 384 /* */
#define NV_PFAULT_MMU_ENG_ID_DISPLAY 1 /* */
#define NV_PFAULT_MMU_ENG_ID_GSP 2 /* */
#define NV_PFAULT_MMU_ENG_ID_IFB 55 /* */
#define NV_PFAULT_MMU_ENG_ID_FLA 4 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2 320 /* */
#define NV_PFAULT_MMU_ENG_ID_SEC 6 /* */
#define NV_PFAULT_MMU_ENG_ID_FSP 7 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF0 10 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF1 11 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF2 12 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF3 13 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF4 14 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF5 15 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF6 16 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF7 17 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF8 18 /* */
#define NV_PFAULT_MMU_ENG_ID_PERF9 19 /* */
#define NV_PFAULT_MMU_ENG_ID_GSPLITE 20 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC0 28 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC1 29 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC2 30 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC3 31 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC4 32 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC5 33 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC6 34 /* */
#define NV_PFAULT_MMU_ENG_ID_NVDEC7 35 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG0 36 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG1 37 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG2 38 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG3 39 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG4 40 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG5 41 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG6 42 /* */
#define NV_PFAULT_MMU_ENG_ID_NVJPG7 43 /* */
#define NV_PFAULT_MMU_ENG_ID_GRCOPY 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE0 65 /* */
#define NV_PFAULT_MMU_ENG_ID_CE1 66 /* */
#define NV_PFAULT_MMU_ENG_ID_CE2 67 /* */
#define NV_PFAULT_MMU_ENG_ID_CE3 68 /* */
#define NV_PFAULT_MMU_ENG_ID_CE4 69 /* */
#define NV_PFAULT_MMU_ENG_ID_CE5 70 /* */
#define NV_PFAULT_MMU_ENG_ID_CE6 71 /* */
#define NV_PFAULT_MMU_ENG_ID_CE7 72 /* */
#define NV_PFAULT_MMU_ENG_ID_CE8 73 /* */
#define NV_PFAULT_MMU_ENG_ID_CE9 74 /* */
#define NV_PFAULT_MMU_ENG_ID_CE10 75 /* */
#define NV_PFAULT_MMU_ENG_ID_CE11 76 /* */
#define NV_PFAULT_MMU_ENG_ID_CE12 77 /* */
#define NV_PFAULT_MMU_ENG_ID_CE13 78 /* */
#define NV_PFAULT_MMU_ENG_ID_CE14 79 /* */
#define NV_PFAULT_MMU_ENG_ID_CE15 80 /* */
#define NV_PFAULT_MMU_ENG_ID_CE16 81 /* */
#define NV_PFAULT_MMU_ENG_ID_CE17 82 /* */
#define NV_PFAULT_MMU_ENG_ID_CE18 83 /* */
#define NV_PFAULT_MMU_ENG_ID_CE19 84 /* */
#define NV_PFAULT_MMU_ENG_ID_PWR_PMU 5 /* */
#define NV_PFAULT_MMU_ENG_ID_PTP 3 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC0 44 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC1 45 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC2 46 /* */
#define NV_PFAULT_MMU_ENG_ID_NVENC3 47 /* */
#define NV_PFAULT_MMU_ENG_ID_OFA0 48 /* */
#define NV_PFAULT_MMU_ENG_ID_PHYSICAL 56 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST0 85 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST1 86 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST2 87 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST3 88 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST4 89 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST5 90 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST6 91 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST7 92 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST8 93 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST9 94 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST10 95 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST11 96 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST12 97 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST13 98 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST14 99 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST15 100 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST16 101 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST17 102 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST18 103 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST19 104 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST20 105 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST21 106 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST22 107 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST23 108 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST24 109 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST25 110 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST26 111 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST27 112 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST28 113 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST29 114 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST30 115 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST31 116 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST32 117 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST33 118 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST34 119 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST35 120 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST36 121 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST37 122 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST38 123 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST39 124 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST40 125 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST41 126 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST42 127 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST43 128 /* */
#define NV_PFAULT_MMU_ENG_ID_HOST44 129 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN0 256 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN1 257 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN2 258 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN3 259 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN4 260 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN5 261 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN6 262 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN7 263 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN8 264 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN9 265 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN10 266 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN11 267 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN12 268 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN13 269 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN14 270 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN15 271 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN16 272 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN17 273 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN18 274 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN19 275 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN20 276 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN21 277 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN22 278 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN23 279 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN24 280 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN25 281 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN26 282 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN27 283 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN28 284 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN29 285 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN30 286 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN31 287 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN32 288 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN33 289 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN34 290 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN35 291 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN36 292 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN37 293 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN38 294 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN39 295 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN40 296 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN41 297 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN42 298 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN43 299 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN44 300 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN45 301 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN46 302 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN47 303 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN48 304 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN49 305 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN50 306 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN51 307 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN52 308 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN53 309 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN54 310 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN55 311 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN56 312 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN57 313 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN58 314 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN59 315 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN60 316 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN61 317 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN62 318 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR1_FN63 319 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN0 320 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN1 321 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN2 322 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN3 323 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN4 324 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN5 325 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN6 326 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN7 327 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN8 328 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN9 329 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN10 330 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN11 331 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN12 332 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN13 333 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN14 334 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN15 335 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN16 336 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN17 337 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN18 338 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN19 339 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN20 340 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN21 341 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN22 342 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN23 343 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN24 344 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN25 345 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN26 346 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN27 347 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN28 348 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN29 349 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN30 350 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN31 351 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN32 352 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN33 353 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN34 354 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN35 355 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN36 356 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN37 357 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN38 358 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN39 359 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN40 360 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN41 361 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN42 362 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN43 363 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN44 364 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN45 365 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN46 366 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN47 367 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN48 368 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN49 369 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN50 370 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN51 371 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN52 372 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN53 373 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN54 374 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN55 375 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN56 376 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN57 377 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN58 378 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN59 379 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN60 380 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN61 381 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN62 382 /* */
#define NV_PFAULT_MMU_ENG_ID_BAR2_FN63 383 /* */
#define NV_PFAULT_FAULT_TYPE_PDE 0x00000000 /* */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE 0x00000001 /* */
#define NV_PFAULT_FAULT_TYPE_PTE 0x00000002 /* */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION 0x00000003 /* */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK 0x00000004 /* */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION 0x00000005 /* */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION 0x00000006 /* */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION 0x00000007 /* */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /* */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION 0x00000009 /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /* */
#define NV_PFAULT_FAULT_TYPE_CC_VIOLATION 0x0000000b /* */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND 0x0000000c /* */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION 0x0000000d /* */
#define NV_PFAULT_FAULT_TYPE_POISONED 0x0000000e /* */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION 0x0000000f /* */
#define NV_PFAULT_CLIENT_GPC_ROP_0 0x00000070 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_1 0x00000071 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_2 0x00000072 /* */
#define NV_PFAULT_CLIENT_GPC_ROP_3 0x00000073 /* */
#define NV_PFAULT_CLIENT_HUB_ESC 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC0 0x00000063 /* */
#define NV_PFAULT_CLIENT_HUB_ESC1 0x00000064 /* */
#define NV_PFAULT_CLIENT_HUB_ESC2 0x00000065 /* */
#define NV_PFAULT_CLIENT_HUB_ESC3 0x00000066 /* */
#define NV_PFAULT_CLIENT_HUB_ESC4 0x00000067 /* */
#define NV_PFAULT_CLIENT_HUB_ESC5 0x00000068 /* */
#define NV_PFAULT_CLIENT_HUB_ESC6 0x00000069 /* */
#define NV_PFAULT_CLIENT_HUB_ESC7 0x0000006a /* */
#define NV_PFAULT_CLIENT_HUB_ESC8 0x0000006b /* */
#define NV_PFAULT_CLIENT_HUB_ESC9 0x0000006c /* */
#define NV_PFAULT_CLIENT_HUB_ESC10 0x0000006d /* */
#define NV_PFAULT_CLIENT_HUB_ESC11 0x0000006e /* */
#define NV_PFAULT_ACCESS_TYPE_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ 0x00000000 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ 0x00000008 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC 0x00000000 /* */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB 0x00000001 /* */
#endif // __gb100_dev_fault_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_fsp_addendum_h__
#define __gb100_dev_fsp_addendum_h__
#define NV_GFW_FSP_UCODE_VERSION NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(1)
#define NV_GFW_FSP_UCODE_VERSION_FULL 11:0
#define NV_GFW_FSP_UCODE_VERSION_MAJOR 11:8
#define NV_GFW_FSP_UCODE_VERSION_MINOR 7:0
#define NV_PFSP_FUSE_ERROR_CHECK NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(3)
#define NV_PFSP_FUSE_ERROR_CHECK_STATUS 31:0
#define NV_PFSP_FUSE_ERROR_CHECK_STATUS_SUCCESS 0x00000000
#endif // __gb100_dev_fsp_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_fsp_pri_h__
#define __gb100_dev_fsp_pri_h__
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x008f0320+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x008f0330+(i)*4) /* RW-4A */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
#define NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
#endif // __gb100_dev_fsp_pri_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_gsp_h__
#define __gb100_dev_gsp_h__
#define NV_PGSP_FALCON_MAILBOX0 0x110040 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_FALCON_MAILBOX1 0x110044 /* RW-4R */
#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
#define NV_PGSP_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWEVF */
#define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT 0 /* */
#define NV_PGSP_FALCON_ENGINE_RESET_ASSERT 1 /* */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS 10:8 /* R-EVF */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_ASSERTED 0x00000000 /* R-E-V */
#define NV_PGSP_FALCON_ENGINE_RESET_STATUS_DEASSERTED 0x00000002 /* R---V */
#define NV_PGSP_MAILBOX(i) (0x110804+(i)*4) /* RW-4A */
#define NV_PGSP_EMEMC(i) (0x110ac0+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMC__SIZE_1 8 /* */
#define NV_PGSP_EMEMC_OFFS 7:2 /* RWIVF */
#define NV_PGSP_EMEMC_OFFS_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_BLK 15:8 /* RWIVF */
#define NV_PGSP_EMEMC_BLK_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW 24:24 /* RWIVF */
#define NV_PGSP_EMEMC_AINCW_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCW_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCW_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMC_AINCR 25:25 /* RWIVF */
#define NV_PGSP_EMEMC_AINCR_INIT 0x00000000 /* RWI-V */
#define NV_PGSP_EMEMC_AINCR_TRUE 0x00000001 /* RW--V */
#define NV_PGSP_EMEMC_AINCR_FALSE 0x00000000 /* RW--V */
#define NV_PGSP_EMEMD(i) (0x110ac4+(i)*8) /* RW-4A */
#define NV_PGSP_EMEMD__SIZE_1 8 /* */
#define NV_PGSP_EMEMD_DATA 31:0 /* RWXVF */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK 0x1103c4 /* RW-4R */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
#define NV_PGSP_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
#endif // __gb100_dev_gsp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_hshub_base_h__
#define __gb100_dev_hshub_base_h__
#define NV_PFB_HSHUB 0x00000FFF:0x00000000 /* RW--D */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO 0x00000E50 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI 0x00000E54 /* RW-4R */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO 0x000006C0 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO_ADR_MASK 0xFFFFFF00 /* ----V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI 0x000006C4 /* RW-4R */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR 31:0 /* RWIVF */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_INIT 0x00000000 /* RWI-V */
#define NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI_ADR_MASK 0x000FFFFF /* ----V */
#endif // __gb100_dev_hshub_base_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_pcfg_pf0_h__
#define __gb100_dev_pcfg_pf0_h__
#define NV_PF0_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS 12:12 /* RWCVF */
#define NV_PF0_STATUS_COMMAND_IO_SPACE_ENABLE 0:0 /* RWIVF */
#define NV_PF0_SUBSYSTEM_ID_AND_VENDOR_ID 0x0000002c /* R--4R */
#define NV_PF0_LINK_CONTROL_AND_STATUS 0x00000050 /* RW-4R */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_BASE_CLASS_CODE_3D 0 /* */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS 20:20 /* RWCVF */
#define NV_PF0_BASE_ADDRESS_REGISTERS_5 0x00000024 /* RW-4R */
#define NV_PF0_VF_BAR_0 0x00000324 /* RW-4R */
#define NV_PF0_LINK_CAPABILITIES 0x0000004c /* R--4R */
#define NV_PF0_BASE_ADDRESS_REGISTERS_0 0x00000010 /* RW-4R */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS 0x00000048 /* RW-4R */
#define NV_PF0_BASE_ADDRESS_REGISTERS_0_ADDR_TYPE 2:1 /* R-IVF */
#define NV_PF0_MSIX_CAPABILITY_HEADR_AND_CONTROL 0x0000007c /* RW-4R */
#define NV_PF0_DEVICE_CONTROL_2_ATOMICOP_REQUESTER_ENABLE 6:6 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_CORRECTABLE_ERROR_DETECTED 16:16 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_UNSUPPORTED_REQUEST_DETECTED 19:19 /* RWIVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_RECEIVED 12:12 /* RWCVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_MNOC_INTERFACE_AVAILABLE 19:19 /* R-IVF */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS 7:7 /* RWCVF */
#define NV_PF0_DEVICE_VENDOR_ID 0x00000000 /* R--4R */
#define NV_PF0_DEVICE_CAPABILITIES 0x00000044 /* R--4R */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE 0x00000008 /* R--4R */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS 16:16 /* RWCVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL 0x00000af8 /* R--4R */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_NON_FATAL_ERROR_DETECTED 17:17 /* RWIVF */
#define NV_PF0_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED 5:5 /* R-IVF */
#define NV_PF0_L1_PM_SUBSTATES_CONTROL_1 0x00000348 /* RW-4R */
#define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE_ENABLE 1 /* */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_MNOC_INTERFACE_AVAILABLE_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_INITIAL_AND_TOTAL_VFS 0x0000030c /* R--4R */
#define NV_PF0_VF_STRIDE_AND_OFFSET 0x00000314 /* R--4R */
#define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE_DISABLE 0 /* */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_NO_SNOOP 11:11 /* RWIVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS 14:14 /* RWCVF */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_BASE_CLASS_CODE 31:24 /* R-IVF */
#define NV_PF0_PF_RESIZABLE_BAR_CONTROL_BAR_SIZE 13:8 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_FATAL_ERROR_DETECTED 18:18 /* RWIVF */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS 6:6 /* RWCVF */
#define NV_PF0_STATUS_COMMAND_BUS_MASTER_ENABLE 2:2 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_BRIDGE_CONFIGURATION_RETRY_ENABLE_INITIATE_FUNCTION_LEVEL_RESET 15:15 /* RWIVF */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS 18:18 /* RWCVF */
#define NV_PF0_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS 8:8 /* RWCVF */
#define NV_PF0_MSIX_CAPABILITY_HEADR_AND_CONTROL_MSIX_ENABLE 31:31 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_RELAXED_ORDERING_DEFAULT 0x00000001 /* RWI-V */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_EXTENDED_TAG_FIELD_ENABLE_DEFAULT 0x00000001 /* RWI-V */
#define NV_PF0_PF_RESIZABLE_BAR_CONTROL 0x000001a0 /* RW-4R */
#define NV_PF0_INITIAL_AND_TOTAL_VFS_TOTAL_VFS 31:16 /* R-EVF */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_PROGRAMMING_INTERFACE 15:8 /* R-IVF */
#define NV_PF0_DEVICE_VENDOR_ID_VENDOR_ID_DEFAULT 0x000010de /* R-E-V */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_EXTENDED_TAG_FIELD_ENABLE 8:8 /* RWIVF */
#define NV_PF0_DEVICE_CONTROL_2 0x00000068 /* RW-4R */
#define NV_PF0_DEVICE_CAPABILITIES_FUNCTION_LEVEL_RESET_CAPABILITY 28:28 /* R-IVF */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS 0:0 /* RWCVF */
#define NV_PF0_REVISION_ID_AND_CLASS_CODE_SUB_CLASS_CODE 23:16 /* R-IVF */
#define NV_PF0_DEVICE_VENDOR_ID_VENDOR_ID 15:0 /* R-EVF */
#define NV_PF0_BASE_ADDRESS_REGISTERS_0_ADDR_TYPE_64BIT 2 /* */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS 0x0000014c /* RW-4R */
#define NV_PF0_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS 4:4 /* RWCVF */
#define NV_PF0_STATUS_COMMAND 0x00000004 /* RW-4R */
#define NV_PF0_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS 13:13 /* RWCVF */
#define NV_PF0_STATUS_COMMAND_IO_SPACE_ENABLE_ENABLE 1 /* */
#define NV_PF0_DEVICE_CONTROL_AND_STATUS_ENABLE_RELAXED_ORDERING 4:4 /* RWIVF */
#define NV_PF0_VF_STRIDE_AND_OFFSET_FIRST_VF_OFFSET 15:0 /* R-IVF */
#define NV_PF0_CORRECTABLE_ERROR_STATUS 0x00000158 /* RW-4R */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_RECOVERY_INDICATION 17:17 /* R-IVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_VENDOR_ID 15:0 /* R-IVF */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_2_AND_GENERAL_RECOVERY_INDICATION_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1_NV_DVSEC0_VENDOR_ID_DEFAULT 0x000010de /* R-I-V */
#define NV_PF0_DESIGNATED_VENDOR_SPECIFIC_0_HEADER_1 0x00000af4 /* R--4R */
#define NV_PF0_DEVICE_CAPABILITIES_2 0x00000064 /* R--4R */
#define NV_PF0_DEVICE_CAPABILITIES_2_COMPLETION_TIMEOUT_RANGES_SUPPORTED 3:0 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_COMPLETION_TIMEOUT_RANGES_SUPPORTED_DEFAULT 0x00000003 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_COMPLETION_TIMEOUT_DISABLE_SUPPORTED 4:4 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_COMPLETION_TIMEOUT_DISABLE_SUPPORTED_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_ARI_FORWARDING_SUPPORTED 5:5 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_ARI_FORWARDING_SUPPORTED_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_ATOMICOP_ROUTING_SUPPORTED 6:6 /* R-CVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_ATOMICOP_ROUTING_SUPPORTED_DEFAULT 0x00000000 /* R-C-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_32_BIT_ATOMICOP_COMPLETER_SUPPORTED 7:7 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_32_BIT_ATOMICOP_COMPLETER_SUPPORTED_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_64_BIT_ATOMICOP_COMPLETER_SUPPORTED 8:8 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_64_BIT_ATOMICOP_COMPLETER_SUPPORTED_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_128_BIT_CAS_COMPLETER_SUPPORTED 9:9 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_128_BIT_CAS_COMPLETER_SUPPORTED_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING 10:10 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_NO_RO_ENABLED_PR_PR_PASSING_DEFAULT 0x00000000 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_LTR_MECHANISM_SUPPORTED 11:11 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_LTR_MECHANISM_SUPPORTED_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_TPH_COMPLETER_SUPPORTED 13:12 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_TPH_COMPLETER_SUPPORTED_DEFAULT 0x00000000 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED 16:16 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_10_BIT_TAG_COMPLETER_SUPPORTED_DEFAULT 0x00000001 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED 17:17 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_10_BIT_TAG_REQUESTER_SUPPORTED_DEFAULT 0x00000001 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED 19:18 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_OBFF_SUPPORTED_DEFAULT 0x00000001 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_EXTENDED_FMT_FIELD_SUPPORTED 20:20 /* R-IVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_EXTENDED_FMT_FIELD_SUPPORTED_DEFAULT 0x00000001 /* R-I-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_SUPPORTED 21:21 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_END_END_TLP_PREFIX_SUPPORTED_DEFAULT 0x00000000 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIXES 23:22 /* R-CVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_MAX_END_END_TLP_PREFIXES_DEFAULT 0x00000001 /* R-C-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED 25:24 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_SUPPORTED_DEFAULT 0x00000002 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_INITIALIZATION_REQUIRED 26:26 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_EMERGENCY_POWER_REDUCTION_INITIALIZATION_REQUIRED_DEFAULT 0x00000000 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_DMWR_COMPLETER_SUPPORTED 28:28 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_DMWR_COMPLETER_SUPPORTED_DEFAULT 0x00000000 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_DMWR_LENGTHS_SUPPORTED 30:29 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_DMWR_LENGTHS_SUPPORTED_DEFAULT 0x00000000 /* R-E-V */
#define NV_PF0_DEVICE_CAPABILITIES_2_FRS_SUPPORTED 31:31 /* R-EVF */
#define NV_PF0_DEVICE_CAPABILITIES_2_FRS_SUPPORTED_DEFAULT 0x00000001 /* R-E-V */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1 0x00000b04 /* R--4R */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_POD 0:0 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_SCPM 1:1 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_SEQUENCE_TOO_BIG 2:2 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PRE_IFF_CRC_CHECK_FAILED 3:3 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_POST_IFF_CRC_CHECK_FAILED 4:4 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_ECC_UNCORRECTABLE_ERROR 5:5 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_CMD_FORMAT_ERROR 6:6 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR 7:7 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_C2C_MISC_LINK_ERROR 8:8 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_C2C_HBI_LINK_ERROR 9:9 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_SCPM 10:10 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_DCLS 11:11 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_EMP 12:12 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_UNCORRECTABLE_ERRORS 13:13 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FSP_WDT 14:14 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_SCPM 15:15 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_DCLS 16:16 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_SEC2_WDT 17:17 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_GSP_DCLS 18:18 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_GSP_WDT 19:19 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PMU_DCLS 20:20 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PMU_WDT 21:21 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_POD_2ND 22:22 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUSE_SCPM_2ND 23:23 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_SEQUENCE_TOO_BIG_2ND 24:24 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_PRE_IFF_CRC_CHECK_FAILED_2ND 25:25 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_POST_IFF_CRC_CHECK_FAILED_2ND 26:26 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_ECC_UNCORRECTABLE_ERROR_2ND 27:27 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_CMD_FORMAT_ERROR_2ND 28:28 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_IFF_PRI_ERROR_2ND 29:29 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_DEVICE_LOCKDOWN 30:30 /* R-IVF */
#define NV_PF0_DVSEC0_SEC_FAULT_REGISTER_1_FUNCTION_LOCKDOWN 31:31 /* R-IVF */
#endif // __gb100_dev_pcfg_pf0_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_perf_h__
#define __gb100_dev_perf_h__
#define NV_PERF_PMASYS_CHANNEL_OUTBASE__SIZE_2 2 /* */
#define NV_PERF_PMASYS_CBLOCK_BPC_CONFIG_SECURE__SIZE_1 5 /* */
#endif // __gb100_dev_gsp_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_therm_h__
#define __gb100_dev_therm_h__
#define NV_THERM_I2CS_SCRATCH 0x000200bc /* RW-4R */
#define NV_THERM_I2CS_SCRATCH_DATA 31:0 /* RWIVF */
#define NV_THERM_I2CS_SCRATCH_DATA_INIT 0x00000000 /* RWI-V */
#endif // __gb100_dev_therm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_therm_addendum_h__
#define __gb100_dev_therm_addendum_h__
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE NV_THERM_I2CS_SCRATCH
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS 31:0
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS 0x000000FF
#define NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_FAILED 0x00000000
#endif // __gb100_dev_therm_addendum_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_top_h__
#define __gb100_dev_top_h__
#define NV_PTOP_DEVICE_INFO_CFG 0x000224fc /* RW-4R */
#define NV_PTOP_DEVICE_INFO_CFG_VERSION 3:0 /* RWDUF */
#define NV_PTOP_DEVICE_INFO_CFG_VERSION_INIT 0x2 /* RWD-V */
#define NV_PTOP_DEVICE_INFO2(i) (0x00022800+(i)*4) /* RW-4A */
#define NV_PTOP_DEVICE_INFO2__SIZE_1 353 /* */
#define NV_PTOP_DEVICE_INFO2_ROW_VALUE 31:0 /* RWDVF */
#define NV_PTOP_DEVICE_INFO2_ROW_VALUE_INVALID 0x00000000 /* R-D-V */
#define NV_PTOP_DEVICE_INFO2_ROW_CHAIN 31:31 /* */
#define NV_PTOP_DEVICE_INFO2_ROW_CHAIN_MORE 0x1 /* */
#define NV_PTOP_DEVICE_INFO2_ROW_CHAIN_LAST 0x0 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_FAULT_ID 10:0 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_FAULT_ID_INVALID 0x000 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_GROUP_ID 15:11 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_INSTANCE_ID 23:16 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM 30:24 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_LCE 0x13 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_TYPE_ENUM_HSHUB 0x18 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_RESET_ID 39:32 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_RESET_ID_INVALID 0x00 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_DEVICE_PRI_BASE 57:40 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE 62:62 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE_TRUE 0x1 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_IS_ENGINE_FALSE 0x0 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_RLENG_ID 65:64 /* */
#define NV_PTOP_DEVICE_INFO2_DEV_RUNLIST_PRI_BASE 89:74 /* */
#define NV_PTOP0_DEVICE_INFO_CFG 0x000224fc /* RW-4R */
#define NV_PTOP0_DEVICE_INFO_CFG_VERSION 3:0 /* RWDUF */
#define NV_PTOP0_DEVICE_INFO_CFG_VERSION_INIT 0x2 /* RWD-V */
#define NV_PTOP0_DEVICE_INFO2(i) (0x00022800+(i)*4) /* RW-4A */
#define NV_PTOP0_DEVICE_INFO2__SIZE_1 353 /* */
#define NV_PTOP0_DEVICE_INFO2_ROW_VALUE 31:0 /* RWDVF */
#define NV_PTOP0_DEVICE_INFO2_ROW_VALUE_INVALID 0x00000000 /* R-D-V */
#define NV_PTOP0_DEVICE_INFO2_ROW_CHAIN 31:31 /* */
#define NV_PTOP0_DEVICE_INFO2_ROW_CHAIN_MORE 0x1 /* */
#define NV_PTOP0_DEVICE_INFO2_ROW_CHAIN_LAST 0x0 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_FAULT_ID 10:0 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_FAULT_ID_INVALID 0x000 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_GROUP_ID 15:11 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_INSTANCE_ID 23:16 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_TYPE_ENUM 30:24 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_TYPE_ENUM_LCE 0x13 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_TYPE_ENUM_HSHUB 0x18 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_RESET_ID 39:32 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_RESET_ID_INVALID 0x00 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_DEVICE_PRI_BASE 57:40 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_IS_ENGINE 62:62 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_IS_ENGINE_TRUE 0x1 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_IS_ENGINE_FALSE 0x0 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_RLENG_ID 65:64 /* */
#define NV_PTOP0_DEVICE_INFO2_DEV_RUNLIST_PRI_BASE 89:74 /* */
#define NV_PTOP1_DEVICE_INFO_CFG 0x000324fc /* RW-4R */
#define NV_PTOP1_DEVICE_INFO_CFG_VERSION 3:0 /* RWDUF */
#define NV_PTOP1_DEVICE_INFO_CFG_VERSION_INIT 0x2 /* RWD-V */
#define NV_PTOP1_DEVICE_INFO2(i) (0x00032800+(i)*4) /* RW-4A */
#define NV_PTOP1_DEVICE_INFO2__SIZE_1 353 /* */
#define NV_PTOP1_DEVICE_INFO2_ROW_VALUE 31:0 /* RWDVF */
#define NV_PTOP1_DEVICE_INFO2_ROW_VALUE_INVALID 0x00000000 /* R-D-V */
#define NV_PTOP1_DEVICE_INFO2_ROW_CHAIN 31:31 /* */
#define NV_PTOP1_DEVICE_INFO2_ROW_CHAIN_MORE 0x1 /* */
#define NV_PTOP1_DEVICE_INFO2_ROW_CHAIN_LAST 0x0 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_FAULT_ID 10:0 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_FAULT_ID_INVALID 0x000 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_GROUP_ID 15:11 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_INSTANCE_ID 23:16 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_TYPE_ENUM 30:24 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_TYPE_ENUM_LCE 0x13 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_TYPE_ENUM_HSHUB 0x18 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_RESET_ID 39:32 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_RESET_ID_INVALID 0x00 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_DEVICE_PRI_BASE 57:40 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_IS_ENGINE 62:62 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_IS_ENGINE_TRUE 0x1 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_IS_ENGINE_FALSE 0x0 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_RLENG_ID 65:64 /* */
#define NV_PTOP1_DEVICE_INFO2_DEV_RUNLIST_PRI_BASE 89:74 /* */
#define NV_PTOP_DEVICE_INFO_CFG_MAX_DEVICES 15:4 /* RWXUF */
#define NV_PTOP_DEVICE_INFO_CFG_MAX_DEVICES_INIT 0x099 /* RWD-V */
#define NV_PTOP_DEVICE_INFO_CFG_MAX_ROWS_PER_DEVICE 19:16 /* RWXUF */
#define NV_PTOP_DEVICE_INFO_CFG_MAX_ROWS_PER_DEVICE_INIT 0x3 /* RW--V */
#define NV_PTOP_DEVICE_INFO_CFG_NUM_ROWS 31:20 /* RWXUF */
#define NV_PTOP_DEVICE_INFO_CFG_NUM_ROWS_INIT 0x161 /* RWD-V */
#endif // __gb100_dev_top_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_dev_vm_h__
#define __gb100_dev_vm_h__
#define NV_VIRTUAL_FUNCTION_PRIV 0x0002FFFF:0x00000000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_RL 0x00009FFF:0x00008000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO 0x0042FFFF:0x00400000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_USER 0x0003FFFF:0x00030000 /* RW--D */
#define NV_VIRTUAL_FUNCTION 0x0003FFFF:0x00030000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_REGION5_GSP 0x0004FFFF:0x00040000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_REGION0 0x00007FFF:0x00000000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_REGION1 0x00009FFF:0x00008000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_REGION2 0x0002FFFF:0x0000A000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_REGION3 0x0003FFFF:0x00030000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_REGION4 0x0042FFFF:0x00400000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_REGION5 0x0004FFFF:0x00040000 /* RW--L */
#define NV_VIRTUAL_FUNCTION_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PHYS_OFFSET_REGION0 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PHYS_OFFSET_REGION1 0x00DBFFFF:0x00D80000 /* RW--D */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE 0x00000F10 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE__VFALIAS NV_XAL_EP_FUNC_L2_SYSMEM_INVALIDATE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED 0x00000F14 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED__VFALIAS NV_XAL_EP_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_SYSMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE 0x00000F18 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE__VFALIAS NV_XAL_EP_FUNC_L2_PEERMEM_INVALIDATE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED 0x00000F1C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED__VFALIAS NV_XAL_EP_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN (31-1):0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_L2_PEERMEM_INVALIDATE_COMPLETED_STATUS_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR 0x00000F70 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR__VFALIAS NV_XAL_EP_FUNC_BAR2_BLOCK_LOW_ADDR(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MAP 31:10 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING 0:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING 1:1 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE 9:9 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET 11:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR 31:12 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_FUNC_BAR2_BLOCK_LOW_ADDR_PTR_0 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP__VFALIAS NV_CTRL_CPU_INTR_TOP(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET__VFALIAS NV_CTRL_CPU_INTR_TOP_EN_SET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR__VFALIAS NV_CTRL_CPU_INTR_TOP_EN_CLEAR(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF__VFALIAS NV_CTRL_CPU_INTR_LEAF((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET__VFALIAS NV_CTRL_CPU_INTR_LEAF_EN_SET((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR__VFALIAS NV_CTRL_CPU_INTR_LEAF_EN_CLEAR((16*f)+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PFB_VECTOR 141 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_IOCTRL_INTR_1_VECTOR NV_INTERRUPT_NVLW_INTR_1_VECTOR /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_THERMAL_VECTOR 146 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_HDACODEC_VECTOR 147 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PTIMER_VECTOR 148 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PMGR_VECTOR 149 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_IOCTRL_INTR_0_VECTOR NV_INTERRUPT_NVLW_INTR_0_VECTOR /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PMU_VECTOR 152 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LTC_ALL_VECTOR 153 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PDISP_VECTOR 154 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_GSP_INTR_0_VECTOR 155 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PBUS_VECTOR 156 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_XVE_VECTOR 157 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PRIV_RING_VECTOR 158 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_PTIMER_ALARM_VECTOR 159 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER__VFALIAS NV_CTRL_CPU_INTR_LEAF_TRIGGER(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH__SIZE_1 16 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH__VFALIAS NV_CTRL_MAILBOX_SCRATCH(f*16+i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH_DATA 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL__VFALIAS NV_CTRL_VF_PRIV_DOORBELL(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_HANDLE 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_VECTOR 11:0 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_RSVD 30:12 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_CPU_NOTIFICATION 31:31 /* -WXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_CPU_NOTIFICATION_TRUE 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL_CPU_NOTIFICATION_FALSE 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER(i) (0x2300+(i)*4) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER__VFALIAS NV_PTIMER_VF_TIMER(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_NSEC 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_USEC 31:10 /* RWIUF */
#define NV_VIRTUAL_FUNCTION_PRIV_TIMER_USEC_INIT 0x0 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_NON_REPLAY_FAULT_BUFFER 0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_REPLAY_FAULT_BUFFER 1 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO(i) (0x00003000+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_LO_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE 2:1 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_PHYS_VOL 3:3 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_LO_ADDR 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI(i) (0x00003004+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_HI_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_HI_ADDR 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET(i) (0x00003008+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_GET_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT(i) (0x0000300C+(i)*32) /* R--4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_PUT_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE__VFALIAS NV_PFB_PRI_MMU_FAULT_BUFFER_SIZE_VIRT(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL__VFALIAS NV_PFB_PRI_MMU_PAGE_FAULT_CTRL_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_ADDR_LO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE 1:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_ADDR_HI_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_ADDR_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO__VFALIAS NV_PFB_PRI_MMU_FAULT_INST_LO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ENGINE_ID_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE_VID_MEM 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_APERTURE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI__VFALIAS NV_PFB_PRI_MMU_FAULT_INST_HI_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INST_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO__VFALIAS NV_PFB_PRI_MMU_FAULT_INFO_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS__VFALIAS NV_PFB_PRI_MMU_FAULT_STATUS_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT 1:1 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS 2:2 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT 3:3 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS 4:4 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT 5:5 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS 6:6 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT 7:7 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE 8:8 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE 9:9 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR 10:10 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR 11:11 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW 12:12 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW 13:13 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED 14:14 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED 15:15 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VAB_ERROR 16:16 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VAB_ERROR_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VAB_ERROR_SET 0x00000000 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_BUSY_TYPE 29:28 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_BUSY_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_BUSY 30:30 /* R-EVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_BUSY_FALSE 0x00000000 /* R-E-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_BUSY_TRUE 0x00000001 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID 31:31 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_PDB_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR 31:4 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB 0x000030A4 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_UPPER_PDB_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR 19:0 /* RWEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE 0x000030B0 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE__VFALIAS NV_PFB_PRI_MMU_INVALIDATE_VIRT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE 16:15 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID 21:21 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_PASID_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE 22:22 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_USE_SIZE_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH 23:23 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_PROP_FLUSH_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK 0x00000004 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL 0x00000005 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL 0x00000007 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SKIPPED 30:30 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SKIPPED_FALSE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_SKIPPED_TRUE 0x00000001 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG 0x00003100 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY 20:20 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD 30:30 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE 31:31 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG 0x00003100 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_CONFIG(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_GVA_NOTIFY 20:20 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_GVA_NOTIFY_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_GVA_NOTIFY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PD 30:30 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PD_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PD_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PCIE 31:31 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG 0x00003200 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_CONFIG(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_GVA_NOTIFY 20:20 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_GVA_NOTIFY_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_GVA_NOTIFY_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PD 30:30 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PD_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PD_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PCIE 31:31 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_LO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO 0x00003208 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_LO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_HI(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI 0x0000320C /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_HI(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE 0x00003110 /* R--4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE 0x00003110 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE 0x00003210 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET 0x00003114 /* RW-4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET 0x00003114 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_GET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET 0x00003214 /* RW-4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_GET(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT 0x00003118 /* R--4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT 0x00003118 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_PUT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT 0x00003218 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_PUT(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO 0x0000311C /* R--4P */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO 0x0000311C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO__VFALIAS NV_PFB_FBHUB0_ACCESS_COUNTER_NOTIFY_BUFFER_INFO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER0_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO 0x0000321C /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO__VFALIAS NV_PFB_FBHUB1_ACCESS_COUNTER_NOTIFY_BUFFER_INFO(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_ACCESS_COUNTER1_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO(i) (0x00010000+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO__VFALIAS NV_XTL_MSIX_TABLE_ADDR_LO(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI(i) (0x00010004+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI__VFALIAS NV_XTL_MSIX_TABLE_ADDR_HI(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA(i) (0x00010008+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA__VFALIAS NV_XTL_MSIX_TABLE_DATA(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL__VFALIAS NV_XTL_MSIX_TABLE_VECTOR_CONTROL(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_RSVD 31:1 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO(i) (0x00410000+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO__VFALIAS NV_XTL_MSIX_TABLE_ADDR_LO(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI(i) (0x00410004+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI__VFALIAS NV_XTL_MSIX_TABLE_ADDR_HI(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA(i) (0x00410008+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA__VFALIAS NV_XTL_MSIX_TABLE_DATA(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL(i) (0x0041000C+(i)*16) /* RW-4A */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 12 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL__VFALIAS NV_XTL_MSIX_TABLE_VECTOR_CONTROL(f,i) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD 31:1 /* C--VF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA 0x00020000 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA__VFALIAS NV_XTL_MSIX_PBA(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA 0x00420000 /* R--4R */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA__VFALIAS NV_XTL_MSIX_PBA(f) /* */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_VIRTUAL_FUNCTION_PRIV_JUMBO_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_VIRTUAL_FUNCTION_CFG0 0x00030000 /* C--4R */
#define NV_VIRTUAL_FUNCTION_CFG0__VFALIAS NV_PTOP_USERMODE_INFO /* */
#define NV_VIRTUAL_FUNCTION_CFG0_USERMODE_CLASS_ID 15:0 /* C--UF */
#define NV_VIRTUAL_FUNCTION_CFG0_USERMODE_CLASS_ID_VALUE 50785 /* C---V */
#define NV_VIRTUAL_FUNCTION_CFG0_RSVD 31:16 /* C--UF */
#define NV_VIRTUAL_FUNCTION_CFG0_RSVD_VALUE_ZERO 0x0000 /* C---V */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0__VFALIAS NV_PTIMER_TIME_0 /* */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1__VFALIAS NV_PTIMER_TIME_1 /* */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL 0x30090 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_DOORBELL__VFALIAS NV_CTRL_VF_DOORBELL(f) /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_HANDLE 31:0 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_VECTOR 11:0 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RSVD 15:12 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_ID 22:16 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_ID_INVALID_RUNLIST 0x7F /* -W--V */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL 22:22 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_DISABLE 0x1 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RUNLIST_DOORBELL_ENABLE 0x0 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_RSVD2 31:23 /* -WXUF */
#define NV_VIRTUAL_FUNCTION_DOORBELL_GSP_DOORBELL 31:31 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_GSP_DOORBELL_DISABLE 0x1 /* */
#define NV_VIRTUAL_FUNCTION_DOORBELL_GSP_DOORBELL_ENABLE 0x0 /* */
#define NV_VIRTUAL_FUNCTION_ERR_CONT 0x30094 /* R--4R */
#define NV_VIRTUAL_FUNCTION_ERR_CONT__VFALIAS NV_CTRL_ERR_CONT /* */
#endif // __gb100_dev_vm_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_hwproject_h__
#define __gb100_hwproject_h__
#define NV_LITTER_NUM_SUBCTX 64
#endif // __gb100_hwproject_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_pri_nv_xal_ep_h__
#define __gb100_pri_nv_xal_ep_h__
#define NV_XAL_EP_INTR_0 0x0010f100 /* RW-4R */
#define NV_XAL_EP_INTR_0_PRI_FECSERR 1:1 /* RWIVF */
#define NV_XAL_EP_INTR_0_PRI_FECSERR_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT 2:2 /* RWIVF */
#define NV_XAL_EP_INTR_0_PRI_REQ_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT 3:3 /* RWIVF */
#define NV_XAL_EP_INTR_0_PRI_RSP_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_XAL_EP_INTR_0_FB_ACK_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_INTR_0_TRS_TIMEOUT 24:24 /* RWIVF */
#define NV_XAL_EP_INTR_0_TRS_TIMEOUT_PENDING 0x1 /* R---V */
#define NV_XAL_EP_SCPM_PRI_DUMMY_DATA_PATTERN_INIT 0xbadf0200 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW 0x0010fd40 /* RW-4R */
#define NV_XAL_EP_BAR0_WINDOW_BASE 22:0 /* RWIUF */
#define NV_XAL_EP_BAR0_WINDOW_BASE_0 0x000000 /* RWI-V */
#define NV_XAL_EP_BAR0_WINDOW_BASE_SHIFT 0x000010 /* */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS 0x0010f808 /* R--4R */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED 0x0010f80c /* R--4R */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_CLEAN_COMPTAGS_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY 0x0010f810 /* R--4R */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED 0x0010f814 /* R--4R */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN 30:0 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_TOKEN_INIT 0x00000000 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS 31:31 /* R-IUF */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_IDLE 0x0 /* R-I-V */
#define NV_XAL_EP_UFLUSH_L2_FLUSH_DIRTY_COMPLETED_STATUS_BUSY 0x1 /* R---V */
#endif // __gb100_pri_nv_xal_ep_h__

49
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/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_pri_nv_xal_ep_p2p_h__
#define __gb100_pri_nv_xal_ep_p2p_h__
#define NV_XAL_EP_P2P 0x00827fff:0x00826000 /* RW--D */
#define NV_XAL_EP_P2P_REG_STRIDE 64
#define NV_XAL_EP_P2P_MAX_READ_SIZE_IN_DW 64
#define NV_XAL_EP_P2P_WMBOX_ADDR(i) (0x00826024+(i)*64) /* RW-4A */
#define NV_XAL_EP_P2P_WMBOX_ADDR__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_WMBOX_ADDR__PRIV_LEVEL_MASK 0x00826900 /* */
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS 0:0 /* RWIUF */
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS_DISABLED 0x1 /* RWI-V */
#define NV_XAL_EP_P2P_WMBOX_ADDR_DIS_ENABLED 0x0 /* RW--V */
#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR 23:1 /* RWIUF */
#define NV_XAL_EP_P2P_WMBOX_ADDR_ADDR_INIT 0x03ffff /* RWI-V */
#define NV_XAL_EP_P2P_WREQMB_L(i) (0x00826200+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_WREQMB_L__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_WREQMB_L__PRIV_LEVEL_MASK 0x00826900 /* */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR 23:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_L_PAGE_ADDR_INIT 0x000000 /* R-I-V */
#define NV_XAL_EP_P2P_WREQMB_H(i) (0x00826204+(i)*64) /* R--4A */
#define NV_XAL_EP_P2P_WREQMB_H__SIZE_1 8 /* */
#define NV_XAL_EP_P2P_WREQMB_H__PRIV_LEVEL_MASK 0x00826900 /* */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR 4:0 /* R-IUF */
#define NV_XAL_EP_P2P_WREQMB_H_REQ_ATTR_INIT 0x00 /* R-I-V */
#endif // __gb100_pri_nv_xal_ep_p2p_h__

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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb102_dev_nv_bus_h
#define gb102_dev_nv_bus_h
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#endif // gb102_dev_nv_bus_h

47
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/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef gb100_dev_nv_bus_addendum_h
#define gb100_dev_nv_bus_addendum_h
/*!
* @defgroup FRTS_INSECURE_SCRATCH_REGISTERS
*
* Used to communicate the location/size of insecure FRTS
*
* @{
*/
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_LO32 NV_PBUS_SW_SCRATCH(0x3D)
#define NV_PBUS_SW_FRTS_INSECURE_ADDR_HI32 NV_PBUS_SW_SCRATCH(0x3E)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG NV_PBUS_SW_SCRATCH(0x3F)
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K 15U:0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_INVALID 0x0000
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_SIZE_4K_SHIFT 12U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE 16U:16U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_FB 0U
#define NV_PBUS_SW_FRTS_INSECURE_CONFIG_MEDIA_TYPE_SYSMEM 1U
/*!@}*/
#endif // gb100_dev_nv_bus_addendum_h