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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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560.28.03
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@@ -150,6 +150,8 @@
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#define NV_PFAULT_CLIENT_HUB_PTP_X3 0x0000002E /* */
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#define NV_PFAULT_CLIENT_HUB_PTP_X4 0x0000002F /* */
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#define NV_PFAULT_CLIENT_HUB_PTP_X5 0x00000030 /* */
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#define NV_PFAULT_CLIENT_HUB_PTP_X6 0x00000031 /* */
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#define NV_PFAULT_CLIENT_HUB_PTP_X7 0x00000032 /* */
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#define NV_PFAULT_CLIENT_HUB_NVENC2 0x00000033 /* */
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#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER0 0x00000034 /* */
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#define NV_PFAULT_CLIENT_HUB_VPR_SCRUBBER1 0x00000035 /* */
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2003-2021 NVIDIA CORPORATION & AFFILIATES
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* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -26,12 +26,15 @@
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#define NV_PGC6_AON_FRTS_INPUT_WPR_SIZE_SECURE_SCRATCH_GROUP_03_0_WPR_SIZE_1MB_IN_4K 0x100
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC NV_PGC6_AON_SECURE_SCRATCH_GROUP_20
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED 0:0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_TRUE 0x1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MODE_ENABLED_FALSE 0x0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED 1:1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_TRUE 0x1
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_DEV_ENABLED_FALSE 0x0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE 6:5
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_NONE 0x0
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#define NV_PGC6_AON_SECURE_SCRATCH_GROUP_20_CC_MULTI_GPU_MODE_PROTECTED_PCIE 0x1
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#endif // __gh100_dev_gc6_island_addendum_h__
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@@ -23,7 +23,13 @@
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#ifndef __gh100_dev_gsp_h__
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#define __gh100_dev_gsp_h__
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#define NV_PGSP 0x113fff:0x110000 /* RW--D */
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#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
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#define NV_PGSP_FALCON_MAILBOX0 0x110040 /* RW-4R */
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#define NV_PGSP_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PGSP_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_FALCON_MAILBOX1 0x110044 /* RW-4R */
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#define NV_PGSP_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PGSP_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PGSP_FALCON_ENGINE 0x1103c0 /* RW-4R */
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#define NV_PGSP_FALCON_ENGINE_RESET 0:0 /* RWEVF */
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#define NV_PGSP_FALCON_ENGINE_RESET_DEASSERT 0 /* */
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#define NV_PGSP_FALCON_ENGINE_RESET_ASSERT 1 /* */
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