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560.28.03

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This commit is contained in:
Gaurav Juvekar
2024-07-19 15:45:15 -07:00
parent 5fdf5032fb
commit 448d5cc656
859 changed files with 165424 additions and 91129 deletions
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39
src/common/modeset/hdmipacket/nvhdmipkt_C771.c
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@@ -50,6 +50,12 @@ extern NVHDMIPKT_RESULT hdmiPacketCtrl9171(NVHDMIPKT_CLASS* pThis,
NVHDMIPKT_TYPE packetType,
NVHDMIPKT_TC transmitControl);
extern void hdmiWriteAviPacket9171(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket);
static NvU32
translateTransmitControlC771(NVHDMIPKT_CLASS* pThis,
NVHDMIPKT_TC transmitControl)
@@ -152,6 +158,38 @@ hdmiPacketCtrlC771(NVHDMIPKT_CLASS* pThis,
return result;
}
static void
hdmiWriteAviPacketC771(NVHDMIPKT_CLASS* pThis,
NvU32* pBaseReg,
NvU32 head,
NvU32 packetLen,
NvU8 const *const pPacket)
{
NvU32 data = 0;
if (packetLen > NVHDMIPKT_C771_MAX_PKT_BYTES_AVI)
{
NvHdmiPkt_Print(pThis, "ERROR - input AVI packet length incorrect. Write will be capped to max allowable bytes");
NvHdmiPkt_Assert(0);
}
data = REG_RD32(pBaseReg, NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(head));
data = FLD_SET_DRF_NUM(C771, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB14, pPacket[17], data);
data = FLD_SET_DRF_NUM(C771, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB15, pPacket[18], data);
data = FLD_SET_DRF_NUM(C771, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB16, pPacket[19], data);
data = FLD_SET_DRF_NUM(C771, _SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW, _PB17, pPacket[20], data);
REG_WR32(pBaseReg, NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(head), data);
// the lower 17 bytes remain the same as in 9171 class, call 9171 packet write function to program them
hdmiWriteAviPacket9171(pThis,
pBaseReg,
head,
17, // packetLen: HB0-2 and PB0-14
pPacket);
return;
}
static NVHDMIPKT_RESULT
hdmiWriteSharedGenericPacketC771(NVHDMIPKT_CLASS* pThis,
NvU32 subDevice,
@@ -305,4 +343,5 @@ initializeHdmiPktInterfaceC771(NVHDMIPKT_CLASS* pClass)
pClass->hdmiPacketCtrl = hdmiPacketCtrlC771;
pClass->hdmiPacketWrite = hdmiPacketWriteC771;
pClass->hdmiWriteAviPacket = hdmiWriteAviPacketC771;
}

14
src/common/modeset/timing/nvt_displayid20.c
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@@ -1542,11 +1542,10 @@ parseDisplayId20Timing7Descriptor(
pDescriptor = (const DISPLAYID_2_0_TIMING_7_DESCRIPTOR *)pVoidDescriptor;
// pclk is in 10Khz
// pixel_clock is in kHz
// pclk is in 1Khz
pTiming->pclk = ((pDescriptor->pixel_clock[2] << 16 |
pDescriptor->pixel_clock[1] << 8 |
pDescriptor->pixel_clock[0]) + 1) / 10;
pDescriptor->pixel_clock[1] << 8 |
pDescriptor->pixel_clock[0]) + 1);
pTiming->HBorder = 0;
pTiming->VBorder = 0;
@@ -1632,11 +1631,14 @@ parseDisplayId20Timing7Descriptor(
pTiming->etc.rr = NvTiming_CalcRR(pTiming->pclk,
pTiming->interlaced,
pTiming->HTotal,
pTiming->VTotal);
pTiming->VTotal) / 10;
pTiming->etc.rrx1k = NvTiming_CalcRRx1k(pTiming->pclk,
pTiming->interlaced,
pTiming->HTotal,
pTiming->VTotal);
pTiming->VTotal) / 10;
// pclk change to 10k
pTiming->pclk /= 10;
pTiming->etc.status = NVT_STATUS_DISPLAYID_7N(++count);

94
src/common/modeset/timing/nvt_util.c
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@@ -30,6 +30,7 @@
#include "nvBinSegment.h"
#include "nvtiming_pvt.h"
#include "nvmisc.h" // NV_MAX
PUSH_SEGMENTS
@@ -367,4 +368,97 @@ NvU16 NvTiming_MaxFrameWidth(NvU16 HVisible, NvU16 repMask)
return (HVisible / minPixelRepeat);
}
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 NvTiming_GetVrrFmin(
const NVT_EDID_INFO *pEdidInfo,
const NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo,
NvU32 nominalRefreshRateHz,
NVT_PROTOCOL sinkProtocol)
{
NvU32 fmin = 0;
// DP Adaptive Sync
if (sinkProtocol == NVT_PROTOCOL_DP)
{
if (pEdidInfo)
{
if (pEdidInfo->ext_displayid.version)
{
fmin = pEdidInfo->ext_displayid.range_limits[0].vfreq_min;
}
if (pEdidInfo->ext_displayid20.version && pEdidInfo->ext_displayid20.range_limits.seamless_dynamic_video_timing_change)
{
fmin = pEdidInfo->ext_displayid20.range_limits.vfreq_min;
}
// DisplayID 2.0 extension
if (pEdidInfo->ext_displayid20.version && pEdidInfo->ext_displayid20.total_adaptive_sync_descriptor != 0)
{
// Go through all the Adaptive Sync Data Blocks and pick the right frequency based on nominalRR
NvU32 i;
for (i = 0; i < pEdidInfo->ext_displayid20.total_adaptive_sync_descriptor; i++)
{
if ((pEdidInfo->ext_displayid20.adaptive_sync_descriptor[i].max_rr == nominalRefreshRateHz) ||
(nominalRefreshRateHz == 0))
{
fmin = pEdidInfo->ext_displayid20.adaptive_sync_descriptor[i].min_rr;
break;
}
}
}
if (!fmin)
{
NvU32 i;
for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++)
{
if (pEdidInfo->ldd[i].tag == NVT_EDID_DISPLAY_DESCRIPTOR_DRL)
{
fmin = pEdidInfo->ldd[i].u.range_limit.min_v_rate;
}
}
}
// Gsync
if (pEdidInfo->nvdaVsdbInfo.valid)
{
fmin = NV_MAX(pEdidInfo->nvdaVsdbInfo.vrrData.v1.minRefreshRate, 10);
}
}
// Display ID 2.0 Standalone
if (pDisplayIdInfo)
{
// Go through all the Adaptive Sync Data Blocks and pick the right frequency based on nominalRR
NvU32 i;
for (i = 0; i < pDisplayIdInfo->total_adaptive_sync_descriptor; i++)
{
if ((pDisplayIdInfo->adaptive_sync_descriptor[i].max_rr == nominalRefreshRateHz) ||
(nominalRefreshRateHz == 0))
{
fmin = pDisplayIdInfo->adaptive_sync_descriptor[i].min_rr;
break;
}
}
// If unable to find the value, choose a fallback from DisplayId
if (!fmin)
{
fmin = pDisplayIdInfo->range_limits.vfreq_min;
}
}
}
// HDMI 2.1 VRR
else if (sinkProtocol == NVT_PROTOCOL_HDMI)
{
if (pEdidInfo)
{
fmin = pEdidInfo->hdmiForumInfo.vrr_min;
}
}
return fmin;
}
POP_SEGMENTS

3
src/common/modeset/timing/nvtiming.h
View File

@@ -5807,6 +5807,9 @@ NvU32 NvTiming_IsTimingExactEqualEx(const NVT_TIMING *pT1, const NVT_TIMING *pT2
NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
NvU16 NvTiming_MaxFrameWidth(NvU16 HVisible, NvU16 rep);
NvU32 NvTiming_GetVrrFmin(const NVT_EDID_INFO *pEdidInfo, const NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo,
NvU32 nominalRefreshRateHz, NVT_PROTOCOL sinkProtocol);
// Establish timing enumeration
NVT_STATUS NvTiming_EnumEST(NvU32 index, NVT_TIMING *pT);
NVT_STATUS NvTiming_EnumESTIII(NvU32 index, NVT_TIMING *pT);