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560.28.03

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This commit is contained in:
Gaurav Juvekar
2024-07-19 15:45:15 -07:00
parent 5fdf5032fb
commit 448d5cc656
859 changed files with 165424 additions and 91129 deletions
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17
src/common/sdk/nvidia/inc/cc_drv.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -57,13 +57,14 @@ typedef enum ROTATE_IV_TYPE {
// Status value written into NvNotification.Info16
typedef enum KEY_ROTATION_STATUS {
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
KEY_ROTATION_STATUS_MAX_COUNT = 6,
KEY_ROTATION_STATUS_IDLE = 0, // Key rotation complete/not in progress
KEY_ROTATION_STATUS_PENDING = 1, // RM is waiting for clients to report their channels are idle for key rotation
KEY_ROTATION_STATUS_IN_PROGRESS = 2, // Key rotation is in progress
KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3, // Key rotation timeout failure, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4, // Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
KEY_ROTATION_STATUS_FAILED_ROTATION = 5, // Internal RM failure while rotating keys for a certain channel, RM will RC the channel
KEY_ROTATION_STATUS_PENDING_TIMER_SUSPENDED = 6, // Key rotation timer suspended waiting for kernel key rotation to complete
KEY_ROTATION_STATUS_MAX_COUNT = 7,
} KEY_ROTATION_STATUS;
typedef struct CC_AES_CRYPTOBUNDLE {

8
src/common/sdk/nvidia/inc/class/cl0050.h
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@@ -30,6 +30,8 @@
// Source file: class/cl0050.finn
//
#include "nvcfg_sdk.h"
#define NV_CE_UTILS (0x50U) /* finn: Evaluated from "NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID" */
#define NV0050_ALLOCATION_PARAMETERS_MESSAGE_ID (0x0050U)
@@ -65,3 +67,9 @@ typedef struct NV0050_ALLOCATION_PARAMETERS {
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID 4:4
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_FORCE_CE_ID_TRUE (0x00000001)
// Use a CC secure channel
#define NV0050_CEUTILS_FLAGS_CC_SECURE 5:5
#define NV0050_CEUTILS_FLAGS_CC_SECURE_FALSE (0x00000000)
#define NV0050_CEUTILS_FLAGS_CC_SECURE_TRUE (0x00000001)

88
src/common/sdk/nvidia/inc/class/cl00de.h
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@@ -36,37 +36,55 @@ extern "C" {
#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX)
#define RUSD_TIMESTAMP_INVALID 0
// seq = c_0 * b_0 + c_1 * (b_0 - 1) where c_0 == open_count and c_1 == close_count
// When they are equal, data is valid, otherwise data is being written.
// b_0 == 1 mod (b_0 - 1) and b_0 - 1 == (-1) mod b_0
// So, c_0 == seq mod (b_0 - 1) and c_1 == (-1 * seq) mod b_0
// c_1 cannot be calculated quite so naively because negative modulos aren't fun, so we
// instead do c_1 == (b_0 - (seq mod b_0)) mod b_0
//
#define RUSD_SEQ_BASE_SHIFT 20llu
#define RUSD_SEQ_BASE0 (1llu << RUSD_SEQ_BASE_SHIFT)
#define RUSD_SEQ_BASE1 (RUSD_SEQ_BASE0 - 1llu)
#define RUSD_SEQ_COEFF1(x) ((RUSD_SEQ_BASE0 - ((x) % RUSD_SEQ_BASE0)) % RUSD_SEQ_BASE0)
#define RUSD_SEQ_COEFF0(x) ((x) % RUSD_SEQ_BASE1)
#define RUSD_SEQ_WRAP_SHIFT 18llu
#define RUSD_SEQ_WRAP_VAL (1llu << RUSD_SEQ_WRAP_SHIFT)
#define RUSD_SEQ_DATA_VALID(x) (RUSD_SEQ_COEFF0(x) == RUSD_SEQ_COEFF1(x))
#define RUSD_SEQ_START (0xFF00000000000000LLU)
#define RUSD_SEQ_DATA_VALID(x) \
((((x) < RUSD_SEQ_START) && ((x) != RUSD_TIMESTAMP_INVALID)) || \
(((x) >= RUSD_SEQ_START) && (((x) & 0x1LLU) == 0x0LLU)))
//
// Helper macros to check seq before reading RUSD.
// No dowhile wrap as it is using continue/break
//
#define RUSD_SEQ_CHECK1(SHARED_DATA) \
NvU64 seq = (SHARED_DATA)->seq; \
portAtomicMemoryFenceLoad(); \
if (!RUSD_SEQ_DATA_VALID(seq)) \
#define RUSD_SEQ_CHECK1(dataField) \
NvU64 RUSD_SEQ = (dataField)->lastModifiedTimestamp; \
portAtomicMemoryFenceLoad(); \
if (!RUSD_SEQ_DATA_VALID(RUSD_SEQ)) \
continue;
#define RUSD_SEQ_CHECK2(SHARED_DATA) \
portAtomicMemoryFenceLoad(); \
if (seq == (SHARED_DATA)->seq) \
#define RUSD_SEQ_CHECK2(dataField) \
portAtomicMemoryFenceLoad(); \
if (RUSD_SEQ == (dataField)->lastModifiedTimestamp) \
break;
//
// Read RUSD data field `dataField` from NV00DE_SHARED_DATA struct `pSharedData` into destination pointer `pDst`
// `pDst` should be the data struct type matching `dataField`
// Check (pDst)->lastModifiedTimestamp using RUSD_IS_DATA_STALE to verify data validity.
//
#define RUSD_READ_DATA(pSharedData,dataField,pDst) \
do { \
portMemSet((pDst), 0, sizeof(*pDst)); \
for (NvU32 RUSD_READ_DATA_ATTEMPTS = 0; RUSD_READ_DATA_ATTEMPTS < 10; ++RUSD_READ_DATA_ATTEMPTS) \
{ \
RUSD_SEQ_CHECK1(&((pSharedData)->dataField)); \
portMemCopy((pDst), sizeof(*pDst), &((pSharedData)->dataField), sizeof(*pDst)); \
RUSD_SEQ_CHECK2(&((pSharedData)->dataField)); \
} \
} while(0);
//
// Check if RUSD data timestamp is stale.
// For polled data, returns true if data is older than `staleThreshold`
// For non-polled data, returns true if data was successfully read
//
#define RUSD_IS_DATA_STALE(timestamp,currentTime,staleThreshold) \
((((timestamp) < (RUSD_SEQ_START)) && /* Polled Data */ \
(((timestamp) == (RUSD_TIMESTAMP_INVALID)) || /* Invalid */ \
(((currentTime) - (timestamp)) > (staleThreshold)))) || \
(((timestamp) >= (RUSD_SEQ_START)) && /* Non-Polled Data */ \
(((timestamp) & (0x1LLU)) == 1LLU)))
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
RUSD_CLK_PUBLIC_DOMAIN_MEMORY,
@@ -89,6 +107,18 @@ enum {
RUSD_CLK_THROTTLE_REASON_DISPLAY_CLOCK_SETTING = NVBIT(8),
};
typedef struct RUSD_BAR1_MEMORY_INFO {
volatile NvU64 lastModifiedTimestamp;
NvU32 bar1Size;
NvU32 bar1AvailSize;
} RUSD_BAR1_MEMORY_INFO;
typedef struct RUSD_PMA_MEMORY_INFO {
volatile NvU64 lastModifiedTimestamp;
NvU64 totalPmaMemory;
NvU64 freePmaMemory;
} RUSD_PMA_MEMORY_INFO;
typedef struct RUSD_CLK_PUBLIC_DOMAIN_INFO {
NvU32 targetClkMHz;
} RUSD_CLK_PUBLIC_DOMAIN_INFO;
@@ -212,17 +242,22 @@ typedef struct RUSD_SHADOW_ERR_CONT {
} RUSD_SHADOW_ERR_CONT;
typedef struct NV00DE_SHARED_DATA {
// Temporarily duplicated - to be removed by nested structs below
volatile NvU64 seq;
NvU32 bar1Size;
NvU32 bar1AvailSize;
NvU64 totalPmaMemory;
NvU64 freePmaMemory;
NV_DECLARE_ALIGNED(RUSD_BAR1_MEMORY_INFO bar1MemoryInfo, 8);
NV_DECLARE_ALIGNED(RUSD_PMA_MEMORY_INFO pmaMemoryInfo, 8);
NV_DECLARE_ALIGNED(RUSD_SHADOW_ERR_CONT shadowErrCont, 8);
// gpuUpdateUserSharedData is sensitive to these two sections being contiguous
//
// GSP polling data section
// Polled data section
// All data structs are a volatile NvU64 timestamp followed by data contents.
// Access by reading timestamp, then copying the struct contents, then reading the timestamp again.
// If time0 matches time1, data has not changed during the read, and contents are valid.
@@ -260,9 +295,6 @@ typedef struct NV00DE_SHARED_DATA {
// POLL_POWER
NV_DECLARE_ALIGNED(RUSD_INST_POWER_USAGE instPowerUsage, 8);
// Non-polled GSP data section
NV_DECLARE_ALIGNED(RUSD_SHADOW_ERR_CONT shadowErrCont, 8);
} NV00DE_SHARED_DATA;
//

2
src/common/sdk/nvidia/inc/class/cl00f8.h
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@@ -96,6 +96,8 @@
#define NV_MEMORY_FABRIC_PAGE_SIZE_2M 0x200000
#define NV_MEMORY_FABRIC_PAGE_SIZE_512M 0x20000000
#define NV_MEMORY_FABRIC_PAGE_SIZE_256G 0x4000000000
#define NV00F8_ALLOC_FLAGS_DEFAULT 0

118
src/common/sdk/nvidia/inc/class/cl2080_notification.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -204,28 +204,33 @@ extern "C" {
#define NV2080_NOTIFIERS_SEC_FAULT_ERROR (163)
#define NV2080_NOTIFIERS_UNUSED_1 (164) // Unused
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_UP (165)
#define NV2080_NOTIFIERS_RESERVED166 (166)
#define NV2080_NOTIFIERS_RESERVED167 (167)
#define NV2080_NOTIFIERS_RESERVED168 (168)
#define NV2080_NOTIFIERS_RESERVED169 (169)
#define NV2080_NOTIFIERS_RESERVED170 (170)
#define NV2080_NOTIFIERS_RESERVED171 (171)
#define NV2080_NOTIFIERS_RESERVED172 (172)
#define NV2080_NOTIFIERS_RESERVED173 (173)
#define NV2080_NOTIFIERS_RESERVED174 (174)
#define NV2080_NOTIFIERS_RESERVED175 (175)
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_CE10 (166)
#define NV2080_NOTIFIERS_CE11 (167)
#define NV2080_NOTIFIERS_CE12 (168)
#define NV2080_NOTIFIERS_CE13 (169)
#define NV2080_NOTIFIERS_CE14 (170)
#define NV2080_NOTIFIERS_CE15 (171)
#define NV2080_NOTIFIERS_CE16 (172)
#define NV2080_NOTIFIERS_CE17 (173)
#define NV2080_NOTIFIERS_CE18 (174)
#define NV2080_NOTIFIERS_CE19 (175)
#define NV2080_NOTIFIERS_NVLINK_INFO_LINK_DOWN (176)
#define NV2080_NOTIFIERS_NVPCF_EVENTS (177)
#define NV2080_NOTIFIERS_HDMI_FRL_RETRAINING_REQUEST (178)
#define NV2080_NOTIFIERS_VRR_SET_TIMEOUT (179)
#define NV2080_NOTIFIERS_RESERVED180 (180)
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_OFA1 (180)
#define NV2080_NOTIFIERS_AUX_POWER_EVENT (181)
#define NV2080_NOTIFIERS_AUX_POWER_STATE_CHANGE (182)
#define NV2080_NOTIFIERS_RESERVED_183 (183) // Unused
#define NV2080_NOTIFIERS_GSP_PERF_TRACE (184)
#define NV2080_NOTIFIERS_INBAND_RESPONSE (185)
#define NV2080_NOTIFIERS_RESERVED_186 (186) // Unused
#define NV2080_NOTIFIERS_MAXCOUNT (187)
#define NV2080_NOTIFIERS_ECC_SBE_STORM (187)
#define NV2080_NOTIFIERS_DRAM_RETIREMENT_EVENT (188)
#define NV2080_NOTIFIERS_DRAM_RETIREMENT_FAILURE (189)
#define NV2080_NOTIFIERS_MAXCOUNT (190)
// Indexed GR notifier reference
#define NV2080_NOTIFIERS_GR(x) ((x == 0) ? (NV2080_NOTIFIERS_GR0) : (NV2080_NOTIFIERS_GR1 + (x - 1)))
@@ -233,9 +238,11 @@ extern "C" {
#define NV2080_NOTIFIER_TYPE_IS_GR(x) (((x) == NV2080_NOTIFIERS_GR0) || (((x) >= NV2080_NOTIFIERS_GR1) && ((x) <= NV2080_NOTIFIERS_GR7)))
// Indexed CE notifier reference
#define NV2080_NOTIFIERS_CE(x) (NV2080_NOTIFIERS_CE0 + (x))
#define NV2080_NOTIFIERS_CE_IDX(x) ((x) - NV2080_NOTIFIERS_CE0)
#define NV2080_NOTIFIER_TYPE_IS_CE(x) (((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9))
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_CE(x) (((x) < 10) ? (NV2080_NOTIFIERS_CE0 + (x)) : (NV2080_NOTIFIERS_CE10 + (x) - 10))
#define NV2080_NOTIFIERS_CE_IDX(x) (((x) <= NV2080_NOTIFIERS_CE9) ? ((x) - NV2080_NOTIFIERS_CE0) : ((x) - NV2080_NOTIFIERS_CE10 + 10))
#define NV2080_NOTIFIER_TYPE_IS_CE(x) ((((x) >= NV2080_NOTIFIERS_CE0) && ((x) <= NV2080_NOTIFIERS_CE9)) || \
(((x) >= NV2080_NOTIFIERS_CE10) && ((x) <= NV2080_NOTIFIERS_CE19)))
// Indexed MSENC notifier reference
#define NV2080_NOTIFIERS_NVENC(x) (NV2080_NOTIFIERS_NVENC0 + (x))
@@ -251,9 +258,10 @@ extern "C" {
#define NV2080_NOTIFIER_TYPE_IS_NVJPEG(x) (((x) >= NV2080_NOTIFIERS_NVJPEG0) && ((x) <= NV2080_NOTIFIERS_NVJPEG7))
// Indexed OFA notifier reference
#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_MAXCOUNT))
#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? (0) : (-1))
#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0))
// removal tracking bug: 3748354
#define NV2080_NOTIFIERS_OFAn(x) ((x == 0) ? (NV2080_NOTIFIERS_OFA0) : (NV2080_NOTIFIERS_OFA1))
#define NV2080_NOTIFIERS_OFA_IDX(x) ((x == NV2080_NOTIFIERS_OFA0) ? ((x) - NV2080_NOTIFIERS_OFA0) : ((x) - NV2080_NOTIFIERS_OFA1 + 1))
#define NV2080_NOTIFIER_TYPE_IS_OFA(x) (((x) == NV2080_NOTIFIERS_OFA0) || ((x) == NV2080_NOTIFIERS_OFA1))
#define NV2080_NOTIFIERS_GPIO_RISING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_RISING_INTERRUPT + (pin))
#define NV2080_NOTIFIERS_GPIO_FALLING_INTERRUPT(pin) (NV2080_NOTIFIERS_GPIO_0_FALLING_INTERRUPT + (pin))
@@ -323,19 +331,44 @@ extern "C" {
#define NV2080_ENGINE_TYPE_NVJPEG7 (0x00000032)
#define NV2080_ENGINE_TYPE_OFA (0x00000033)
#define NV2080_ENGINE_TYPE_OFA0 NV2080_ENGINE_TYPE_OFA
#define NV2080_ENGINE_TYPE_RESERVED34 (0x00000034)
#define NV2080_ENGINE_TYPE_RESERVED35 (0x00000035)
#define NV2080_ENGINE_TYPE_RESERVED36 (0x00000036)
#define NV2080_ENGINE_TYPE_RESERVED37 (0x00000037)
#define NV2080_ENGINE_TYPE_RESERVED38 (0x00000038)
#define NV2080_ENGINE_TYPE_RESERVED39 (0x00000039)
#define NV2080_ENGINE_TYPE_RESERVED3a (0x0000003a)
#define NV2080_ENGINE_TYPE_RESERVED3b (0x0000003b)
#define NV2080_ENGINE_TYPE_RESERVED3c (0x0000003c)
#define NV2080_ENGINE_TYPE_RESERVED3d (0x0000003d)
#define NV2080_ENGINE_TYPE_RESERVED3e (0x0000003e)
// removal tracking bug: 3748354
// Update the TYPE_COMP_DECOMP_COPYN defines as well when you update COPYN defines
#define NV2080_ENGINE_TYPE_COPY10 (0x00000034)
#define NV2080_ENGINE_TYPE_COPY11 (0x00000035)
#define NV2080_ENGINE_TYPE_COPY12 (0x00000036)
#define NV2080_ENGINE_TYPE_COPY13 (0x00000037)
#define NV2080_ENGINE_TYPE_COPY14 (0x00000038)
#define NV2080_ENGINE_TYPE_COPY15 (0x00000039)
#define NV2080_ENGINE_TYPE_COPY16 (0x0000003a)
#define NV2080_ENGINE_TYPE_COPY17 (0x0000003b)
#define NV2080_ENGINE_TYPE_COPY18 (0x0000003c)
#define NV2080_ENGINE_TYPE_COPY19 (0x0000003d)
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_OFA1 (0x0000003e)
#define NV2080_ENGINE_TYPE_RESERVED3f (0x0000003f)
#define NV2080_ENGINE_TYPE_LAST (0x00000040)
// See TBD documentation for how these defines work with existing ENGINE_TYPE_COPYN defines
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 (0x00000040)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY1 (0x00000041)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY2 (0x00000042)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY3 (0x00000043)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY4 (0x00000044)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY5 (0x00000045)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY6 (0x00000046)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY7 (0x00000047)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY8 (0x00000048)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY9 (0x00000049)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY10 (0x0000004a)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY11 (0x0000004b)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY12 (0x0000004c)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY13 (0x0000004d)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY14 (0x0000004e)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY15 (0x0000004f)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY16 (0x00000050)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY17 (0x00000051)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY18 (0x00000052)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19 (0x00000053)
#define NV2080_ENGINE_TYPE_LAST (0x00000054)
#define NV2080_ENGINE_TYPE_ALLENGINES (0xffffffff)
//
@@ -350,12 +383,20 @@ extern "C" {
#define NV2080_ENGINE_TYPE_NVJPEG_SIZE 8
#define NV2080_ENGINE_TYPE_NVDEC_SIZE 8
#define NV2080_ENGINE_TYPE_GR_SIZE 8
#define NV2080_ENGINE_TYPE_OFA_SIZE 1
#define NV2080_ENGINE_TYPE_OFA_SIZE 2
// Indexed engines
#define NV2080_ENGINE_TYPE_COPY(i) (NV2080_ENGINE_TYPE_COPY0+(i))
#define NV2080_ENGINE_TYPE_IS_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COPY0)
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY(i) (NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0 + (i))
#define NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i) (((i) >= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COMP_DECOMP_COPY19))
#define NV2080_ENGINE_TYPE_COMP_DECOMP_COPY_IDX(i) ((i) - NV2080_ENGINE_TYPE_COMP_DECOMP_COPY0)
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_COPY(i) (((i) < 10) ? (NV2080_ENGINE_TYPE_COPY0 + (i)) : (NV2080_ENGINE_TYPE_COPY10 + (i) - 10))
#define NV2080_ENGINE_TYPE_IS_COPY(i) ((((i) >= NV2080_ENGINE_TYPE_COPY0) && ((i) <= NV2080_ENGINE_TYPE_COPY9)) || \
(((i) >= NV2080_ENGINE_TYPE_COPY10) && ((i) <= NV2080_ENGINE_TYPE_COPY19)) || \
(NV2080_ENGINE_TYPE_IS_COMP_DECOMP_COPY(i)))
#define NV2080_ENGINE_TYPE_COPY_IDX(i) (((i) <= NV2080_ENGINE_TYPE_COPY9) ? \
((i) - NV2080_ENGINE_TYPE_COPY0) : ((i) - NV2080_ENGINE_TYPE_COPY10 + 10))
#define NV2080_ENGINE_TYPE_NVENC(i) (NV2080_ENGINE_TYPE_NVENC0+(i))
#define NV2080_ENGINE_TYPE_IS_NVENC(i) (((i) >= NV2080_ENGINE_TYPE_NVENC0) && ((i) < NV2080_ENGINE_TYPE_NVENC(NV2080_ENGINE_TYPE_NVENC_SIZE)))
@@ -373,9 +414,10 @@ extern "C" {
#define NV2080_ENGINE_TYPE_IS_GR(i) (((i) >= NV2080_ENGINE_TYPE_GR0) && ((i) < NV2080_ENGINE_TYPE_GR(NV2080_ENGINE_TYPE_GR_SIZE)))
#define NV2080_ENGINE_TYPE_GR_IDX(i) ((i) - NV2080_ENGINE_TYPE_GR0)
#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_LAST))
#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0))
#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? (0) : (-1))
// removal tracking bug: 3748354
#define NV2080_ENGINE_TYPE_OFAn(i) ((i == 0) ? (NV2080_ENGINE_TYPE_OFA0) : (NV2080_ENGINE_TYPE_OFA1))
#define NV2080_ENGINE_TYPE_IS_OFA(i) (((i) == NV2080_ENGINE_TYPE_OFA0) || ((i) == NV2080_ENGINE_TYPE_OFA1))
#define NV2080_ENGINE_TYPE_OFA_IDX(i) ((i == NV2080_ENGINE_TYPE_OFA0) ? ((i) - NV2080_ENGINE_TYPE_OFA0) : ((i) - NV2080_ENGINE_TYPE_OFA1 + 1))
#define NV2080_ENGINE_TYPE_IS_VALID(i) (((i) > (NV2080_ENGINE_TYPE_NULL)) && ((i) < (NV2080_ENGINE_TYPE_LAST)))

2
src/common/sdk/nvidia/inc/class/cla084.h
View File

@@ -85,5 +85,7 @@ typedef struct NVA084_ALLOC_PARAMETERS {
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
NvBool bDeviceProfilingEnabled;
} NVA084_ALLOC_PARAMETERS;

3
src/common/sdk/nvidia/inc/class/clc370_notification.h
View File

@@ -34,7 +34,8 @@ extern "C" {
#define NVC370_NOTIFIERS_BEGIN NV5070_NOTIFIERS_MAXCOUNT
#define NVC370_NOTIFIERS_RG_SEM_NOTIFICATION NVC370_NOTIFIERS_BEGIN + (0)
#define NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION NVC370_NOTIFIERS_RG_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_LTM_CALC_TIMEOUT NVC370_NOTIFIERS_WIN_SEM_NOTIFICATION + (1)
#define NVC370_NOTIFIERS_MAXCOUNT NVC370_NOTIFIERS_LTM_CALC_TIMEOUT + (1)
#ifdef __cplusplus
}; /* extern "C" */

77
src/common/sdk/nvidia/inc/class/clc671.h
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@@ -39,6 +39,83 @@ typedef volatile struct _clc671_tag0 {
#define NVC671_SF_HDMI_INFO_CTRL(i,j) (0x000E0000-0x000E0000+(i)*1024+(j)*64) /* RW-4A */
#define NVC671_SF_HDMI_INFO_CTRL__SIZE_1 4 /* */
#define NVC671_SF_HDMI_INFO_CTRL__SIZE_2 5 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC671_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#ifdef __cplusplus
}; /* extern "C" */

77
src/common/sdk/nvidia/inc/class/clc771.h
View File

@@ -33,6 +33,83 @@ typedef volatile struct _clc771_tag0 {
NvU32 dispSfUserOffset[0x400]; /* NV_PDISP_SF_USER 0x000D0FFF:0x000D0000 */
} _NvC771DispSfUser, NvC771DispSfUserMap;
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x000E0000-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x000E0004-0x000E0000+(i)*1024) /* R--4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x000E0008-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x000E000C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x000E0010-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x000E0014-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x000E0018-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x000E001C-0x000E0000+(i)*1024) /* RW-4A */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
#define NVC771_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
#define NVC771_SF_SHARED_GENERIC_CTRL(i,j) (0x000E0200-0x000E0000+(i)*1024+(j)*40) /* RW-4A */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */
#define NVC771_SF_SHARED_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */

104
src/common/sdk/nvidia/inc/class/clc86f.h
View File

@@ -82,4 +82,108 @@ typedef volatile struct Nvc86fControl_struct {
#define NVC86F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVC86F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#define NVC86F_WFI (0x00000078)
#define NVC86F_WFI_SCOPE 0:0
#define NVC86F_WFI_SCOPE_CURRENT_SCG_TYPE 0x00000000
#define NVC86F_WFI_SCOPE_CURRENT_VEID 0x00000000
#define NVC86F_WFI_SCOPE_ALL 0x00000001
// NOTE - MEM_OP_A and MEM_OP_B have been replaced in gp100 with methods for
// specifying the page address for a targeted TLB invalidate and the uTLB for
// a targeted REPLAY_CANCEL for UVM.
// The previous MEM_OP_A/B functionality is in MEM_OP_C/D, with slightly
// rearranged fields.
#define NVC86F_MEM_OP_A (0x00000028)
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_CLIENT_UNIT_ID 5:0 // only relevant for REPLAY_CANCEL_TARGETED
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVALIDATION_SIZE 5:0 // Used to specify size of invalidate, used for invalidates which are not of the REPLAY_CANCEL_TARGETED type
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_TARGET_GPC_ID 10:6 // only relevant for REPLAY_CANCEL_TARGETED
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE 7:6 // only relevant for invalidates with NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE for invalidating link TLB only, or non-link TLB only or all TLBs
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_LINK_TLBS 1
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 2
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_INVAL_SCOPE_RSVRVD 3
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_CANCEL_MMU_ENGINE_ID 8:0 // only relevant for REPLAY_CANCEL_VA_GLOBAL
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR 11:11
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_EN 0x00000001
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_SYSMEMBAR_DIS 0x00000000
#define NVC86F_MEM_OP_A_TLB_INVALIDATE_TARGET_ADDR_LO 31:12
#define NVC86F_MEM_OP_B (0x0000002c)
#define NVC86F_MEM_OP_B_TLB_INVALIDATE_TARGET_ADDR_HI 31:0
#define NVC86F_MEM_OP_C (0x00000030)
#define NVC86F_MEM_OP_C_MEMBAR_TYPE 2:0
#define NVC86F_MEM_OP_C_MEMBAR_TYPE_SYS_MEMBAR 0x00000000
#define NVC86F_MEM_OP_C_MEMBAR_TYPE_MEMBAR 0x00000001
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB 0:0
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ONE 0x00000000
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ALL 0x00000001 // Probably nonsensical for MMU_TLB_INVALIDATE_TARGETED
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC 1:1
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_ENABLE 0x00000000
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_GPC_DISABLE 0x00000001
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY 4:2 // only relevant if GPC ENABLE
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_NONE 0x00000000
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START 0x00000001
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE 6:5 // only relevant if GPC ENABLE
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_NONE 0x00000000
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_GLOBALLY 0x00000001
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACK_TYPE_INTRANODE 0x00000002
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE 9:7 //only relevant for REPLAY_CANCEL_VA_GLOBAL
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_READ 0
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE 1
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_STRONG 2
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_RSVRVD 3
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_WEAK 4
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ATOMIC_ALL 5
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_WRITE_AND_ATOMIC 6
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_ACCESS_TYPE_VIRT_ALL 7
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL 9:7 // Invalidate affects this level and all below
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_ALL 0x00000000 // Invalidate tlb caches at all levels of the page table
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_PTE_ONLY 0x00000001
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE0 0x00000002
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE1 0x00000003
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE2 0x00000004
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE3 0x00000005
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE4 0x00000006
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PAGE_TABLE_LEVEL_UP_TO_PDE5 0x00000007
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE 11:10 // only relevant if PDB_ONE
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_COHERENT 0x00000002
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_APERTURE_SYS_MEM_NONCOHERENT 0x00000003
#define NVC86F_MEM_OP_C_TLB_INVALIDATE_PDB_ADDR_LO 31:12 // only relevant if PDB_ONE
#define NVC86F_MEM_OP_C_ACCESS_COUNTER_CLR_TARGETED_NOTIFY_TAG 19:0
// MEM_OP_D MUST be preceded by MEM_OPs A-C.
#define NVC86F_MEM_OP_D (0x00000034)
#define NVC86F_MEM_OP_D_TLB_INVALIDATE_PDB_ADDR_HI 26:0 // only relevant if PDB_ONE
#define NVC86F_MEM_OP_D_OPERATION 31:27
#define NVC86F_MEM_OP_D_OPERATION_MEMBAR 0x00000005
#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE 0x00000009
#define NVC86F_MEM_OP_D_OPERATION_MMU_TLB_INVALIDATE_TARGETED 0x0000000a
#define NVC86F_MEM_OP_D_OPERATION_MMU_OPERATION 0x0000000b
#define NVC86F_MEM_OP_D_OPERATION_L2_PEERMEM_INVALIDATE 0x0000000d
#define NVC86F_MEM_OP_D_OPERATION_L2_SYSMEM_INVALIDATE 0x0000000e
// CLEAN_LINES is an alias for Tegra/GPU IP usage
#define NVC86F_MEM_OP_B_OPERATION_L2_INVALIDATE_CLEAN_LINES 0x0000000e
#define NVC86F_MEM_OP_D_OPERATION_L2_CLEAN_COMPTAGS 0x0000000f
#define NVC86F_MEM_OP_D_OPERATION_L2_FLUSH_DIRTY 0x00000010
#define NVC86F_MEM_OP_D_OPERATION_L2_WAIT_FOR_SYS_PENDING_READS 0x00000015
#define NVC86F_MEM_OP_D_OPERATION_ACCESS_COUNTER_CLR 0x00000016
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE 1:0
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MIMC 0x00000000
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_MOMC 0x00000001
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_ALL 0x00000002
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TYPE_TARGETED 0x00000003
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE 2:2
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MIMC 0x00000000
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_TYPE_MOMC 0x00000001
#define NVC86F_MEM_OP_D_ACCESS_COUNTER_CLR_TARGETED_BANK 6:3
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE 23:20
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_RESERVED 0x00000000
#define NVC86F_MEM_OP_D_MMU_OPERATION_TYPE_VIDMEM_ACCESS_BIT_DUMP 0x00000001
#endif // __gh100_clc86f_h__

20
src/common/sdk/nvidia/inc/class/clc8b5.h
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@@ -52,6 +52,10 @@
#define NVC8B5_LAUNCH_DMA_SRC_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_DST_TYPE 13:13
#define NVC8B5_LAUNCH_DMA_DST_TYPE_PHYSICAL (0x00000001)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE 21:20
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_PROT2PROT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_DEFAULT (0x00000000)
#define NVC8B5_LAUNCH_DMA_COPY_TYPE_SECURE (0x00000001)
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE 23:23
#define NVC8B5_LAUNCH_DMA_MEMORY_SCRUB_ENABLE_TRUE (0x00000001)
#define NVC8B5_LAUNCH_DMA_DISABLE_PLC 26:26
@@ -61,6 +65,22 @@
#define NVC8B5_OFFSET_OUT_LOWER (0x0000040C)
#define NVC8B5_OFFSET_OUT_LOWER_VALUE 31:0
#define NVC8B5_LINE_LENGTH_IN (0x00000418)
#define NVC8B5_SET_SECURE_COPY_MODE (0x00000500)
#define NVC8B5_SET_SECURE_COPY_MODE_MODE 0:0
#define NVC8B5_SET_SECURE_COPY_MODE_MODE_ENCRYPT (0x00000000)
#define NVC8B5_SET_SECURE_COPY_MODE_MODE_DECRYPT (0x00000001)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER (0x00000514)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER (0x00000518)
#define NVC8B5_SET_DECRYPT_AUTH_TAG_COMPARE_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER (0x00000530)
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER (0x00000534)
#define NVC8B5_SET_ENCRYPT_AUTH_TAG_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER (0x00000538)
#define NVC8B5_SET_ENCRYPT_IV_ADDR_UPPER_UPPER 24:0
#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER (0x0000053C)
#define NVC8B5_SET_ENCRYPT_IV_ADDR_LOWER_LOWER 31:0
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS (0x000006FC)
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE 0:0
#define NVC8B5_SET_MEMORY_SCRUB_PARAMETERS_DISCARDABLE_FALSE (0x00000000)

74
src/common/sdk/nvidia/inc/class/clc96f.h Normal file
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@@ -0,0 +1,74 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clc96f_h__
#define __gb100_clc96f_h__
typedef volatile struct Nvc96fControl_struct {
NvU32 Ignored00[0x23]; /* 0000-008b*/
NvU32 GPPut; /* GP FIFO put offset 008c-008f*/
NvU32 Ignored01[0x5c];
} Nvc96fControl, BlackwellAControlGPFifo;
#define BLACKWELL_CHANNEL_GPFIFO_A (0x0000C96F)
#define NVC96F_SET_OBJECT (0x00000000)
#define NVC96F_SEM_ADDR_LO (0x0000005c)
#define NVC96F_SEM_ADDR_LO_OFFSET 31:2
#define NVC96F_SEM_ADDR_HI (0x00000060)
#define NVC96F_SEM_ADDR_HI_OFFSET 24:0
#define NVC96F_SEM_PAYLOAD_LO (0x00000064)
#define NVC96F_SEM_PAYLOAD_HI (0x00000068)
#define NVC96F_SEM_EXECUTE (0x0000006c)
#define NVC96F_SEM_EXECUTE_OPERATION 2:0
#define NVC96F_SEM_EXECUTE_OPERATION_ACQUIRE 0x00000000
#define NVC96F_SEM_EXECUTE_OPERATION_RELEASE 0x00000001
#define NVC96F_SEM_EXECUTE_RELEASE_WFI 20:20
#define NVC96F_SEM_EXECUTE_RELEASE_WFI_DIS 0x00000000
#define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE 24:24
#define NVC96F_SEM_EXECUTE_PAYLOAD_SIZE_32BIT 0x00000000
/* GPFIFO entry format */
#define NVC96F_GP_ENTRY__SIZE 8
#define NVC96F_GP_ENTRY0_FETCH 0:0
#define NVC96F_GP_ENTRY0_FETCH_UNCONDITIONAL 0x00000000
#define NVC96F_GP_ENTRY0_FETCH_CONDITIONAL 0x00000001
#define NVC96F_GP_ENTRY0_GET 31:2
#define NVC96F_GP_ENTRY0_OPERAND 31:0
#define NVC96F_GP_ENTRY0_PB_EXTENDED_BASE_OPERAND 24:8
#define NVC96F_GP_ENTRY1_GET_HI 7:0
#define NVC96F_GP_ENTRY1_LEVEL 9:9
#define NVC96F_GP_ENTRY1_LEVEL_MAIN 0x00000000
#define NVC96F_GP_ENTRY1_LEVEL_SUBROUTINE 0x00000001
#define NVC96F_GP_ENTRY1_LENGTH 30:10
#define NVC96F_GP_ENTRY1_SYNC 31:31
#define NVC96F_GP_ENTRY1_SYNC_PROCEED 0x00000000
#define NVC96F_GP_ENTRY1_SYNC_WAIT 0x00000001
#define NVC96F_GP_ENTRY1_OPCODE 7:0
#define NVC96F_GP_ENTRY1_OPCODE_NOP 0x00000000
#define NVC96F_GP_ENTRY1_OPCODE_ILLEGAL 0x00000001
#define NVC96F_GP_ENTRY1_OPCODE_GP_CRC 0x00000002
#define NVC96F_GP_ENTRY1_OPCODE_PB_CRC 0x00000003
#define NVC96F_GP_ENTRY1_OPCODE_SET_PB_SEGMENT_EXTENDED_BASE 0x00000004
#endif // __gb100_clc96f_h__

45
src/common/sdk/nvidia/inc/class/clc96fsw.h Normal file
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@@ -0,0 +1,45 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
/* This file is *not* auto-generated. */
#ifndef _clc96f_sw_h_
#define _clc96f_sw_h_
#define NVC96F_NOTIFIERS_RC (0)
#define NVC96F_NOTIFIERS_REFCNT (1)
#define NVC96F_NOTIFIERS_NONSTALL (2)
#define NVC96F_NOTIFIERS_EVENTBUFFER (3)
#define NVC96F_NOTIFIERS_IDLECHANNEL (4)
#define NVC96F_NOTIFIERS_ENDCTX (5)
#define NVC96F_NOTIFIERS_SW (6)
#define NVC96F_NOTIFIERS_GR_DEBUG_INTR (7)
#define NVC96F_NOTIFIERS_REPLAYABLE_FAULT (8)
#define NVC96F_NOTIFIERS_KEY_ROTATION (9)
#define NVC96F_NOTIFIERS_MAXCOUNT (10)
/* NvNotification[] fields and values */
#define NVC96F_NOTIFICATION_STATUS_ERROR_BAD_ARGUMENT (0x2000)
#define NVC96F_NOTIFICATION_STATUS_ERROR_PROTECTION_FAULT (0x4000)
#endif /* _clc96f_sw_h_ */

29
src/common/sdk/nvidia/inc/class/clc9b5.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clc9b5_h__
#define __gb100_clc9b5_h__
#define BLACKWELL_DMA_COPY_A (0x0000C9B5)
#endif // __gb100_clc9b5_h__

29
src/common/sdk/nvidia/inc/class/clcd40.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcd40_h__
#define __gb100_clcd40_h__
#define BLACKWELL_INLINE_TO_MEMORY_A 0xCD40
#endif // __gb100_clcd40_h__

29
src/common/sdk/nvidia/inc/class/clcd97.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcd97_h__
#define __gb100_clcd97_h__
#define BLACKWELL_A 0xCD97
#endif // __gb100_clcd97_h__

29
src/common/sdk/nvidia/inc/class/clcdb0.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcdb0_h__
#define __gb100_clcdb0_h__
#define NVCDB0_VIDEO_DECODER (0x0000CDB0)
#endif // __gb100_clcdb0_h__

30
src/common/sdk/nvidia/inc/class/clcdc0.h Normal file
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@@ -0,0 +1,30 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcdc0_h__
#define __gb100_clcdc0_h__
#define BLACKWELL_COMPUTE_A 0xCDC0
#endif // __gb100_clcdc0_h__

29
src/common/sdk/nvidia/inc/class/clcdd1.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcdd1_h__
#define __gb100_clcdd1_h__
#define NVCDD1_VIDEO_NVJPG (0x0000CDD1)
#endif // __gb100_clcdd1_h__

29
src/common/sdk/nvidia/inc/class/clcdfa.h Normal file
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@@ -0,0 +1,29 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __gb100_clcdfa_h__
#define __gb100_clcdfa_h__
#define NVCDFA_VIDEO_OFA (0x0000CDFA)
#endif // __gb100_clcdfa_h__

112
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000system.h
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@@ -46,6 +46,8 @@
* When this bit is set, SLI is supported.
* NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT
* When this bit is set, EFI has initialized core channel
* NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED
* When this bit is set, RM test only code is supported.
*
* Possible status values returned are:
* NV_OK
@@ -63,17 +65,20 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
/* Valid feature values */
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI 0:0
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_SLI_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT 2:2
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_IS_EFI_INIT_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING 3:3
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_UUID_BASED_MEM_SHARING_TRUE (0x00000001U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED 4:4
#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_FALSE (0x00000000U)
#define NV0000_CTRL_SYSTEM_GET_FEATURES_RM_TEST_ONLY_CODE_ENABLED_TRUE (0x00000001U)
/*
* NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION
*
@@ -104,7 +109,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_FEATURES_PARAMS {
* NV_ERR_INVALID_PARAM_STRUCT
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_BUILD_VERSION (0x101U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_PARAMS_MESSAGE_ID (0x1U)
@@ -412,6 +417,28 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
/*
* NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT
*
* This command returns whether the VRR cookie is present in the SBIOS.
*
* bIsPresent (out)
* This parameter contains whether the VRR cookie is present in the SBIOS.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_REQUEST
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT (0x107U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS_MESSAGE_ID (0x7U)
typedef struct NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS {
NvBool bIsPresent;
} NV0000_CTRL_SYSTEM_GET_VRR_COOKIE_PRESENT_PARAMS;
/*
* NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES
*
@@ -439,7 +466,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CHIPSET_INFO_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_CMD_SYSTEM_GET_LOCK_TIMES (0x109U) /* finn: Evaluated from "(FINN_NV01_ROOT_SYSTEM_INTERFACE_ID << 8) | NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID" */
#define NV0000_CTRL_SYSTEM_GET_LOCK_TIMES_PARAMS_MESSAGE_ID (0x9U)
@@ -2086,40 +2113,82 @@ typedef struct NV0000_CTRL_SYSTEM_GET_RM_INSTANCE_ID_PARAMS {
typedef struct NV0000_CTRL_CMD_SYSTEM_NVPCF_GET_POWER_MODE_INFO_PARAMS {
/* GPU ID */
NvU32 gpuId;
NvU32 gpuId;
/* Total processing power including CPU and GPU */
NvU32 tpp;
NvU32 tpp;
/* Rated total GPU Power */
NvU32 ratedTgp;
NvU32 ratedTgp;
/* NVPCF subfunction id */
NvU32 subFunc;
NvU32 subFunc;
/* Configurable TGP offset, in mW */
NvS32 ctgpOffsetmW;
NvS32 ctgpOffsetmW;
/* TPP, as offset in mW */
NvS32 targetTppOffsetmW;
NvS32 targetTppOffsetmW;
/* Maximum allowed output, as offset in mW */
NvS32 maxOutputOffsetmW;
NvS32 maxOutputOffsetmW;
/* Minimum allowed output, as offset in mW */
NvS32 minOutputOffsetmW;
NvS32 minOutputOffsetmW;
/* Configurable TGP offset, on battery, in milli-Watts. */
NvS32 ctgpBattOffsetmW;
/* Target total processing power on battery, offset, in milli-Watts. */
NvS32 targetTppBattOffsetmW;
/*
* If value specified is larger than the statically assigned ROS reserve in
* the system power limits table, this will take affect.
*
* A value of zero naturally works as a clear as it will be lesser than the
* statically assigned value.
*/
NvU32 dcRosReserveOverridemW;
/*
* This is the active arbitrated long timescale limit provided by Qboost and
* honored by JPAC/JPPC
*/
NvU32 dcTspLongTimescaleLimitmA;
/*
* This is the active arbitrated short timescale limit provided by Qboost and
* honored by RM/PMU
*/
NvU32 dcTspShortTimescaleLimitmA;
/* Require DB on DC to use system power limits table */
NvBool bRequireDcSysPowerLimitsTable;
/* Dynamic params can override ROS reserve used in DB-DC */
NvBool bAllowDcRestOfSystemReserveOverride;
/* Is DC-TSP supported? */
NvBool bSupportDcTsp;
/* Dynamic Boost AC support */
NvBool bEnableForAC;
/* Dynamic Boost DC support */
NvBool bEnableForDC;
/* The System Controller Table Version */
NvU8 version;
NvU8 version;
/* Base sampling period */
NvU16 samplingPeriodmS;
NvU16 samplingPeriodmS;
/* Sampling Multiplier */
NvU16 samplingMulti;
NvU16 samplingMulti;
/* Fitler function type */
NvU8 filterType;
NvU8 filterType;
union {
@@ -2240,6 +2309,8 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS {
* This field returns the version (NV_VERSION_STRING).
* versionBuffer
* This field returns the version (NV_BUILD_BRANCH_VERSION).
* driverBranch
* This field returns the branch (NV_BUILD_BRANCH).
* titleBuffer
* This field returns the title (NV_DISPLAY_DRIVER_TITLE).
* changelistNumber
@@ -2260,6 +2331,7 @@ typedef struct NV0000_CTRL_SYSTEM_GET_CLIENT_DATABASE_INFO_PARAMS {
typedef struct NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_PARAMS {
char driverVersionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
char versionBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
char driverBranch[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
char titleBuffer[NV0000_CTRL_SYSTEM_GET_BUILD_VERSION_V2_MAX_STRING_SIZE];
NvU32 changelistNumber;
NvU32 officialChangelistNumber;

24
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dfp.h
View File

@@ -107,8 +107,6 @@
* This indicates whether this SOR uses DSI-A, DSI-B or both (ganged mode).
* NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE
* This indicates whether this DFP supports DDS (NV dynamic display mux).
* NV0073_CTRL_DFP_FLAGS_MDM
* This indicates whether this DFP supports MDM (Microsoft dynamic display mux).
* UHBRSupportedByDfp
* Bitmask to specify the UHBR link rates supported by this dfp.
*
@@ -196,9 +194,6 @@ typedef struct NV0073_CTRL_DFP_GET_INFO_PARAMS {
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE 30:30
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_FALSE (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_DYNAMIC_MUX_CAPABLE_TRUE (0x00000001U)
#define NV0073_CTRL_DFP_FLAGS_MDM 31:31
#define NV0073_CTRL_DFP_FLAGS_MDM_DISABLED (0x00000000U)
#define NV0073_CTRL_DFP_FLAGS_MDM_ENABLED (0x00000001U)
@@ -471,7 +466,6 @@ typedef struct NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS {
} NV0073_CTRL_DFP_SET_AUDIO_ENABLE_PARAMS;
/*
* NV0073_CTRL_DFP_ASSIGN_SOR_LINKCONFIG
*
@@ -1306,16 +1300,16 @@ typedef struct NV0073_CTRL_DFP_GET_FIXED_MODE_TIMING_PARAMS {
* hwOkToGateLatencyUs
* Duration in microseconds that HW took to assert ok_to_gate.
* Only valid when displayId is not equal to 0xFFFFFFFF
* jadeApiLatencyUs
* Duration in microseconds that Jade took to service 'Enter
* Display Power Gating' command
* carApiLatencyUs
* Duration in microseconds that CAR (Clock and Reset) block took to
* service 'Enter Display Power Gating' command
*
*/
typedef struct NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA {
NvU32 totalRmEntryLatencyUs;
NvU32 hwOkToGateLatencyUs;
NvU32 jadeEntryApiLatencyUs;
NvU32 carEntryApiLatencyUs;
} NV0073_CTRL_DFP_ENTER_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA;
/*
@@ -1376,15 +1370,15 @@ typedef struct NV0073_CTRL_CMD_DFP_ENTER_DISPLAY_POWER_GATING_PARAMS {
* sequence including the below parameters.
* riscvBootupLatencyUs
* Duration in microseconds that LTM RISCV took to bootup.
* jadeExitApiLatencyUs
* Duration in microseconds that Jade took to service 'Exit
* Display Power Gating' command
* carExitApiLatencyUs
* Duration in microseconds that CAR (Clock and Reset) block took
* to service 'Exit Display Power Gating' command
*
*/
typedef struct NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA {
NvU32 totalRmExitLatencyUs;
NvU32 riscvBootupLatencyUs;
NvU32 jadeExitApiLatencyUs;
NvU32 carExitApiLatencyUs;
} NV0073_CTRL_DFP_EXIT_DISPLAY_POWER_GATING_DIAGNOSTIC_DATA;
/*
@@ -1455,4 +1449,6 @@ typedef struct NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS {
NvU32 displayId;
} NV0073_CTRL_DFP_EDP_DRIVER_UNLOAD_PARAMS;
/* _ctrl0073dfp_h_ */

110
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -1102,61 +1102,6 @@ typedef struct NV0073_CTRL_DP_MAIN_LINK_CTRL_PARAMS {
#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERDOWN (0x00000000U)
#define NV0073_CTRL_DP_MAIN_LINK_CTRL_POWER_STATE_POWERUP (0x00000001U)
/*
* NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM
*
* This command returns the current audio mute state on the main link of Display Port
*
* The command takes a NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS structure as the
* argument with the appropriate subDeviceInstance, displayId as inputs and returns the
* current mute status in mute field of the structure.
*
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the display for which the audio stream
* state should be returned. The display ID must a DP display.
* If the display ID is invalid or if it is not a DP display,
* this call will return NV_ERR_INVALID_ARGUMENT.
* mute
* This parameter will return one of the following values:
* NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE
* Audio mute is currently disabled.
* NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE
* Audio mute is currently enabled.
* NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO
* Audio mute is automatically controlled by hardware.
* NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN
* Audio mute is currently in an unknown state.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*
*/
#define NV0073_CTRL_CMD_DP_GET_AUDIO_MUTESTREAM (0x731358U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 mute;
} NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS;
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U)
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE (0x00000001U)
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO (0x00000002U)
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_UNKNOWN (0x00000003U)
/*
* NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM
*
@@ -1197,7 +1142,7 @@ typedef struct NV0073_CTRL_DP_GET_AUDIO_MUTESTREAM_PARAMS {
*
*
*/
#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_SET_AUDIO_MUTESTREAM (0x731359U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS_MESSAGE_ID (0x59U)
@@ -1207,6 +1152,10 @@ typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS {
NvU32 mute;
} NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS;
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_DISABLE (0x00000000U)
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_ENABLE (0x00000001U)
#define NV0073_CTRL_DP_AUDIO_MUTESTREAM_MUTE_AUTO (0x00000002U)
/*
* NV0073_CTRL_CMD_DP_ASSR_CTRL
*
@@ -1271,7 +1220,7 @@ typedef struct NV0073_CTRL_DP_SET_AUDIO_MUTESTREAM_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_DP_ASSR_CTRL (0x73135aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_ASSR_CTRL_PARAMS_MESSAGE_ID (0x5AU)
@@ -1390,8 +1339,6 @@ typedef struct NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS {
NvU32 displayId;
} NV0073_CTRL_CMD_DP_TOPOLOGY_FREE_DISPLAYID_PARAMS;
/*
* NV0073_CTRL_CMD_DP_GET_LINK_CONFIG
*
@@ -1459,9 +1406,7 @@ typedef struct NV0073_CTRL_DP_GET_LINK_CONFIG_PARAMS {
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_3_24GBPS (0x00000114U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_4_32GBPS (0x000001B0U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_6_75GBPS (0x000002A3U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_10_0GBPS (0x000003E8U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_13_5GBPS (0x00000546U)
#define NV0073_CTRL_CMD_DP_GET_LINK_CONFIG_DP2LINK_BW_20_0GBPS (0x000007D0U)
/*
* NV0073_CTRL_CMD_DP_GET_EDP_DATA
@@ -2780,47 +2725,6 @@ typedef struct NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS {
NV0073_CTRL_DP_MSA_PROPERTIES_VALUES featureDebugValues;
} NV0073_CTRL_CMD_DP_SET_MSA_PROPERTIES_V2_PARAMS;
/*
* NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY
*
* This command is used to execute RM Over Drive policy and decide if TCON Overdrive needs to be enabled
* or not based on the panel Overdrive grade determined using the panel manufId and prodId.
*
* subDeviceInstance [in]
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId [in]
* This parameter specifies the ID of the eDP display which owns
* the Main Link to be adjusted. The display ID must a eDP display
* as determined with the NV0073_CTRL_CMD_SPECIFIC_GET_TYPE command.
* If more than one displayId bit is set or the displayId is not an eDP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* manfId [in]
* This parameter is an input to this command which tells the
* Internal panel's manufacturer ID.
* prodId [in]
* This parameter is an input to this command which tells the
* Internal panel's product ID.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_DP_EXECUTE_OVERDRIVE_POLICY (0x731382U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU16 manfId;
NvU16 prodId;
} NV0073_CTRL_DP_EXECUTE_OVERDRIVE_POLICY_PARAMS;
/*

10
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
View File

@@ -62,15 +62,9 @@ typedef NV0073_CTRL_CMD_DFP_GET_DISP_MUX_STATUS_PARAMS NV0073_CTRL_CMD_INTERNAL_
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE (0x730406U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730406U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID (0x6U)
typedef NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS NV0073_CTRL_CMD_INTERNAL_VBLANK_SEM_CONTROL_DISABLE_PARAMS;
#define NV0073_CTRL_CMD_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR (0x730407U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_INTERNAL_INTERFACE_ID << 8) | NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x7U)
#define NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS_MESSAGE_ID (0x6U)
typedef NV0073_CTRL_SYSTEM_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS NV0073_CTRL_INTERNAL_INLINE_DISP_INTR_SERVICE_WAR_FOR_VR_PARAMS;

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073stereo.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

2
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
View File

@@ -1009,8 +1009,6 @@ typedef struct NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS {
NvU32 bootDisplayMask;
} NV0073_CTRL_SYSTEM_GET_BOOT_DISPLAYS_PARAMS;
/*
* NV0073_CTRL_CMD_SYSTEM_EXECUTE_ACPI_METHOD
*

1
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080fb.h
View File

@@ -92,6 +92,7 @@ typedef struct NV0080_CTRL_FB_GET_CAPS_PARAMS {
#define NV0080_CTRL_FB_CAPS_VIDMEM_ALLOCS_ARE_CLEARED 2:0x02
#define NV0080_CTRL_FB_CAPS_DISABLE_PLC_GLOBALLY 2:0x04
#define NV0080_CTRL_FB_CAPS_PLC_BUG_3046774 2:0x08
#define NV0080_CTRL_FB_CAPS_PARTIAL_UNMAP 2:0x10
/* size in bytes of fb caps table */

2
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2004-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2004-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

24
src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080host.h
View File

@@ -70,32 +70,8 @@ typedef struct NV0080_CTRL_HOST_GET_CAPS_PARAMS {
#define NV0080_CTRL_HOST_GET_CAP(tbl,c) (((NvU8)tbl[(1?c)]) & (0?c))
/* caps format is byte_index:bit_mask */
#define NV0080_CTRL_HOST_CAPS_SEMA_ACQUIRE_BUG_105665 0:0x01
#define NV0080_CTRL_HOST_CAPS_DUP_CMPLT_BUG_126020 0:0x02
/*
* This bit indicates whether CPU mappings obtained with NvRmMapMemory() are
* coherent with the GPU. When this bit is _not_ set, all mappings are to the
* "raw" memory; i.e., they behave as it the NVOS33_FLAGS_MAPPING_DIRECT flag
* were used on a sysmem mapping.
*/
#define NV0080_CTRL_HOST_CAPS_GPU_COHERENT_MAPPING_SUPPORTED 0:0x04
#define NV0080_CTRL_HOST_CAPS_SYS_SEMA_DEADLOCK_BUG_148216 0:0x08
#define NV0080_CTRL_HOST_CAPS_SLOWSLI 0:0x10
#define NV0080_CTRL_HOST_CAPS_SEMA_READ_ONLY_BUG 0:0x20
#define NV0080_CTRL_HOST_CAPS_LARGE_NONCOH_UPSTR_WRITE_BUG_114871 0:0x40
#define NV0080_CTRL_HOST_CAPS_LARGE_UPSTREAM_WRITE_BUG_115115 0:0x80
#define NV0080_CTRL_HOST_CAPS_SEP_VIDMEM_PB_NOTIFIERS_BUG_83923 1:0x02
#define NV0080_CTRL_HOST_CAPS_P2P_4_WAY 1:0x08 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_8_WAY 1:0x10 // Deprecated
#define NV0080_CTRL_HOST_CAPS_P2P_DEADLOCK_BUG_203825 1:0x20 // Deprecated
#define NV0080_CTRL_HOST_CAPS_BUG_254580 1:0x80
#define NV0080_CTRL_HOST_CAPS_COMPRESSED_BL_P2P_BUG_257072 2:0x02 // Deprecated
#define NV0080_CTRL_HOST_CAPS_CROSS_BLITS_BUG_270260 2:0x04 // Deprecated
/* unused 2:0x08 */
#define NV0080_CTRL_HOST_CAPS_MEM2MEM_BUG_365782 2:0x10
#define NV0080_CTRL_HOST_CAPS_CPU_WRITE_WAR_BUG_420495 2:0x20
#define NV0080_CTRL_HOST_CAPS_EXPLICIT_CACHE_FLUSH_REQD 2:0x40
#define NV0080_CTRL_HOST_CAPS_BAR1_READ_DEADLOCK_BUG_511418 2:0x80 // Deprecated
/* size in bytes of host caps table */
#define NV0080_CTRL_HOST_CAPS_TBL_SIZE 3

101
src/common/sdk/nvidia/inc/ctrl/ctrl00da.h
View File

@@ -71,42 +71,101 @@ typedef struct NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS {
NvHandle hMaxSubmittedMem;
} NV_SEMAPHORE_SURFACE_CTRL_REF_MEMORY_PARAMS;
/*
* Currently no known usages that require more than two indices per channel:
*
* 1) The channel's associated backend engine's TRAP interrupt.
* 2) The frontend/GPFIFO's non-stall interrupt.
*
* The remaining slots are for futureproofing purposes only.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES 8
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL
* Associates a channel with the semaphore surface. All channels which will
* wait on or signal semaphores in a semaphore surface should first register
* with it to ensure proper event delivery and error handling.
*
* engineMask is a bitfield whose contents should be defined by setting bit
* index <n> to '1' if the corresponding engine index will be used. See
* cl2080.h for a list of engine indices. For example, this would indicate
* a channel making use of the engines GR0(graphics/compute), COPY0-COPY9,
* and host:
* numNotifyIndices is the number of valid entries in notifyIndices.
*
* NvU64 engineMask = (1ULL << NV2080_ENGINE_TYPE_GR0) |
* (1ULL << NV2080_ENGINE_TYPE_COPY0) |
* (1ULL << NV2080_ENGINE_TYPE_COPY1) |
* (1ULL << NV2080_ENGINE_TYPE_COPY2) |
* (1ULL << NV2080_ENGINE_TYPE_COPY3) |
* (1ULL << NV2080_ENGINE_TYPE_COPY4) |
* (1ULL << NV2080_ENGINE_TYPE_COPY5) |
* (1ULL << NV2080_ENGINE_TYPE_COPY6) |
* (1ULL << NV2080_ENGINE_TYPE_COPY7) |
* (1ULL << NV2080_ENGINE_TYPE_COPY8) |
* (1ULL << NV2080_ENGINE_TYPE_COPY9) |
* (1ULL << NV2080_ENGINE_TYPE_HOST);
* notifyIndices is an array of notifier indices corresponding to the engines
* the caller may use to signal a semaphore in the semaphore surface. See
* cl2080_notifiers.h for a list of notifier indices. For example, this would
* indicate a channel using the GR0(graphics/compute) and FIFO TRAP method
* (GPFIFO) notifiers to signal semaphores.
*
* params.hChannel = myChannelHandle;
* params.numNotifyIndices = 2;
* params.notifyIndex[0] = NV2080_NOTIFIERS_GR0;
* params.notifyIndex[1] = NV2080_NOTIFIERS_FIFO_EVENT_MTHD;
*
* If the specified channel will only be used to wait for semaphores, set
* numNotifyIndices to 0.
*
* RETURNS:
* NVOS_STATUS_SUCCESS if the channel and notification indices were
* successfully bound.
* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE if hChannel does not refer an object
* in the client.
* NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR if hChannel does not refer to a valid
* channel object.
* NVOS_STATUS_ERROR_INVALID_PARAMETER if numNotifyIndices is greater than
* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES.
* NVOS_STATUS_ERROR_NOT_SUPPORTED if the notifyIndex is not a valid
* notification index.
* NVOS_STATUS_ERROR_INVALID_STATE if an internal inconsistency is found in the
* binding tracking logic.
* NV_ERR_NO_MEMORY if memory could not be allocated for internal tracking
* structures.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL (0xda0002) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS_MESSAGE_ID (0x02U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS {
NvHandle hClient;
NvHandle hDevice;
NvHandle hChannel;
NV_DECLARE_ALIGNED(NvU64 engineMask, 8);
NvU32 numNotifyIndices;
NvU32 notifyIndices[NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES];
} NV_SEMAPHORE_SURFACE_CTRL_BIND_CHANNEL_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_UNBIND_CHANNEL
* Dissociate a channel and a semaphore surface. Before freeing a channel
* object, it should be dissociated from all semaphore surfaces to which it has
* been bound.
*
* hChannel is a valid channel object handle which has previously been bound
* to the semaphore surface.
*
* numNotifyIndices is the number of valid entries in the notifyIndices array.
* the hChannel handle.
*
* notifyIndices is the array of notifier indices that was bound to the
* semaphore surface with the hChannel handle.
* RETURNS:
* NVOS_STATUS_SUCCESS if the channel and notification indices were
* successfully unbound.
* NVOS_STATUS_ERROR_INVALID_OBJECT_HANDLE if hChannel does not refer an object
* in the client.
* NVOS_STATUS_ERROR_INVALID_OBJECT_ERROR if hChannel does not refer to a valid
* channel object.
* NVOS_STATUS_ERROR_INVALID_PARAMETER if numNotifyIndices is greater than
* NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES.
* NVOS_STATUS_ERROR_INVALID_STATE if no binding associated with the specified
* channel and notification indices is found.
*/
#define NV_SEMAPHORE_SURFACE_CTRL_CMD_UNBIND_CHANNEL (0xda0006) /* finn: Evaluated from "(FINN_NV_SEMAPHORE_SURFACE_INTERFACE_ID << 8) | NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS_MESSAGE_ID" */
#define NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS_MESSAGE_ID (0x06U)
typedef struct NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS {
NvHandle hChannel;
NvU32 numNotifyIndices;
NvU32 notifyIndices[NV_SEMAPHORE_SURFACE_CTRL_CMD_BIND_CHANNEL_MAX_INDICES];
} NV_SEMAPHORE_SURFACE_CTRL_UNBIND_CHANNEL_PARAMS;
/*
* NV_SEMAPHORE_SURFACE_CTRL_CMD_REGISTER_WAITER
* Ask RM to signal the specified OS event and/or set the semaphore to a new

118
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bus.h
View File

@@ -1182,10 +1182,19 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS
*
* This command returns the PCIe requester atomics operation capabilities
* from GPU to coherent SYSMEM.
* of the GPU with regards to the aspect of support the client is asking for.
*
*
* capType [IN]
* The aspect of the atomics support the client is querying atomics capability for.
* Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
*
* dbdf [IN] -
* Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
* Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
*
* atomicsCaps[OUT]
* Mask of supported PCIe atomic operations in the form of
* Mask of supported PCIe requester atomic operations in the form of
* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_*
*
* Possible status values returned are:
@@ -1198,9 +1207,26 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U)
typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
NvU32 capType;
NvU32 dbdf;
NvU32 atomicsCaps;
} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS;
/*
* Defined methods to expose atomics capability.
*
* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM
* Exposes the state of atomics support between GPU and Sysmem.
* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU
* Exposes the state of the GPU atomics support without taking into account PCIe topology.
* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P
* Exposes the state of atomics support between the source (this GPU)
* and peer GPU identified by the dbdf argument.
*/
#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM 0x0
#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU 0x1
#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P 0x2
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000)
@@ -1230,19 +1256,19 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
* that map to the capable PCIe atomic operations from GPU to
* coherent SYSMEM.
*
* capType [IN]
* The aspect of the atomics support the client is querying atomics capability for.
* Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
*
* dbdf [IN] -
* Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
* Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
*
* atomicOp[OUT]
* Array of structure that contains the atomic operation
* Array of NV2080_CTRL_BUS_PCIE_GPU_ATOMICS that contains the atomic operation
* supported status and its attributes. The array can be
* indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_*
*
* bSupported[OUT]
* Is the GPU atomic operation natively supported by the PCIe?
*
* attributes[OUT]
* Provides the attributes mask of the GPU atomic operation when supported
* in the form of
* NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_*
*
*/
#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */
@@ -1262,13 +1288,30 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13
/*
* NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
*
* Describes the support state and related attributes of a single GPU atomic op.
*
* bSupported
* Is the GPU atomic operation natively supported by the PCIe
*
* attributes
* Provides the attributes mask of the GPU atomic operation when supported
* in the form of
* NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_*
*/
typedef struct NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO {
NvBool bSupported;
NvU32 attributes;
} NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO;
#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU)
typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
struct {
NvBool bSupported;
NvU32 attributes;
} atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
NvU32 capType;
NvU32 dbdf;
NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS;
#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0
@@ -1464,3 +1507,48 @@ typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS {
NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS;
/*
* NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS
*
* This command returns the PCIe completer atomics operation capabilities
* of the GPU.
*
* atomicsCaps[OUT]
* Mask of supported PCIe completer atomic operations in the form of
* NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_*
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS (0x20801830) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x30U)
typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
NvU32 atomicsCaps;
} NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS;
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 0:0
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 1:1
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 2:2
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 3:3
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 4:4
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 5:5
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO (0x00000000)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 6:6
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001)
#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000)

161
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080ce.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -99,6 +99,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04
#define NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED 1:0x08
/*
* NV2080_CTRL_CE_CAPS_CE_GRCE
@@ -135,6 +136,10 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
*
* NV2080_CTRL_CE_CAPS_CE_CC_SECURE
* Set if the CE is capable of encryption/decryption
*
* NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED
* Set if the CE is capable of handling decompression workloads;
* async copies will not be supported on the same CE
*/
/*
@@ -154,6 +159,10 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
* NV_ERR_INVALID_ARGUMENT
*/
/*
* The pceMask is local to the CE shim that ceEngineType belongs to.
*/
#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
@@ -228,6 +237,15 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
* NV_ERR_GENERIC
*/
/*
* This command updates the PCE-LCE mappings for one CE shim. On
* GPUs with multiple CE shims, this interface must be called for
* each shim.
*
* shimInstance [IN]
* Specify which CE shim instance to operate on.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
@@ -254,6 +272,10 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
* set in stubbedCeMask.
*/
/*
* This function operates on all CE shims.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
@@ -339,5 +361,142 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO
*
* This command queries LCE shim information of a specified CE.
* The information includes the shim instance the CE belongs to.
* And the local LCE within the shim.
*
* [in] ceEngineType
* This parameter specifies the copy engine type, NV2080 define
* [out] shimInstance
* The shim instance the ceEngineType belongs to.
* [out] shimLocalLceIdx
* The local LCE index within the shim
*
*/
#define NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO (0x20802a0c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID (0xcU)
typedef struct NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS {
NvU32 ceEngineType;
NvU32 shimInstance;
NvU32 shimLocalLceIdx;
} NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS;
/*
* This command is identical to NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
* but supports more than one CE shim.
*
* This command updates the PCE-LCE mappings for one CE shim. On
* GPUs with multiple CE shims, this interface must be called for
* each shim.
*
* shimInstance [IN]
* Specify which CE shim instance to operate on.
*/
#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 (0x20802a0d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID (0xdU)
typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS {
NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
NvU32 grceConfig[NV2080_CTRL_MAX_GRCES];
NvU32 exposeCeMask;
NvBool bUpdateNvlinkPceLce;
NvU32 shimInstance;
} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS;
/*
* This command is identical to NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_PARAMS
* but supports more than one CE shim.
*
* This command gets HSHUB/CEHUB and FBHUB PCE Mask. On
* GPUs with multiple CE shims, this interface must be called for
* each shim.
*
* [in] shimInstance
* Specify which CE shim instance to operate on.
*/
#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 (0x20802a0e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID (0xeU)
typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS {
NvU32 connectingHubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
NvU32 fbhubPceMask;
NvU32 shimInstance;
} NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS;
typedef enum NV2080_CTRL_CE_LCE_TYPE {
NV2080_CTRL_CE_LCE_TYPE_PCIE = 1,
NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2,
NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3,
NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4,
NV2080_CTRL_CE_LCE_TYPE_C2C = 5,
} NV2080_CTRL_CE_LCE_TYPE;
/*
* NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE
*
* This command queries the PCE config required for the specified LCE type.
*
* [in] lceType
* LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
* [out] numPces
* Number of PCEs supported per LCE
* [out] numLces
* Maximum number of LCEs supported by the chip for the specified LCE type.
* [out] supportedPceMask
* The mask of the PCEs that support the specified LCE type.
* [out] supportedLceMask
* The mask of the LCEs that support the specified LCE type.
* [out] pcePerHshub
* Numbers of PCEs from any given HSHUB that can be assigned to this LCE type.
*
* @return NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE (0x20802a0f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID (0xfU)
typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
NV2080_CTRL_CE_LCE_TYPE lceType;
NvU32 numPces;
NvU32 numLces;
NvU32 supportedPceMask;
NvU32 supportedLceMask;
NvU32 pcePerHshub;
} NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS;
/*
* NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK
*
* This command gets the mask of LCEs that are enabled for decomp workloads.
* On GPUs with multiple CE shims, this interface must be called for
* each shim.
*
* [in] shimInstance
* Specify which CE shim instance to operate on.
* [out] decompLceMask
* Returns a 64-bit mask of which LCEs in given shim are marked as decomp CEs
*/
#define NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK (0x20802a11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID (0x11U)
typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS {
NV_DECLARE_ALIGNED(NvU64 decompLceMask, 8);
NvU32 shimInstance;
} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS;
/* _ctrl2080ce_h_ */

34
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -156,11 +156,35 @@
* NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW
* This index is deprecated, and returns zero value.
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1
* This index is used to request the mask of currently active partitions.
* Each active partition has an ID that's equivalent to the corresponding
* Each active partition has an ID that's equivalent to the corresponding
* bit position in the mask.
* This an SMC aware attribute, thus necessary partition subscription is
* required if the device is partitioned.
* This value is moving from 32bits to 64bits, so PARTITION_MASK
* (though kept for backwards compatibility on older chips), on newer chips
* will be replaced by:
* PARTITION_MASK_0 for the lower 32bits
* PARTITION_MASK_1 for the upper 32bits
* Note that PARTITION_MASK and PARTITION_MASK_0 are handled the same, and
* use the same enum value.
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1
* This index is used to request the mask of currently active LTCs.
* Each active LTC has an ID that's equivalent to the corresponding
* bit position in the mask.
* This an SMC aware attribute, thus necessary partition subscription is
* required if the device is partitioned.
* This value is moving from 32bits to 64bits, so LTC_MASK
* (though kept for backwards compatibility on older chips), on newer chips
* will be replaced by:
* LTC_MASK_0 for the lower 32bits
* LTC_MASK_1 for the upper 32bits
* Note that LTC_MASK and LTC_MASK_0 are handled the same, and
* use the same enum value.
* NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE
* This index is used to request the amount of total RAM in kilobytes
* reserved for internal RM allocations on Vista. This will need to
@@ -332,9 +356,13 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 (0x00000037U)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U)
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000039U)
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x36U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x38U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
/* valid fb RAM type values */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)

28
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
View File

@@ -905,6 +905,34 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
*
* This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
* The difference is that it doesn't take a list of clients and instead all channels belong
* to the client on which this control call is made.
*
* numChannels
* The number of valid entries in hChannelList array.
* hChannelList
* An array of NvHandle listing the channel handles
* to be stopped.
* bEnableAfterKeyRotation
* This determines if channel is enabled by RM after it completes key rotation.
* Possible status values returned are:
* NV_OK
* NVOS_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
NvU32 numChannels;
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
NvBool bEnableAfterKeyRotation;
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
/*

36
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -115,6 +115,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
@@ -753,7 +755,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x54U
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
@@ -1126,7 +1128,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001EU)
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001FU)
@@ -4325,6 +4327,36 @@ typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS];
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
*
* This command will return the MSIX capabilities for virtual function
* Parameters:
*
* gfid [IN]
* The GPU function identifier for a given VF BDF
*
* vfMsixCap [out]
* This field returns the VF MSIX cap values
*
* Possible status values returned are:
* NV_OK
*/
typedef struct NV2080_VF_MSIX_CAPS {
NvU32 msix_header;
NvU32 msix_table;
NvU32 msix_pba;
} NV2080_VF_MSIX_CAPS;
#define NV2080_CTRL_CMD_GPU_GET_VF_CAPS (0x208001b1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID (0xB1U)
typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS {
NvU32 gfid;
NV2080_VF_MSIX_CAPS vfMsixCap;
} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS;
/*
* NV2080_CTRL_GPU_GET_FIPS_STATUS
*

10
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -310,6 +310,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */
@@ -328,6 +331,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
@@ -736,7 +742,7 @@ typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
*/
#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 144U
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 240U
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU)
typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {

76
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -748,6 +748,8 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
NvU32 rlEngId;
NvU32 runlistPriBase;
NvU32 groupId;
NvU32 ginTargetId;
NvU32 deviceBroadcastPriBase;
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
@@ -2633,6 +2635,8 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
* To indicate whether save or restore needs to be performed.
* [in] bUseVbios
* Primary VGA indication from OS.
* [out] bReturnEarly
* To indicate caller to return after this call.
*
* Possible status values returned are:
* NV_OK
@@ -2646,6 +2650,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS {
NvBool bSave;
NvBool bUseVbios;
NvBool bReturnEarly;
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS;
/*!
@@ -3574,11 +3579,15 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
*
* bwMode[IN]
* - Nvlink Bandwidth mode
*
* bLocalEgmEnabled[IN]
* - EGM Enablement Status that needs to be set in GSP-RM
*/
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
NvU8 bwMode;
NvU8 bwMode;
NvBool bLocalEgmEnabled;
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
/*!
@@ -3677,7 +3686,8 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
@@ -3804,22 +3814,6 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
*
* This command is an internal command sent from Kernel RM to Physical RM
* to update the logical Uproc Id for the configuration.
*
* logicalUprocId [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
NvU8 logicalUprocId;
} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
*
@@ -4107,7 +4101,16 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
NvBool bInPMTransition;
NvU32 newPMLevel;
} NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS;
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_RECOVERY
*
* This command is used to perform recovery actions after the fabric has been
* idled due to a fatal nvlink error.
* This command accepts no parameters.
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xEA" */
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
@@ -4124,4 +4127,39 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS {
NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8);
} NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM
*
* This command sets a new value for the specified Illumination control attribute.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0xECU)
typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
NvU32 attribute;
NvU32 value;
} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM
*
* Returns the maximum number of HSHUBs in a shim instance.
*
* maxHshubs[OUT]
* The maximum number of HSHUBs in a shim instance.
*
* @return NV_OK
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U)
typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS {
NvU32 maxHshubs;
} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS;
/* ctrl2080internal_h */

46
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvd.h
View File

@@ -214,41 +214,41 @@ typedef struct NV2080_NOCAT_JOURNAL_RECORD {
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 9
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX 5
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 6
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 7
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 8
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 9
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 10
// Journal Lock activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 10
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 12
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 11
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 12
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 13
// lookup activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 13
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 14
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 15
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 16
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 17
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 18
// reporting activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 18
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 19
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 20
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 19
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 20
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 21
// update activity
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 21
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 22
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 23
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 22
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 23
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 24
// general errors
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 24
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 25
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 26
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 25
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 26
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 27
// reserved entries for temporary use.
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES5_IDX 27
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30

910
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -136,6 +136,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
@@ -145,6 +147,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 (0x00000008U)
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
@@ -374,6 +378,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
@@ -384,6 +390,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 (0x00000008U)
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
@@ -866,6 +874,118 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
#define NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER NV2080_CTRL_NVLINK_COUNTER_LP_DL
/* Transmit Counters */
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS 22U
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES 23U
/* Received Counters */
#define NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS 24U
#define NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES 25U
/* Link Events */
#define NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER 26U
#define NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER 27U
#define NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER 28U
/* Link Receive Errors */
#define NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS 29U
#define NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS 30U
#define NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS 31U
/* Link Receive Errors Detail */
#define NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR 32U
#define NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR 33U
#define NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR 34U
/* Link Other Errors Detail */
#define NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS 35U
#define NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS 36U
/* Link Transmit Errors */
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME 37U
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS 38U
/* FEC Block Counters */
#define NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS 39U
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS 40U
#define NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS 41U
/* FEC Symbol Counters */
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 42U
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 43U
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL 44U
/* FEC Raw Error Counters */
#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 45U
#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 46U
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS 47U
/* FEC Raw BER */
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 48U
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 49U
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL 50U
/* FEC Effective BER */
#define NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS 51U
#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS 52U
#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER 53U
/* Phy Symbol Errors Counters */
#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS 54U
#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER 55U
#define NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS 56U
/* Phy Other Errors Counters */
#define NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS 57U
#define NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR 58U
/* PLR Receive Counters */
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS 59U
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS 60U
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS 61U
/* PLR Transmit Counters */
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS 62U
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS 63U
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS 64U
/* PLR BW Loss Counters */
#define NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS 65U
/* NVLE Rx counters */
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD 66U
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR 67U
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH 68U
/* NVLE Tx Counters */
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD 69U
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR 70U
/* FEC Histogram */
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 71U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 72U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 73U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 74U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 75U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 76U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 77U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 78U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 79U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 80U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 81U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 82U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 83U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 84U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 85U
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 86U
/* Throughput counters */
#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA 87U
#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA 88U
#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW 89U
#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW 90U
/* Low power counters */
#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY 91U
#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE 92U
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT 93U
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL 94U
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE 95U
#define NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME 96U
#define NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME 97U
#define NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME 98U
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME 99U
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME 100U
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME 101U
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME 102U
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME 103U
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME 104U
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME 105U
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME 106U
#define NV2080_CTRL_NVLINK_COUNTERS_MAX 107U
#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U
@@ -945,14 +1065,145 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS;
/* NVLINK unit list - to be used with error notifiers */
#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U
#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U
#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U
#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U
#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
/*
* NV2080_CTRL_NVLINK_ERROR_INJECT_CFG
*
* [in] errType
* This parameter specifies the type of error injection settings
* [in] errSettings
* This parameter specifies the settings for the error type in NVL5
*/
typedef enum NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE {
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1,
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2,
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3,
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4,
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5,
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE;
typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE errType;
NV_DECLARE_ALIGNED(NvU64 errSettings, 8);
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG;
/*
* Tx error type settings
*/
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE 31:28
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER 0x00000001U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER 0x00000002U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION 27:12 // Error Injection Duration, in 10ms units.
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA 11:8
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT 7:0
/*
* Packet error type settings
*/
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT 15:0
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP 16:16
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN 0x00000001U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON 17:17
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN 0x00000001U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS 18:18
/*
* Authentication error type settings
*/
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX 3:0
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR 4:4
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN 0x00000001U
/*
* Link Error type settings
*/
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN 0:0
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN 0x00000001U
/*
* NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT
* This command causes all the same actions to occur as if the related
* error were to occur, either fatal or recoverable.
*
* [in] linkMask size: 64 bits
* Mask of the links to be configured.
* [in] errCfg
* This parameter specifies that the error configurations.
*/
#define NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x81U)
typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE 1:0
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST 0x00000001U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR 0x00000002U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS 0:0
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT 0x00000000U
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT 0x00000001U
/*
* NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
*
* [out] txErrInfo
* This info specifies the settings for Tx errs in NVL5
* [out] packetErrSettings
* This info specifies the settings for Pkt errs in NVL5
* [out] authErrSettings
* This info specifies the settings for NVLE errs in NVL5
* [out] linkStatus
* This specifies the status of the link in NVL5
* [out] errInjectStatus
* This specifies the status of error injection
*/
typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
NvU32 txErrInfo;
NvU32 packetErrInfo;
NvU32 authErrInfo;
NvU32 linkStatus;
NvU32 errInjectStatus;
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO;
/*
* NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT
* This command get all the current nvlink error config
*
* [in] linkMask size: 64 bits
* Mask of the links to be configured.
* [in] errCfg
* This parameter specifies that the error configurations.
*/
#define NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
@@ -3233,6 +3484,34 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U
typedef struct NV2080_CTRL_NVLINK_PRM_DATA {
NvU8 data[NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH];
} NV2080_CTRL_NVLINK_PRM_DATA;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS (0x20803047U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID (0x47U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 admin_status;
NvU8 lp_msb;
NvU8 local_port;
NvU8 swid;
NvU8 e;
NvU8 fd;
NvU8 ps_e;
NvU8 ls_e;
NvU8 ee_ps;
NvU8 ee_ls;
NvU8 ee;
NvU8 ase;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
/*!
@@ -3246,6 +3525,621 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC (0x20803053U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID (0x53U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 lane_mask;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 local_tx_precoding_admin;
NvU8 local_rx_precoding_admin;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM (0x20803054U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID (0x54U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool test_mode;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 fec_override_admin_10g_40g;
NvU8 fec_override_admin_25g;
NvU8 fec_override_admin_50g;
NvU8 fec_override_admin_100g;
NvU8 fec_override_admin_56g;
NvU8 rs_fec_correction_bypass_admin;
NvU16 fec_override_admin_200g_4x;
NvU16 fec_override_admin_400g_8x;
NvU16 fec_override_admin_50g_1x;
NvU16 fec_override_admin_100g_2x;
NvU16 fec_override_admin_400g_4x;
NvU16 fec_override_admin_800g_8x;
NvU16 fec_override_admin_100g_1x;
NvU16 fec_override_admin_200g_2x;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC (0x20803055U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 lp_msb;
NvU8 local_port;
NvBool l1_req_en;
NvBool l1_fw_req_en;
NvBool l1_cap_adv;
NvBool l1_fw_cap_adv;
NvU32 hp_queues_bitmap;
NvU16 l1_hw_active_time;
NvU16 l1_hw_inactive_time;
NvU8 qem[8];
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM (0x20803056U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 access_reg_group;
NvU8 feature_group;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR (0x2080305cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID (0x5cU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTWE (0x2080305dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID (0x5dU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE (0x2080305eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID (0x5eU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE (0x2080305fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID (0x5fU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGCR (0x20803060U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID (0x60U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 segment;
NvU32 GPIO_set;
NvU32 GPIO_clear;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP (0x20803061U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID (0x61U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU (0x20803062U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID (0x62U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool itre;
NvU8 i_e;
NvU8 lp_msb;
NvU8 local_port;
NvU8 protocol;
NvU16 admin_mtu;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCIA (0x20803063U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID (0x63U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 slot_index;
NvU8 module;
NvBool pnv;
NvBool l;
NvU16 device_address;
NvU8 page_number;
NvU8 i2c_device_address;
NvU16 size;
NvU8 bank_number;
NvBool passwd_length;
NvU32 password;
NvU32 dword[32];
NvU32 password_msb;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP (0x20803064U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID (0x64U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 width;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 local_port;
NvBool m_lane_m;
NvBool rxtx;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT (0x20803065U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID (0x65U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 trap_id;
NvU8 action;
} NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR (0x20803066U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID (0x66U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 port_type;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 page_select;
NvU8 module_info_ext;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTMP (0x20803067U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID (0x67U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 sensor_index;
NvU8 slot_index;
NvU8 sdme;
NvU8 weme;
NvU8 mtr;
NvU8 mte;
NvU16 temperature_threshold_hi;
NvU8 sdee;
NvU8 tee;
NvU16 temperature_threshold_lo;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID (0x68U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool le;
NvU8 port_type;
NvU8 lane;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool sw;
NvBool dm_ig;
NvBool p;
NvBool e;
NvU8 modulation;
NvU8 prbs_mode_admin;
NvBool prbs_fec_admin;
NvU16 lane_rate_admin;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT (0x20803069U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID (0x69U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 grp;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 swid;
NvU8 prio_tc;
NvU8 grp_profile;
NvU8 plane_ind;
NvBool counters_cap;
NvBool lp_gl;
NvBool clr;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR (0x2080306aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID (0x6aU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS (0x2080306bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID (0x6bU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 port_type;
NvU8 phy_test_mode_admin;
NvU8 lp_msb;
NvU8 local_port;
NvU8 swid;
NvU8 plane_ind;
NvU8 phy_status_admin;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR (0x2080306cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID (0x6cU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvU8 hist_type;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP (0x2080306dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID (0x6dU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool c_db;
NvU8 port_type;
NvU8 lane_speed;
NvU8 lane;
NvBool tx_policy;
NvU8 pnat;
NvU8 local_port;
NvU8 lp_msb;
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID (0x2080306eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID (0x6eU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT (0x2080306fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID (0x6fU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool le;
NvU8 port_type;
NvU8 lane;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool sw;
NvBool dm_ig;
NvBool p;
NvBool tun_ovr;
NvBool s;
NvBool e;
NvU8 modulation;
NvU8 prbs_mode_admin;
NvU16 lane_rate_oper;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS (0x20803070U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID (0x70U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 proto_mask;
NvBool transmit_allowed;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 local_port;
NvU8 tx_ready_e;
NvBool ee_tx_ready;
NvBool an_disable_admin;
NvU32 ext_eth_proto_admin;
NvU32 eth_proto_admin;
NvU16 ib_proto_admin;
NvU16 ib_link_width_admin;
NvBool xdr_2x_slow_admin;
NvU8 force_lt_frames_admin;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG (0x20803071U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID (0x71U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 port_type;
NvU8 lane;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS (0x20803072U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID (0x72U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 admin_status;
NvU8 module;
NvU8 slot_index;
NvBool rst;
NvU8 e;
NvBool ee;
NvBool ase;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR (0x20803073U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID (0x73U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 port_type;
NvBool op_mod;
NvBool apply_im;
NvU8 lp_msb;
NvU8 local_port;
NvU16 lb_en;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID (0x74U)
typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
} NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD (0x20803075U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID (0x75U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 segment_type;
NvU8 seq_num;
NvBool vhca_id_valid;
NvBool inline_dump;
NvU16 vhca_id;
NvU32 index1;
NvU32 index2;
NvU16 num_of_obj2;
NvU16 num_of_obj1;
NV_DECLARE_ALIGNED(NvU64 device_opaque, 8);
NvU32 mkey;
NV_DECLARE_ALIGNED(NvU64 address, 8);
} NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP (0x20803076U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID (0x76U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool trace_owner;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF (0x20803077U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID (0x77U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 trace_mode;
NvU8 log_trace_buffer_size;
NvU8 trace_mkey;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL (0x20803078U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 modify_field_select;
NvBool arm_event;
NvU8 trace_status;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM (0x20803079U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID (0x79U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE (0x2080307aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID (0x7aU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 enable_all;
NvU8 log_delay;
NvU32 source_id_bitmask[8];
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM (0x2080307bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID (0x7bU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 log_level;
NvU32 log_bit_mask;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR (0x2080307cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID (0x7cU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 warning_inactive_time;
NvU8 warning_active_time;
NvU8 critical_inactive_time;
NvU8 critical_active_time;
NvBool cc;
NvU16 queue_depth_th;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID (0x7dU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS (0x2080307eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID (0x7eU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 lp_msb;
NvU8 local_port;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC (0x2080307fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID (0x7fU)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 lp_msb;
NvU8 local_port;
NvU8 cnt_64bit;
NvBool stop_at_ff;
NvBool counter_rst;
NvBool counter_en;
NvU8 force_count_mask;
NvU8 cnt_type[8];
NvU8 cnt_val[8];
} NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB (0x20803080U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID (0x80U)
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU16 ib_port;
NvU8 lp_msb;
NvU8 local_port;
NvU8 split_num;
} NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO (0x20803083U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
NvU8 ibGuid[16];
NvU8 rackGuid[16];
NvU8 chassisPhysicalSlotNumber;
NvU8 computeSlotIndex;
NvU8 nodeIndex;
NvU8 peerType;
NvU8 moduleId;
} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
/* _ctrl2080nvlink_h_ */

61
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -288,6 +288,42 @@ typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
} NV2080_CTRL_PERF_RATED_TDP_ACTION;
/*!
* Enumeration VPstates - these are possible VPStates that clients can
* request
*/
typedef enum NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE {
/*!
* Choise of the RATED TDP VPstate
*/
NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0,
/*!
* Choise of the TURBO BOOST VPstate
*/
NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1,
/*!
* Number of supported vpstates.
*
* @Note MUST ALWAYS BE LAST!
*/
NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2,
} NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE;
/*!
* Enumeration VPstates - these are possible VPStates that clients can
* request
*/
typedef struct NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST {
/*!
* [in] - Specified client for request.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION action;
/*!
* [in/out] - Client's requested action.
*/
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
} NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST;
/*!
* Structure describing dynamic state of the RATED_TDP feature.
*/
@@ -323,7 +359,12 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
/*
* [out] - Arbitrated output VPStates of all client requests (@ref inputs).
* This is the current VPState of the RATED_TDP feature.
*/
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE outputVPstate;
/*!
* [out] - Array of input client request actions, indexed via @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
@@ -331,7 +372,15 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
/*!
* [out] - Array of input client request VPstates, indexed via @ref
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
* requests, choosing the highest priority request != @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
*/
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateTypes[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
/*!
@@ -357,11 +406,15 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
/*!
* [in] - Specified client for request.
*/
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
/*!
* [in/out] - Client's requested action.
*/
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
/*
* [in] - Specified VPState of the request
*/
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU)

42
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080spdm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -34,6 +34,8 @@
/*************************** SPDM COMMANDS ************************************/
#include "cc_drv.h"
/*!
* @brief SPDM Command Types
*
@@ -43,6 +45,7 @@
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
@@ -114,6 +117,25 @@ typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
/*!
* HCC FIPS Self-test.
*/
#define CE_FIPS_SELF_TEST_DATA_SIZE 16
#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
#define CE_FIPS_SELF_TEST_IV_SIZE 12
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
NvU8 cmdType;
NvU8 isEnc;
CC_KMB kmb;
NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE];
NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
/*!
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
@@ -132,6 +154,9 @@ typedef union RM_GSP_SPDM_CMD {
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest;
} RM_GSP_SPDM_CMD;
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
@@ -149,6 +174,7 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6)
@@ -168,20 +194,20 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
* SPDM message structure.
*/
typedef struct RM_GSP_SPDM_MSG {
NvU8 msgType;
NvU8 msgType;
// status returned from GSP message infrastructure.
NvU32 status;
NvU32 status;
NvU32 rsvd1;
NvU32 rsvd1;
NvU32 rsvd2;
NvU32 rsvd2;
NvU32 rsvd3;
NvU32 rsvd3;
NvU32 rsvd4;
NvU32 rsvd4;
NvBool rsvd5;
NvU32 rsvd5;
} RM_GSP_SPDM_MSG;
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -61,7 +61,7 @@
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
#define NV2080_GPU_MAX_ENGINES 0x40
#define NV2080_GPU_MAX_ENGINES 0x54
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
@@ -85,6 +85,8 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8);
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8);
NvBool bDeviceProfilingEnabled;

4
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fbif.h
View File

@@ -43,7 +43,7 @@
* this specifies the function that needs to be performed on pbi
*data
* the data to be set in the data in register
* status
* status
* this corresponds to pbi status register
* sysNotify
* this corresponds to system notify event, i.e. whether system
@@ -115,7 +115,7 @@ typedef struct NV208F_CTRL_BIF_CONFIG_REG_WRITE_PARAMS {
* index
* Defines the index of the property to read
* data
* Data that is read
* Data that is read
*/
#define NV208F_CTRL_CMD_BIF_INFO (0x208f0704) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_BIF_INTERFACE_ID << 8) | NV208F_CTRL_BIF_INFO_PARAMS_MESSAGE_ID" */

71
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208ffb.h
View File

@@ -427,9 +427,11 @@ typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS {
NvBool bUncorrectableSupported;
} NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS;
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC 0:0
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC (0x00000000)
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001)
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC 1:0
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LTC (0x00000000)
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_DRAM (0x00000001)
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_LRC (0x00000002)
#define NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_LOC_SYSL2 (0x00000003)
/*
* NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL
@@ -451,7 +453,7 @@ typedef struct NV208F_CTRL_FB_ECC_INJECTION_SUPPORTED_PARAMS {
* address
* The physical DRAM address to be targeted by the write kill
*/
#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_CMD_FB_ECC_SET_WRITE_KILL (0x208f0511) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_ECC_SET_WRITE_KILL_PARAMS_MESSAGE_ID (0x11U)
@@ -591,4 +593,65 @@ typedef struct NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS {
NvBool bForcePurge;
} NV208F_CTRL_FB_CLEAR_REMAPPED_ROWS_PARAMS;
/*
* NV208F_CTRL_CMD_FB_INJECT_LRC_ECC_ERROR
*
* This API allows a client to inject ECC errors in the LRC.
*
* lrcc:
* The physical LRCC number to inject the error into.
* lrc:
* THe physical LRC number within the LRCC to inject the error into.
* locationMask
* LTC location subtype(s) where error is to be injected. (Valid on Ampere and later)
* errorType
* Type of error to inject
* NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE.
* NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE.
*
*/
#define NV208F_CTRL_CMD_FB_INJECT_LRC_ECC_ERROR (0x208f0516) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS_MESSAGE_ID (0x16U)
typedef struct NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS {
NvU8 lrcc;
NvU8 lrc;
NvU8 locationMask;
NV208F_CTRL_FB_ERROR_TYPE errorType;
} NV208F_CTRL_FB_INJECT_LRC_ECC_ERROR_PARAMS;
/*
* NV208F_CTRL_CMD_FB_INJECT_SYSLTC_ECC_ERROR
*
* This API allows a client to inject ECC errors in the SYSLTC.
*
* group:
* The physical group number to inject the error into.
* instance:
* The physical instance number within the group to inject the error into.
* instance:
* The physical slice number within the instance to inject the error into.
* locationMask
* SYSLTC location subtype(s) where error is to be injected. Same as LTC.
* errorType
* Type of error to inject
* NV208F_CTRL_FB_ERROR_TYPE_CORRECTABLE for SBE.
* NV208F_CTRL_FB_ERROR_TYPE_UNCORRECTABLE for DBE.
*
*/
#define NV208F_CTRL_CMD_FB_INJECT_SYSLTC_ECC_ERROR (0x208f0517) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_FB_INTERFACE_ID << 8) | NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS_MESSAGE_ID (0x17U)
typedef struct NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS {
NvU8 group;
NvU8 instance;
NvU8 slice;
NvU8 locationMask;
NV208F_CTRL_FB_ERROR_TYPE errorType;
} NV208F_CTRL_FB_INJECT_SYSLTC_ECC_ERROR_PARAMS;
/* _ctrl208ffb_h_ */

29
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fgr.h
View File

@@ -106,4 +106,33 @@ typedef struct NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV208F_CTRL_GR_ECC_INJECTION_SUPPORTED_PARAMS;
/*
* NV208F_CTRL_CMD_GR_ECC_SET_TRANSIENT_CLEARING_POLICY
*
* Control command to determine whether or not the actions to clear potential transient
* errors in the SM should be taken
*
* Parameters:
*
* policy
* NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_DISABLED
* Don't attempt to clear a transient error in the SM
* NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_ENABLED
* Attempt to clear a transient error in the SM
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_DISABLED (0x00000000)
#define NV208F_CTRL_GR_ECC_TRANSIENT_CLEARING_ENABLED (0x00000001)
#define NV208F_CTRL_CMD_GR_ECC_SET_TRANSIENT_CLEARING_POLICY (0x208f1205) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_GR_INTERFACE_ID << 8) | NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS_MESSAGE_ID (0x5U)
typedef struct NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS {
NvU32 policy;
} NV208F_CTRL_GR_ECC_SET_TRANSIENT_CLEARING_POLICY_PARAMS;
/* _ctrl208fgr_h_ */

21
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fmmu.h
View File

@@ -68,6 +68,7 @@ typedef struct NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS {
NvU32 sublocation;
NvU8 unit;
NvU8 errorType;
NvU8 instance;
} NV208F_CTRL_MMU_ECC_INJECT_ERROR_PARAMS;
@@ -126,6 +127,26 @@ typedef struct NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS {
NvU32 numHshubmmus;
} NV208F_CTRL_MMU_GET_NUM_HSHUBMMUS_PARAMS;
/*
* NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS
*
* Returns the number of ECC Capable HUBMMUS.
*
* numHubmmus [out]
* Number of Hubmmus
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV208F_CTRL_CMD_MMU_GET_NUM_HUBMMUS (0x208f0b04) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_DIAG_MMU_INTERFACE_ID << 8) | NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID" */
#define NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS {
NvU32 numHubmmus;
} NV208F_CTRL_MMU_GET_NUM_HUBMMUS_PARAMS;
/* _ctrl208fmmu_h_ */

2
src/common/sdk/nvidia/inc/ctrl/ctrl208f/ctrl208fpower.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2007-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2007-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

368
src/common/sdk/nvidia/inc/ctrl/ctrl5070/ctrl5070or.h
View File

@@ -149,149 +149,6 @@ typedef struct NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS {
NvU32 flags;
} NV5070_CTRL_CMD_SET_DAC_PWR_PARAMS;
/*
* NV5070_CTRL_CMD_GET_SOR_PWM
*
* This command returns SOR's current PWM settings.
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* targetFreq
* The target PWM freq. This is the PWM frequency we planned on
* programming.
*
* actualFreq
* Actual PWM freq programmed into PWM.
*
* div
* The divider being used currently for generating PWM clk.
* A valued of 0 means that PWM is disabled.
*
* resolution
* The resolution of steps currently programmed or the max number of
* clocks per cycle. The possible values for NV50 are 128, 256, 512
* and 1024. This field is irrelevant when div is 0.
*
* dutyCycle
* Duty cycle in range 0-1024
*
* sourcePCLK (OUT)
* The PWM source clock selector. This field is non-zero if the PCLK
* is selected as the PWM source clock. Otherwise, the PWM source
* clock is XTAL.
*
* head (IN)
* The head for which the pixel clock is sourced from.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_GET_SOR_PWM (0x50700420) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 targetFreq;
NvU32 actualFreq;
NvU32 div;
NvU32 resolution;
NvU32 dutyCycle;
NvU32 sourcePCLK;
NvU32 head;
} NV5070_CTRL_CMD_GET_SOR_PWM_PARAMS;
/*
* NV5070_CTRL_CMD_SET_SOR_PWM
*
* This command returns SOR's current PWM settings.
*
* orNumber
* The OR number for which the seq ctrls are to be modified.
*
* targetFreq
* The target PWM freq to be programmed.
*
* actualFreq
* Actual PWM freq programmed into PWM after all the specified
* settings have been applied.
*
* div
* The divider to use for generating PWM clk.
* Set this to 0 to disable PWM. Note that only one of div
* or targetFreq can be specified at a time since specifying one
* automatically determines the value of the other. Selection is
* done via USE_SPECIFIED_DIV flag.
*
* resolution
* The resolution or the max number of clocks per cycle desired.
* Note that if it's not possible to program the given resolution
* and frequency (or div) combination, RM would not attempt to
* smartly lower the resolution. The call would return failure.
* The possible values for NV50 are 128, 256, 512 and 1024. This
* field is irrelevant when div is 0.
*
* dutyCycle
* Duty cycle in range 0-1024
*
* flags
* The following flags have been defined:
* (1) USE_SPECIFIED_DIV: Indicates whether RM should use
* specified div or targetFreq when determining the divider
* for xtal clock.
* (2) PROG_DUTY_CYCLE: Indicates whether or not the caller
* desires to program duty cycle. Normally whenever pwm freq
* and range need to be programmed, it's expected that duty
* cycle would be reprogrammed as well but this is not
* enforced.
* (3) PROG_FREQ_AND_RANGE: Indicates whether or not the caller
* desires to program a new PWM setting (div and resolution).
* (4) SOURCE_CLOCK: Indicates whether the PCLK or XTAL is used
* as the PWM clock source. GT21x and better.
*
* head (IN)
* The head for which the pixel clock is sourced from.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_SET_SOR_PWM (0x50700421) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV 0:0
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_NO (0x00000000)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_USE_SPECIFIED_DIV_YES (0x00000001)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE 1:1
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_NO (0x00000000)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_DUTY_CYCLE_YES (0x00000001)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE 2:2
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_NO (0x00000000)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_PROG_FREQ_AND_RANGE_YES (0x00000001)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK 3:3
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_XTAL (0x00000000)
#define NV5070_CTRL_CMD_SET_SOR_PWM_FLAGS_SOURCE_CLOCK_PCLK (0x00000001)
#define NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 targetFreq;
NvU32 actualFreq;
NvU32 div; // equivalent of NV_PDISP_SOR_PWM_DIV_DIVIDE
NvU32 resolution; // equivalent of NV_PDISP_SOR_PWM_DIV_RANGE
NvU32 dutyCycle;
NvU32 flags;
NvU32 head;
} NV5070_CTRL_CMD_SET_SOR_PWM_PARAMS;
/*
* NV5070_CTRL_CMD_GET_SOR_OP_MODE
*
@@ -641,231 +498,6 @@ typedef struct NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS {
NvU32 rotDat;
} NV5070_CTRL_CMD_SET_SOR_OP_MODE_PARAMS;
/*
* NV5070_CTRL_CMD_GET_PIOR_OP_MODE
*
* This command returns current settings for the specified PIOR.
*
* orNumber
* The OR number for which the operating mode needs to be programmed.
*
* category
* Whether ext TMDS, TV, DRO or DRI settings are desired.
* EXT TV is not supported at the moment.
* EXT DisplayPort is specified through EXT 10BPC 444.
*
* clkPolarity
* Whether or not output clock is inverted relative to generated clock.
*
* clkMode
* Whether data being transmitted is SDR or DDR.
*
* clkPhs
* Position of the edge on which data is launched.
*
* unusedPins
* Status of unused pins of this PIOR.
*
* polarity
* Whether or not sync and DE pin polarities are inverted.
*
* dataMuxing
* How are the bits are multiplexed together.
*
* clkDelay
* Extra delay for the clock.
*
* dataDelay
* Extra delay for the data.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE (0x50700430) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY 2:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY 0:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE 0:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS 1:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_0 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_1 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_2 0x00000002
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_PHS_3 0x00000003
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS 0:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H 0:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V 1:1
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE 2:2
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING 3:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_CLK_DLY 2:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_DATA_DLY 2:0
#define NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x30U)
typedef struct NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 category;
NvU32 clkPolarity;
NvU32 clkMode;
NvU32 clkPhs;
NvU32 unusedPins;
NvU32 polarity;
NvU32 dataMuxing;
NvU32 clkDelay;
NvU32 dataDelay;
} NV5070_CTRL_CMD_GET_PIOR_OP_MODE_PARAMS;
/*
* NV5070_CTRL_CMD_SET_PIOR_OP_MODE
*
* This command applies the specified settings to the specified PIOR.
*
* orNumber
* The OR number for which the operating mode needs to be programmed.
*
* category
* Whether ext TMDS, TV, DRO or DRI settings are to be programmed.
* EXT TV is not supported at the moment.
* EXT DisplayPort is specified through EXT 10BPC 444.
*
* clkPolarity
* Whether or not to invert output clock relative to generated clock.
*
* clkMode
* Whether data being transmitted should be SDR or DDR.
*
* clkPhs
* Position of the edge on which data should be launched.
*
* unusedPins
* What to do with unused pins of this PIOR.
*
* polarity
* Whether or not to invert sync and DE pin polarities.
*
* dataMuxing
* How to multiplex the bits together.
*
* clkDelay
* Extra delay for the clock.
*
* dataDelay
* Extra delay for the data.
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_GENERIC
*/
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE (0x50700431) /* finn: Evaluated from "(FINN_NV50_DISPLAY_OR_INTERFACE_ID << 8) | NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID" */
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY 2:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TMDS 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_TV 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRO 0x00000003
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_DRI 0x00000004
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CATEGORY_EXT_10BPC_444 0x00000005
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY 0:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_NORMAL 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_POLARITY_INV 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE 0:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_SDR 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_MODE_DDR 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS 1:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_0 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_1 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_2 0x00000002
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_PHS_3 0x00000003
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS 0:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_LO 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_UNUSED_PINS_TS 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H 0:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_NORMAL 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_H_INV 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V 1:1
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_NORMAL 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_V_INV 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE 2:2
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_NORMAL 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_POLARITY_DE_INV 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING 3:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_0 0x00000000
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_RGB_1 0x00000001
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_DIST_RNDR 0x00000003
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_YUV_0 0x00000004
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_MUXING_UYVY 0x00000005
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_CLK_DLY 2:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DATA_DLY 2:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_MASTER 1:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET 2:0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_NEITHER 0
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_A 1
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_DRO_DRIVE_PIN_SET_B 2
#define NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS {
NV5070_CTRL_CMD_BASE_PARAMS base;
NvU32 orNumber;
NvU32 category;
NvU32 clkPolarity;
NvU32 clkMode;
NvU32 clkPhs;
NvU32 unusedPins;
NvU32 polarity;
NvU32 dataMuxing;
NvU32 clkDelay;
NvU32 dataDelay;
NvU32 dro_master;
NvU32 dro_drive_pin_set;
} NV5070_CTRL_CMD_SET_PIOR_OP_MODE_PARAMS;
/*
* NV5070_CTRL_CMD_SET_SOR_FLUSH_MODE
*

2
src/common/sdk/nvidia/inc/ctrl/ctrla06c.h
View File

@@ -402,6 +402,8 @@ typedef struct NVA06C_CTRL_MAKE_REALTIME_PARAMS {
/*
* NVA06C_CTRL_CMD_INTERNAL_GPFIFO_SCHEDULE
*

7
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -660,6 +660,9 @@ typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS {
*
* heterogeneousMultiVgpuSupported [OUT]
* This param specifies whether heterogeneous multi-vGPU is supported
* warmUpdateSupported [OUT]
* This param specifies FSR / warm driver update operation is supported
* ie. supports FSR and warm update of vGPU host driver without terminating the running guest VM
*
* Possible status values returned are:
* NV_OK
@@ -674,6 +677,7 @@ typedef struct NVA081_CTRL_PGPU_GET_MULTI_VGPU_SUPPORT_INFO_PARAMS {
typedef struct NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS {
NvU32 heterogeneousMultiVgpuSupported;
NvU32 warmUpdateSupported;
} NVA081_CTRL_GET_VGPU_DRIVER_CAPS_PARAMS;
/*
@@ -823,6 +827,7 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
/* vGPU capabilities */
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
#define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1
#define NVA081_CTRL_VGPU_CAPABILITY_WARM_UPDATE 2
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY

92
src/common/sdk/nvidia/inc/ctrl/ctrlb0cc/ctrlb0ccprofiler.h
View File

@@ -556,6 +556,98 @@ typedef struct NVB0CC_CTRL_RELEASE_HES_PARAMS {
NVB0CC_CTRL_HES_TYPE type;
} NVB0CC_CTRL_RELEASE_HES_PARAMS;
/*!
* Defines the maximum count of output credit pools.
* 30 is estimate based on the # of PMAs (2) and chiplet types(3),
* which should be big enough to accommodate the required number of credit pools
*/
#define NVB0CC_CREDIT_POOL_MAX_COUNT 30
/*!
* NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL
*
* Gets the total high speed streaming credits available for the client
* in each chiplet pool.
*
* This command is similar to @ref NVB0CC_CTRL_CMD_GET_TOTAL_HS_CREDITS but
* supports multiple chiplet credit pools.
*
*/
typedef struct NVB0CC_CTRL_CREDIT_POOL_INFO {
/*!
* [out] number of credits.
*/
NvU16 numCredits;
/*!
* [out] index of credit pool.
*/
NvU8 poolIndex;
/*!
* [out] chiplet type of credit pool.
*/
NvU8 chipletType;
} NVB0CC_CTRL_CREDIT_POOL_INFO;
#define NVB0CC_CTRL_CMD_GET_CHIPLET_HS_CREDIT_POOL (0xb0cc0115) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID" */
#define NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL_MESSAGE_ID (0x15U)
typedef struct NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL {
/*!
* [out] chiplet-level credit pool.
*/
NVB0CC_CTRL_CREDIT_POOL_INFO poolInfos[NVB0CC_CREDIT_POOL_MAX_COUNT];
/*!
* [out] number of credit pools.
*/
NvU32 poolInfosCount;
} NVB0CC_CTRL_GET_CHIPLET_HS_CREDIT_POOL;
typedef struct NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO {
/*!
* [in] Specifies the chiplet type @ref NVB0CC_CHIPLET_TYPE.
*/
NvU8 chipletType;
/*!
* [in] Specifies the logical index of the chiplet.
*/
NvU8 chipletIndex;
/*!
* [out] Specifies the index of credits pool for the chiplet.
*/
NvU8 poolIndex;
} NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO;
/*!
* NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING
*
* Query the associated PMA credit pool index for given chiplet.
*
*/
#define NVB0CC_CTRL_CMD_GET_HS_CREDITS_MAPPING (0xb0cc0116) /* finn: Evaluated from "(FINN_MAXWELL_PROFILER_PROFILER_INTERFACE_ID << 8) | NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID" */
#define NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS_MESSAGE_ID (0x16U)
typedef struct NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS {
/*!
* [in]: number of input queries.
*/
NvU16 numQueries;
/*!
* [out] Provides status for the entire operation.
*/
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_STATUS statusInfo;
/*!
* [in/out]: Used to query the PMA credit pool index of specified chiplet.
*/
NVB0CC_CTRL_PMA_STREAM_HS_CREDITS_MAPPING_INFO queries[NVB0CC_MAX_CREDIT_INFO_ENTRIES];
} NVB0CC_CTRL_GET_HS_CREDITS_POOL_MAPPING_PARAMS;
/* End of extension construct */

2
src/common/sdk/nvidia/inc/ctrl/ctrlc370/ctrlc370or.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2015-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

61
src/common/sdk/nvidia/inc/ctrl/ctrlc96f.h Normal file
View File

@@ -0,0 +1,61 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#pragma once
//
// This file was generated with FINN, an NVIDIA coding tool.
// Source file: ctrl/ctrlc96f.finn
//
#include "nvcfg_sdk.h"
/* BLACKWELL_CHANNEL_GPFIFO_A control commands and parameters */
#include "ctrl/ctrlxxxx.h"
#include "ctrl/ctrl906f.h" /* C36F is partially derived from 906F */
#include "ctrl/ctrla06f.h" /* C36F is partially derived from a06F */
#include "ctrl/ctrlc36f.h" // This control call interface is an ALIAS of C36F
#define NVC96F_CTRL_CMD(cat,idx) \
NVXXXX_CTRL_CMD(0xC36F, NVC96F_CTRL_##cat, idx)
/* BLACKWELL_CHANNEL_GPFIFO_A command categories (6bits) */
#define NVC96F_CTRL_RESERVED (0x00)
#define NVC96F_CTRL_GPFIFO (0x01)
#define NVC96F_CTRL_EVENT (0x02)
/*
* NVC96F_CTRL_CMD_NULL
*
* This command does nothing.
* This command does not take any parameters.
*
* Possible status values returned is: NV_OK
*/
#define NVC96F_CTRL_CMD_NULL (NVC36F_CTRL_CMD_NULL)

33
src/common/sdk/nvidia/inc/ctrl/ctrlcb33.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -387,5 +387,36 @@ typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS {
NvU32 maxCeChannels;
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_NUM_SECURE_CHANNELS_PARAMS;
/*
* NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE
* This control call returns if key rotation is enabled.
*
* hSubDevice: [IN]
* subdevice handle for the GPU queried
* keyRotationState: [OUT]
* NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_* value
*
* Possible return values:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_INVALID_OBJECT_HANDLE
* NV_ERR_INVALID_CLIENT
* NV_ERR_OBJECT_NOT_FOUND
*/
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE (0xcb33010c) /* finn: Evaluated from "(FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID << 8) | 0xC" */
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_DISABLED 0 // key rotation is disabled
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_KERN_ENABLED 1 // key rotation enabled for kernel keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_USER_ENABLED 2 // key rotation enabled for user keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_KEY_ROTATION_BOTH_ENABLED 3 // key rotation enabled for both keys
#define NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS_MESSAGE_ID (0xCU)
typedef struct NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS {
NvHandle hSubDevice;
NvU32 keyRotationState;
} NV_CONF_COMPUTE_CTRL_CMD_GPU_GET_KEY_ROTATION_STATE_PARAMS;
/* _ctrlcb33_h_ */

3
src/common/sdk/nvidia/inc/g_finn_rm_api.h
View File

@@ -711,6 +711,9 @@ typedef FINN_RM_API FINN_MMU_VIDMEM_ACCESS_BIT_BUFFER_VIDMEM_ACCESS_BIT_BUFFER;
#define FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc86f00U)
typedef FINN_RM_API FINN_HOPPER_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED_INTERFACE_ID (0xc96f00U)
typedef FINN_RM_API FINN_BLACKWELL_CHANNEL_GPFIFO_A_RESERVED;
#define FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED_INTERFACE_ID (0xcb3300U)
typedef FINN_RM_API FINN_NV_CONFIDENTIAL_COMPUTE_RESERVED;
#define FINN_NV_CONFIDENTIAL_COMPUTE_CONF_COMPUTE_INTERFACE_ID (0xcb3301U)

56
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -118,21 +118,34 @@
#define SPI_PMU_RPC_WRITE_FAIL (123)
#define SPI_PMU_RPC_ERASE_FAIL (124)
#define INFOROM_FS_ERROR (125)
#define ROBUST_CHANNEL_CE10_ERROR (126)
#define ROBUST_CHANNEL_CE11_ERROR (127)
#define ROBUST_CHANNEL_CE12_ERROR (128)
#define ROBUST_CHANNEL_CE13_ERROR (129)
#define ROBUST_CHANNEL_CE14_ERROR (130)
#define ROBUST_CHANNEL_CE15_ERROR (131)
#define ROBUST_CHANNEL_CE16_ERROR (132)
#define ROBUST_CHANNEL_CE17_ERROR (133)
#define ROBUST_CHANNEL_CE18_ERROR (134)
#define ROBUST_CHANNEL_CE19_ERROR (135)
#define ALI_TRAINING_FAIL (136)
#define NVLINK_FLA_PRIV_ERR (137)
#define ROBUST_CHANNEL_DLA_ERROR (138)
#define ROBUST_CHANNEL_OFA1_ERROR (139)
#define UNRECOVERABLE_ECC_ERROR_ESCAPE (140)
#define ROBUST_CHANNEL_FAST_PATH_ERROR (141)
#define GPU_INIT_ERROR (143)
#define RESERVED0_ERROR (144)
#define RESERVED1_ERROR (145)
#define RESERVED2_ERROR (146)
#define RESERVED3_ERROR (147)
#define RESERVED4_ERROR (148)
#define RESERVED5_ERROR (149)
#define RESERVED6_ERROR (150)
#define NVLINK_SAW_ERROR (144)
#define NVLINK_RLW_ERROR (145)
#define NVLINK_TLW_ERROR (146)
#define NVLINK_TREX_ERROR (147)
#define NVLINK_NVLPW_CTRL_ERROR (148)
#define NVLINK_NETIR_ERROR (149)
#define NVLINK_MSE_ERROR (150)
#define ROBUST_CHANNEL_KEY_ROTATION_ERROR (151)
#define ROBUST_CHANNEL_LAST_ERROR (151)
#define RESERVED7_ERROR (152)
#define RESERVED8_ERROR (153)
#define ROBUST_CHANNEL_LAST_ERROR (153)
// Indexed CE reference
@@ -143,14 +156,21 @@
(ROBUST_CHANNEL_CE3_ERROR + (x - 3)) : \
((x < 9) ? \
(ROBUST_CHANNEL_CE6_ERROR + (x - 6)) : \
(ROBUST_CHANNEL_CE9_ERROR))))
((x == 9) ? \
(ROBUST_CHANNEL_CE9_ERROR) : \
(ROBUST_CHANNEL_CE10_ERROR + (x - 10))))))
#define ROBUST_CHANNEL_IS_CE_ERROR(x) \
((x == ROBUST_CHANNEL_CE0_ERROR) || (x == ROBUST_CHANNEL_CE1_ERROR) || \
(x == ROBUST_CHANNEL_CE2_ERROR) || (x == ROBUST_CHANNEL_CE3_ERROR) || \
(x == ROBUST_CHANNEL_CE4_ERROR) || (x == ROBUST_CHANNEL_CE5_ERROR) || \
(x == ROBUST_CHANNEL_CE6_ERROR) || (x == ROBUST_CHANNEL_CE7_ERROR) || \
(x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR))
(x == ROBUST_CHANNEL_CE8_ERROR) || (x == ROBUST_CHANNEL_CE9_ERROR) || \
(x == ROBUST_CHANNEL_CE10_ERROR) || (x == ROBUST_CHANNEL_CE11_ERROR) || \
(x == ROBUST_CHANNEL_CE12_ERROR) || (x == ROBUST_CHANNEL_CE13_ERROR) || \
(x == ROBUST_CHANNEL_CE14_ERROR) || (x == ROBUST_CHANNEL_CE15_ERROR) || \
(x == ROBUST_CHANNEL_CE16_ERROR) || (x == ROBUST_CHANNEL_CE17_ERROR) || \
(x == ROBUST_CHANNEL_CE18_ERROR) || (x == ROBUST_CHANNEL_CE19_ERROR))
#define ROBUST_CHANNEL_CE_ERROR_IDX(x) \
(((x >= ROBUST_CHANNEL_CE0_ERROR) && (x <= ROBUST_CHANNEL_CE2_ERROR)) ? \
@@ -159,7 +179,9 @@
(x - ROBUST_CHANNEL_CE3_ERROR + 3) : \
(((x >= ROBUST_CHANNEL_CE6_ERROR) && (x <= ROBUST_CHANNEL_CE8_ERROR)) ? \
(x - ROBUST_CHANNEL_CE6_ERROR + 6) : \
(x - ROBUST_CHANNEL_CE9_ERROR + 9))))
((x == ROBUST_CHANNEL_CE9_ERROR) ? \
(x - ROBUST_CHANNEL_CE9_ERROR + 9) : \
(x - ROBUST_CHANNEL_CE10_ERROR + 10)))))
// Indexed NVDEC reference
#define ROBUST_CHANNEL_NVDEC_ERROR(x) \
@@ -229,14 +251,20 @@
(x - ROBUST_CHANNEL_NVJPG0_ERROR) : \
(x - ROBUST_CHANNEL_NVJPG1_ERROR + 1))
// Indexed OFA reference
#define ROBUST_CHANNEL_OFA_ERROR(x) \
(ROBUST_CHANNEL_OFA0_ERROR)
((x == 0) ? \
(ROBUST_CHANNEL_OFA0_ERROR) : \
(ROBUST_CHANNEL_OFA1_ERROR))
#define ROBUST_CHANNEL_IS_OFA_ERROR(x) \
(x == ROBUST_CHANNEL_OFA0_ERROR)
((x == ROBUST_CHANNEL_OFA0_ERROR) || \
(x == ROBUST_CHANNEL_OFA1_ERROR))
#define ROBUST_CHANNEL_OFA_ERROR_IDX(x) \
(x - ROBUST_CHANNEL_OFA0_ERROR)
((x == ROBUST_CHANNEL_OFA0_ERROR) ? \
(x - ROBUST_CHANNEL_OFA0_ERROR) : \
(x - ROBUST_CHANNEL_OFA1_ERROR + 1))
// Error Levels
#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0)

6
src/common/sdk/nvidia/inc/nvfixedtypes.h
View File

@@ -87,6 +87,7 @@ typedef NvUFXP32 NvUFXP28_4;
typedef NvUFXP64 NvUFXP40_24;
typedef NvUFXP64 NvUFXP48_16;
typedef NvUFXP64 NvUFXP52_12;
typedef NvUFXP64 NvUFXP60_4;
/*!
* Utility macros used in converting between signed integers and fixed-point
@@ -371,6 +372,11 @@ typedef NvSFXP24_8 NvTemp;
*/
#define NV_TYPES_NVSFXP11_5_TO_NV_TEMP(x) ((NvTemp)(x) << 3)
/*!
* Macro to convert UFXP 5.3 to NvTemp.
*/
#define NV_TYPES_NVUFXP5_3_TO_NV_TEMP(x) ((NvTemp)(x) << 5)
/*!
* Macro to convert UFXP11.5 Watts to NvU32 milli-Watts.
*/

3
src/common/sdk/nvidia/inc/nvmisc.h
View File

@@ -67,6 +67,9 @@ extern "C" {
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
#endif
//Concatenate 2 32bit values to a 64bit value
#define NV_CONCAT_32_TO_64(hi, lo) ((((NvU64)hi) << 32) | ((NvU64)lo))
// Helper macro's for 32 bit bitmasks
#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3)
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)

80
src/common/sdk/nvidia/inc/nvos.h
View File

@@ -1300,6 +1300,7 @@ typedef struct
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_DEFAULT 0x00000000
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_2MB 0x00000001
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_512MB 0x00000002
#define NVOS32_ATTR2_PAGE_SIZE_HUGE_256GB 0x00000003
// Allow read-only or read-write user CPU mappings
#define NVOS32_ATTR2_PROTECTION_USER 22:22
@@ -2848,85 +2849,6 @@ typedef struct
// NV_TIMEOUT_CONTROL_CMD_RESET_DEVICE_TIMEOUT resets the device timeout to its
// default value. It uses 'deviceInstance' as the target device.
/**
* @brief GspTestGetRpcMessageData parameters
*
* This API is used by the user-mode GSP firmware RM to get RPC message data
* from the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* blockNum
* Specifies block number of message data to return. A value of 0
* indicates that the (default) message header and body should be returned
* in the buffer. If additional RPC-specific data is required it can
* be read by continually incrementing the block number and reading the
* next block in sequence.
* msgBufferSize
* Size (in bytes) of buffer pointed to by pMsgBuffer.
* pMsgBuffer
* Address of user-buffer into which RPC message data will be copied.
* status
* Returns status of call.
**/
typedef struct
{
NvU32 blockNum; // [IN] block # of data to get
NvU32 bufferSize; // [IN] size of pBuffer
NvP64 pBuffer NV_ALIGN_BYTES(8); // [OUT] buffer returning data
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_GET_MSG_BLOCK_PARAMETERS;
/**
* @brief GspTestSendRpcMessageResponse parameters
*
* This API is used to by the user-mode GSP firmware RM to send an RPC message
* response to the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* bufferSize
* Size (in bytes) of buffer pointed to by pBuffer.
* pBuffer
* Address of user-buffer from which RPC response data will be copied.
* status
* Returns status of call.
**/
typedef struct
{
NvU32 bufferSize; // [IN] size of response data buffer
NvP64 pBuffer NV_ALIGN_BYTES(8); // [IN] response data buffer
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_SEND_MSG_RESPONSE_PARAMETERS;
/**
* @brief GspTestSendEventNotification parameters
*
* This API is used by the user-mode GSP firmware RM to send an event
* notification to the kernel-mode GSP client RM.
*
* This API is only supported in the GSP testbed environment.
*
* hParentClient
* Specifies handle of client that owns object associated with event.
* hSrcResource
* Specifies handle of object associated with event.
* hClass
* Specifies class number (type) of event.
* notifyIndex
* Specifies notifier index associated with event.
* status
* Returns status of call.
**/
typedef struct
{
NvHandle hParentClient; // [IN] handle of client
NvHandle hSrcResource; // [IN] handle of object
NvU32 hClass; // [IN] class number of event
NvU32 notifyIndex; // [IN] notifier index
NvV32 status; // [OUT] status of call
} NV_GSP_TEST_SEND_EVENT_NOTIFICATION_PARAMETERS;
/*
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_COH
* NV_VIDMEM_ACCESS_BIT_BUFFER_ADDR_SPACE_DEFAULT

2
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -153,6 +153,8 @@ NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Su
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled")
NV_STATUS_CODE(NV_ERR_SECURE_BOOT_FAILED, 0x0000007F, "GFW secure boot failed")
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_ZBC_ENTRY, 0x00000080, "No more ZBC entry for the client")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

2
src/common/sdk/nvidia/inc/rmcd.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2002-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2002-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a