mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-05 15:49:58 +00:00
560.28.03
This commit is contained in:
Gaurav Juvekar
@@ -1182,10 +1182,19 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
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* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS
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*
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* This command returns the PCIe requester atomics operation capabilities
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* from GPU to coherent SYSMEM.
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* of the GPU with regards to the aspect of support the client is asking for.
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*
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*
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* capType [IN]
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* The aspect of the atomics support the client is querying atomics capability for.
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* Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
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*
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* dbdf [IN] -
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* Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
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* Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
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*
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* atomicsCaps[OUT]
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* Mask of supported PCIe atomic operations in the form of
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* Mask of supported PCIe requester atomic operations in the form of
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* NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_*
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*
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* Possible status values returned are:
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@@ -1198,9 +1207,26 @@ typedef struct NV2080_CTRL_BUS_GET_EOM_STATUS_PARAMS {
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x29U)
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typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
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NvU32 capType;
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NvU32 dbdf;
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NvU32 atomicsCaps;
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} NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS;
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/*
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* Defined methods to expose atomics capability.
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*
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* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM
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* Exposes the state of atomics support between GPU and Sysmem.
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* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU
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* Exposes the state of the GPU atomics support without taking into account PCIe topology.
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* NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P
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* Exposes the state of atomics support between the source (this GPU)
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* and peer GPU identified by the dbdf argument.
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*/
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#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_SYSMEM 0x0
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#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_GPU 0x1
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#define NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_P2P 0x2
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32 0:0
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000)
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@@ -1230,19 +1256,19 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
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* that map to the capable PCIe atomic operations from GPU to
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* coherent SYSMEM.
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*
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* capType [IN]
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* The aspect of the atomics support the client is querying atomics capability for.
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* Supported types are defined under NV2080_CTRL_CMD_BUS_PCIE_ATOMICS_CAPTYPE_*.
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*
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* dbdf [IN] -
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* Argument used to identify the PCIe peer endpoint. Used only for the _CAPTYPE_P2P.
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* Encoded as: domain (31:16), bus (15:8), device (7:3), function (2:0)
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*
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* atomicOp[OUT]
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* Array of structure that contains the atomic operation
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* Array of NV2080_CTRL_BUS_PCIE_GPU_ATOMICS that contains the atomic operation
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* supported status and its attributes. The array can be
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* indexed using one of NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_*
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*
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* bSupported[OUT]
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* Is the GPU atomic operation natively supported by the PCIe?
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*
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* attributes[OUT]
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* Provides the attributes mask of the GPU atomic operation when supported
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* in the form of
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* NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_REDUCTION_*
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*
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*/
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS (0x2080182a) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID" */
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@@ -1262,13 +1288,30 @@ typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_REQ_ATOMICS_CAPS_PARAMS {
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#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT 13
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/*
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* NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO
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*
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* Describes the support state and related attributes of a single GPU atomic op.
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*
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* bSupported
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* Is the GPU atomic operation natively supported by the PCIe
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*
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* attributes
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* Provides the attributes mask of the GPU atomic operation when supported
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* in the form of
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* NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_*
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*/
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typedef struct NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO {
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NvBool bSupported;
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NvU32 attributes;
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} NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO;
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS_MESSAGE_ID (0x2AU)
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typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS {
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struct {
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NvBool bSupported;
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NvU32 attributes;
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} atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
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NvU32 capType;
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NvU32 dbdf;
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NV2080_CTRL_BUS_PCIE_GPU_ATOMIC_OP_INFO atomicOp[NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_OP_TYPE_COUNT];
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} NV2080_CTRL_CMD_BUS_GET_PCIE_SUPPORTED_GPU_ATOMICS_PARAMS;
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#define NV2080_CTRL_PCIE_SUPPORTED_GPU_ATOMICS_ATTRIB_SCALAR 0:0
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@@ -1464,3 +1507,48 @@ typedef struct NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS {
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NvU8 remoteGpuUuid[NV2080_SET_P2P_MAPPING_UUID_LEN];
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} NV2080_CTRL_BUS_UNSET_P2P_MAPPING_PARAMS;
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/*
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* NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS
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*
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* This command returns the PCIe completer atomics operation capabilities
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* of the GPU.
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*
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* atomicsCaps[OUT]
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* Mask of supported PCIe completer atomic operations in the form of
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* NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_*
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*
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* Possible status values returned are:
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* NV_OK
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS (0x20801830) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_BUS_INTERFACE_ID << 8) | NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS_MESSAGE_ID (0x30U)
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typedef struct NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS {
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NvU32 atomicsCaps;
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} NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_PARAMS;
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32 0:0
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_32_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64 1:1
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_FETCHADD_64_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32 2:2
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_32_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64 3:3
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_SWAP_64_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32 4:4
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_32_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64 5:5
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_64_NO (0x00000000)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128 6:6
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_YES (0x00000001)
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#define NV2080_CTRL_CMD_BUS_GET_PCIE_CPL_ATOMICS_CAPS_CAS_128_NO (0x00000000)
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -99,6 +99,7 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
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#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_NONPIPELINED_BL 1:0x01
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#define NV2080_CTRL_CE_CAPS_CE_SUPPORTS_PIPELINED_BL 1:0x02
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#define NV2080_CTRL_CE_CAPS_CE_CC_SECURE 1:0x04
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#define NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED 1:0x08
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/*
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* NV2080_CTRL_CE_CAPS_CE_GRCE
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@@ -135,6 +136,10 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
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*
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* NV2080_CTRL_CE_CAPS_CE_CC_SECURE
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* Set if the CE is capable of encryption/decryption
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*
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* NV2080_CTRL_CE_CAPS_CE_DECOMP_SUPPORTED
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* Set if the CE is capable of handling decompression workloads;
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* async copies will not be supported on the same CE
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*/
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/*
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@@ -154,6 +159,10 @@ typedef struct NV2080_CTRL_CE_GET_CAPS_V2_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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*/
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/*
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* The pceMask is local to the CE shim that ceEngineType belongs to.
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*/
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#define NV2080_CTRL_CMD_CE_GET_CE_PCE_MASK (0x20802a02) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_CE_PCE_MASK_PARAMS_MESSAGE_ID" */
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@@ -228,6 +237,15 @@ typedef struct NV2080_CTRL_CE_SET_PCE_LCE_CONFIG_PARAMS {
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* NV_ERR_GENERIC
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*/
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/*
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* This command updates the PCE-LCE mappings for one CE shim. On
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* GPUs with multiple CE shims, this interface must be called for
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* each shim.
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*
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* shimInstance [IN]
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* Specify which CE shim instance to operate on.
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*/
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#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS (0x20802a05) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS_MESSAGE_ID" */
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@@ -254,6 +272,10 @@ typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_PARAMS {
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* set in stubbedCeMask.
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*/
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/*
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* This function operates on all CE shims.
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*/
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#define NV2080_CTRL_CMD_CE_UPDATE_CLASS_DB (0x20802a06) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_CLASS_DB_PARAMS_MESSAGE_ID" */
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@@ -339,5 +361,142 @@ typedef struct NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS {
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typedef NV2080_CTRL_CE_GET_ALL_CAPS_PARAMS NV2080_CTRL_CE_GET_ALL_PHYSICAL_CAPS_PARAMS;
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/*
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* NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO
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*
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* This command queries LCE shim information of a specified CE.
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* The information includes the shim instance the CE belongs to.
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* And the local LCE within the shim.
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*
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* [in] ceEngineType
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* This parameter specifies the copy engine type, NV2080 define
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* [out] shimInstance
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* The shim instance the ceEngineType belongs to.
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* [out] shimLocalLceIdx
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* The local LCE index within the shim
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*
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*/
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#define NV2080_CTRL_CMD_CE_GET_LCE_SHIM_INFO (0x20802a0c) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS_MESSAGE_ID (0xcU)
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typedef struct NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS {
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NvU32 ceEngineType;
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NvU32 shimInstance;
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NvU32 shimLocalLceIdx;
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} NV2080_CTRL_CE_GET_LCE_SHIM_INFO_PARAMS;
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/*
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* This command is identical to NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS
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* but supports more than one CE shim.
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*
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* This command updates the PCE-LCE mappings for one CE shim. On
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* GPUs with multiple CE shims, this interface must be called for
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* each shim.
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*
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* shimInstance [IN]
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* Specify which CE shim instance to operate on.
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*/
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#define NV2080_CTRL_CMD_CE_UPDATE_PCE_LCE_MAPPINGS_V2 (0x20802a0d) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS_MESSAGE_ID (0xdU)
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typedef struct NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS {
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NvU32 pceLceMap[NV2080_CTRL_MAX_PCES];
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NvU32 grceConfig[NV2080_CTRL_MAX_GRCES];
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NvU32 exposeCeMask;
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NvBool bUpdateNvlinkPceLce;
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NvU32 shimInstance;
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} NV2080_CTRL_CE_UPDATE_PCE_LCE_MAPPINGS_V2_PARAMS;
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/*
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* This command is identical to NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_PARAMS
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* but supports more than one CE shim.
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*
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* This command gets HSHUB/CEHUB and FBHUB PCE Mask. On
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* GPUs with multiple CE shims, this interface must be called for
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* each shim.
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*
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* [in] shimInstance
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* Specify which CE shim instance to operate on.
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*/
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#define NV2080_CTRL_CMD_CE_GET_HUB_PCE_MASK_V2 (0x20802a0e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS_MESSAGE_ID (0xeU)
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typedef struct NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS {
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NvU32 connectingHubPceMasks[NV2080_CTRL_CE_MAX_HSHUBS];
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NvU32 fbhubPceMask;
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NvU32 shimInstance;
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} NV2080_CTRL_CE_GET_HUB_PCE_MASK_V2_PARAMS;
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typedef enum NV2080_CTRL_CE_LCE_TYPE {
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NV2080_CTRL_CE_LCE_TYPE_PCIE = 1,
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NV2080_CTRL_CE_LCE_TYPE_DECOMP = 2,
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NV2080_CTRL_CE_LCE_TYPE_SCRUB = 3,
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NV2080_CTRL_CE_LCE_TYPE_NVLINK_PEER = 4,
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NV2080_CTRL_CE_LCE_TYPE_C2C = 5,
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} NV2080_CTRL_CE_LCE_TYPE;
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/*
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* NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE
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*
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* This command queries the PCE config required for the specified LCE type.
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*
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* [in] lceType
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* LCE type. Should be one of NV2080_CTRL_CE_LCE_TYPE_* values.
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* [out] numPces
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* Number of PCEs supported per LCE
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* [out] numLces
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* Maximum number of LCEs supported by the chip for the specified LCE type.
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* [out] supportedPceMask
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* The mask of the PCEs that support the specified LCE type.
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* [out] supportedLceMask
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* The mask of the LCEs that support the specified LCE type.
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* [out] pcePerHshub
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* Numbers of PCEs from any given HSHUB that can be assigned to this LCE type.
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*
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* @return NV_OK
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*/
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#define NV2080_CTRL_CMD_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE (0x20802a0f) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID" */
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#define NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS_MESSAGE_ID (0xfU)
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|
||||
typedef struct NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS {
|
||||
NV2080_CTRL_CE_LCE_TYPE lceType;
|
||||
NvU32 numPces;
|
||||
NvU32 numLces;
|
||||
NvU32 supportedPceMask;
|
||||
NvU32 supportedLceMask;
|
||||
NvU32 pcePerHshub;
|
||||
} NV2080_CTRL_INTERNAL_CE_GET_PCE_CONFIG_FOR_LCE_TYPE_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK
|
||||
*
|
||||
* This command gets the mask of LCEs that are enabled for decomp workloads.
|
||||
* On GPUs with multiple CE shims, this interface must be called for
|
||||
* each shim.
|
||||
*
|
||||
* [in] shimInstance
|
||||
* Specify which CE shim instance to operate on.
|
||||
* [out] decompLceMask
|
||||
* Returns a 64-bit mask of which LCEs in given shim are marked as decomp CEs
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_CMD_CE_GET_DECOMP_LCE_MASK (0x20802a11) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_CE_INTERFACE_ID << 8) | NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS_MESSAGE_ID (0x11U)
|
||||
|
||||
typedef struct NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 decompLceMask, 8);
|
||||
NvU32 shimInstance;
|
||||
} NV2080_CTRL_CE_GET_DECOMP_LCE_MASK_PARAMS;
|
||||
|
||||
|
||||
|
||||
/* _ctrl2080ce_h_ */
|
||||
|
||||
@@ -156,11 +156,35 @@
|
||||
* NV2080_CTRL_FB_INFO_INDEX_EFFECTIVE_BW
|
||||
* This index is deprecated, and returns zero value.
|
||||
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK
|
||||
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0
|
||||
* NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1
|
||||
* This index is used to request the mask of currently active partitions.
|
||||
* Each active partition has an ID that's equivalent to the corresponding
|
||||
* Each active partition has an ID that's equivalent to the corresponding
|
||||
* bit position in the mask.
|
||||
* This an SMC aware attribute, thus necessary partition subscription is
|
||||
* required if the device is partitioned.
|
||||
* This value is moving from 32bits to 64bits, so PARTITION_MASK
|
||||
* (though kept for backwards compatibility on older chips), on newer chips
|
||||
* will be replaced by:
|
||||
* PARTITION_MASK_0 for the lower 32bits
|
||||
* PARTITION_MASK_1 for the upper 32bits
|
||||
* Note that PARTITION_MASK and PARTITION_MASK_0 are handled the same, and
|
||||
* use the same enum value.
|
||||
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK
|
||||
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0
|
||||
* NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1
|
||||
* This index is used to request the mask of currently active LTCs.
|
||||
* Each active LTC has an ID that's equivalent to the corresponding
|
||||
* bit position in the mask.
|
||||
* This an SMC aware attribute, thus necessary partition subscription is
|
||||
* required if the device is partitioned.
|
||||
* This value is moving from 32bits to 64bits, so LTC_MASK
|
||||
* (though kept for backwards compatibility on older chips), on newer chips
|
||||
* will be replaced by:
|
||||
* LTC_MASK_0 for the lower 32bits
|
||||
* LTC_MASK_1 for the upper 32bits
|
||||
* Note that LTC_MASK and LTC_MASK_0 are handled the same, and
|
||||
* use the same enum value.
|
||||
* NV2080_CTRL_FB_INFO_INDEX_VISTA_RESERVED_HEAP_SIZE
|
||||
* This index is used to request the amount of total RAM in kilobytes
|
||||
* reserved for internal RM allocations on Vista. This will need to
|
||||
@@ -332,9 +356,13 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_PROTECTED_MEM_SIZE_FREE_KB (0x00000034U)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_ECC_STATUS_SIZE (0x00000035U)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_IS_ZERO_FB (0x00000036U)
|
||||
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000037U)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_PARTITION_MASK_1 (0x00000037U)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_0 (NV2080_CTRL_FB_INFO_INDEX_LTC_MASK)
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U)
|
||||
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000039U)
|
||||
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x36U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
|
||||
#define NV2080_CTRL_FB_INFO_INDEX_MAX (0x38U) /* finn: Evaluated from "(NV2080_CTRL_FB_INFO_MAX_LIST_SIZE - 1)" */
|
||||
|
||||
/* valid fb RAM type values */
|
||||
#define NV2080_CTRL_FB_INFO_RAM_TYPE_UNKNOWN (0x00000000U)
|
||||
|
||||
@@ -905,6 +905,34 @@ typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS {
|
||||
NvBool bEnableAfterKeyRotation;
|
||||
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2
|
||||
*
|
||||
* This command does the same thing as @ref NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION.
|
||||
* The difference is that it doesn't take a list of clients and instead all channels belong
|
||||
* to the client on which this control call is made.
|
||||
*
|
||||
* numChannels
|
||||
* The number of valid entries in hChannelList array.
|
||||
* hChannelList
|
||||
* An array of NvHandle listing the channel handles
|
||||
* to be stopped.
|
||||
* bEnableAfterKeyRotation
|
||||
* This determines if channel is enabled by RM after it completes key rotation.
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NVOS_INVALID_STATE
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2 (0x2080111b) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS_MESSAGE_ID (0x1BU)
|
||||
|
||||
typedef struct NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS {
|
||||
NvU32 numChannels;
|
||||
NvHandle hChannelList[NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_MAX_ENTRIES];
|
||||
NvBool bEnableAfterKeyRotation;
|
||||
} NV2080_CTRL_FIFO_DISABLE_CHANNELS_FOR_KEY_ROTATION_V2_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
@@ -115,6 +115,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_MAX_LIST_SIZE (0x00000041U)
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_GROUP_ID 30:24
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_INFO_INDEX_RESERVED 31:31
|
||||
|
||||
@@ -753,7 +755,7 @@ typedef struct NV2080_CTRL_GPU_GET_ENGINES_PARAMS {
|
||||
#define NV2080_CTRL_CMD_GPU_GET_ENGINES_V2 (0x20800170U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
|
||||
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x40U
|
||||
#define NV2080_GPU_MAX_ENGINES_LIST_SIZE 0x54U
|
||||
|
||||
#define NV2080_CTRL_GPU_GET_ENGINES_V2_PARAMS_MESSAGE_ID (0x70U)
|
||||
|
||||
@@ -1126,7 +1128,7 @@ typedef struct NV2080_CTRL_GPU_QUERY_ECC_INTR_PARAMS {
|
||||
#define NV2080_CTRL_CMD_GPU_QUERY_ECC_STATUS (0x2080012fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_QUERY_ECC_STATUS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
|
||||
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001EU)
|
||||
#define NV2080_CTRL_GPU_ECC_UNIT_COUNT (0x0000001FU)
|
||||
|
||||
|
||||
|
||||
@@ -4325,6 +4327,36 @@ typedef struct NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS {
|
||||
NV2080_CTRL_GPU_CONSTRUCTED_FALCON_INFO constructedFalconsTable[NV2080_CTRL_GPU_MAX_CONSTRUCTED_FALCONS];
|
||||
} NV2080_CTRL_GPU_GET_CONSTRUCTED_FALCON_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_GPU_GET_VF_CAPS
|
||||
*
|
||||
* This command will return the MSIX capabilities for virtual function
|
||||
* Parameters:
|
||||
*
|
||||
* gfid [IN]
|
||||
* The GPU function identifier for a given VF BDF
|
||||
*
|
||||
* vfMsixCap [out]
|
||||
* This field returns the VF MSIX cap values
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
*/
|
||||
typedef struct NV2080_VF_MSIX_CAPS {
|
||||
NvU32 msix_header;
|
||||
NvU32 msix_table;
|
||||
NvU32 msix_pba;
|
||||
} NV2080_VF_MSIX_CAPS;
|
||||
|
||||
#define NV2080_CTRL_CMD_GPU_GET_VF_CAPS (0x208001b1) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS_MESSAGE_ID (0xB1U)
|
||||
|
||||
typedef struct NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS {
|
||||
NvU32 gfid;
|
||||
NV2080_VF_MSIX_CAPS vfMsixCap;
|
||||
} NV2080_CTRL_GPU_GET_VF_CAPS_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_GPU_GET_FIPS_STATUS
|
||||
*
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -310,6 +310,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
|
||||
|
||||
|
||||
|
||||
/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */
|
||||
@@ -328,6 +331,9 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
|
||||
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
|
||||
|
||||
|
||||
|
||||
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
|
||||
@@ -736,7 +742,7 @@ typedef struct NV2080_CTRL_GR_CTXSW_SMPC_MODE_PARAMS {
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_GR_GET_SM_TO_GPC_TPC_MAPPINGS (0x2080120fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 144U
|
||||
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_MAX_SM_COUNT 240U
|
||||
#define NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS_MESSAGE_ID (0xFU)
|
||||
|
||||
typedef struct NV2080_CTRL_GR_GET_SM_TO_GPC_TPC_MAPPINGS_PARAMS {
|
||||
|
||||
@@ -748,6 +748,8 @@ typedef struct NV2080_CTRL_INTERNAL_DEVICE_INFO {
|
||||
NvU32 rlEngId;
|
||||
NvU32 runlistPriBase;
|
||||
NvU32 groupId;
|
||||
NvU32 ginTargetId;
|
||||
NvU32 deviceBroadcastPriBase;
|
||||
} NV2080_CTRL_INTERNAL_DEVICE_INFO;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_DEVICE_INFO_MAX_ENTRIES 256
|
||||
|
||||
@@ -2633,6 +2635,8 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
|
||||
* To indicate whether save or restore needs to be performed.
|
||||
* [in] bUseVbios
|
||||
* Primary VGA indication from OS.
|
||||
* [out] bReturnEarly
|
||||
* To indicate caller to return after this call.
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
@@ -2646,6 +2650,7 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_SET_PCIE_RO_PARAMS {
|
||||
typedef struct NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS {
|
||||
NvBool bSave;
|
||||
NvBool bUseVbios;
|
||||
NvBool bReturnEarly;
|
||||
} NV2080_CTRL_CMD_INTERNAL_DISPLAY_PRE_UNIX_CONSOLE_PARAMS;
|
||||
|
||||
/*!
|
||||
@@ -3574,11 +3579,15 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_GET_GPU_FABRIC_PROBE_INFO_PARAMS {
|
||||
*
|
||||
* bwMode[IN]
|
||||
* - Nvlink Bandwidth mode
|
||||
*
|
||||
* bLocalEgmEnabled[IN]
|
||||
* - EGM Enablement Status that needs to be set in GSP-RM
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS_MESSAGE_ID (0xF5U)
|
||||
|
||||
typedef struct NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS {
|
||||
NvU8 bwMode;
|
||||
NvU8 bwMode;
|
||||
NvBool bLocalEgmEnabled;
|
||||
} NV2080_CTRL_CMD_INTERNAL_START_GPU_FABRIC_PROBE_INFO_PARAMS;
|
||||
|
||||
/*!
|
||||
@@ -3677,7 +3686,8 @@ typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_GET_STATIC_INFO_PARAMS {
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SIZE 3U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_KERNEL 0U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_USER 1U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 2U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_SCRUBBER 2U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_SWL_COUNT 3U
|
||||
#define NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK_LCE_COUNT 6U
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_CONF_COMPUTE_IVMASK {
|
||||
@@ -3804,22 +3814,6 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
|
||||
*
|
||||
* This command is an internal command sent from Kernel RM to Physical RM
|
||||
* to update the logical Uproc Id for the configuration.
|
||||
*
|
||||
* logicalUprocId [OUT]
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
|
||||
NvU8 logicalUprocId;
|
||||
} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
|
||||
*
|
||||
@@ -4107,7 +4101,16 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
|
||||
NvBool bInPMTransition;
|
||||
NvU32 newPMLevel;
|
||||
} NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS;
|
||||
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER (0x20800ae9) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_RECOVERY
|
||||
*
|
||||
* This command is used to perform recovery actions after the fabric has been
|
||||
* idled due to a fatal nvlink error.
|
||||
* This command accepts no parameters.
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xEA" */
|
||||
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
|
||||
@@ -4124,4 +4127,39 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 freeHeapSize, 8);
|
||||
} NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP (0x20800aeb) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM
|
||||
*
|
||||
* This command sets a new value for the specified Illumination control attribute.
|
||||
*
|
||||
* Possible status return values are:
|
||||
* NV_OK
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
*/
|
||||
#define NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID (0xECU)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS {
|
||||
NvU32 attribute;
|
||||
NvU32 value;
|
||||
} NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS;
|
||||
#define NV2080_CTRL_CMD_INTERNAL_GPU_SET_ILLUM (0x20800aecU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_GPU_SET_ILLUM_PARAMS_MESSAGE_ID" */
|
||||
/*!
|
||||
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM
|
||||
*
|
||||
* Returns the maximum number of HSHUBs in a shim instance.
|
||||
*
|
||||
* maxHshubs[OUT]
|
||||
* The maximum number of HSHUBs in a shim instance.
|
||||
*
|
||||
* @return NV_OK
|
||||
*/
|
||||
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM (0x20800a79) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS_MESSAGE_ID (0x79U)
|
||||
|
||||
typedef struct NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS {
|
||||
NvU32 maxHshubs;
|
||||
} NV2080_CTRL_INTERNAL_HSHUB_GET_MAX_HSHUBS_PER_SHIM_PARAMS;
|
||||
|
||||
/* ctrl2080internal_h */
|
||||
|
||||
@@ -214,41 +214,41 @@ typedef struct NV2080_NOCAT_JOURNAL_RECORD {
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOCATED_IDX 2
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECTED_IDX 3
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATIONS_IDX 4
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 5
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 6
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 7
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 8
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 9
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NOTIFICATION_FAIL_IDX 5
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_ALLOC_FAILED_IDX 6
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_FAILED_IDX 7
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_COLLECT_LOCKED_OUT_IDX 8
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CTRL_INSERT_RECORDS_IDX 9
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RPC_INSERT_RECORDS_IDX 10
|
||||
|
||||
// Journal Lock activity
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 10
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 11
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 12
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCKED_IDX 11
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_LOCK_UPDATED_IDX 12
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_JOURNAL_UNLOCKED_IDX 13
|
||||
|
||||
// lookup activity
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 13
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 14
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 15
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 16
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 17
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_RECORDS_IDX 14
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_BUFFER_IDX 15
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_MATCH_FOUND_IDX 16
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_NO_MATCH_IDX 17
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_CLOSEST_FOUND_IDX 18
|
||||
|
||||
// reporting activity
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 18
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 19
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 20
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REQUESTED_IDX 19
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_REPORTED_IDX 20
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_DROPPED_IDX 21
|
||||
|
||||
// update activity
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 21
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 22
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 23
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_REQ_IDX 22
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATED_IDX 23
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_UPDATE_FAILED_IDX 24
|
||||
|
||||
// general errors
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 24
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 25
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 26
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BUSY_IDX 25
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_PARAM_IDX 26
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_BAD_TYPE_IDX 27
|
||||
|
||||
// reserved entries for temporary use.
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES5_IDX 27
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES4_IDX 28
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES3_IDX 29
|
||||
#define NV2080_NOCAT_JOURNAL_REPORT_ACTIVITY_RES2_IDX 30
|
||||
|
||||
@@ -136,6 +136,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NVLINK_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_INVALID (0x00000000U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_1_0 (0x00000001U)
|
||||
@@ -145,6 +147,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_CAPS_NCI_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS
|
||||
@@ -374,6 +378,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NVLINK_VERSION_INVALID (0x000000FFU)
|
||||
|
||||
@@ -384,6 +390,8 @@ typedef struct NV2080_CTRL_NVLINK_LINK_STATUS_INFO {
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_3_1 (0x00000006U)
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_4_0 (0x00000007U)
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_5_0 (0x00000008U)
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_STATUS_NCI_VERSION_INVALID (0x000000FFU)
|
||||
|
||||
@@ -866,6 +874,118 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_COUNTERS_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_V1_MAX_COUNTER NV2080_CTRL_NVLINK_COUNTER_LP_DL
|
||||
|
||||
/* Transmit Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_PACKETS 22U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_BYTES 23U
|
||||
/* Received Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_PACKETS 24U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_BYTES 25U
|
||||
/* Link Events */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LINK_ERROR_RECOVERY_COUNTER 26U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LINK_DOWNED_COUNTER 27U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LINK_RECOVERY_SUCCESSFUL_COUNTER 28U
|
||||
/* Link Receive Errors */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_ERRORS 29U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_REMOTE_ERRORS 30U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_GENERAL_ERRORS 31U
|
||||
/* Link Receive Errors Detail */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_MALFORMED_PKT_ERROR 32U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_BUFFER_OVERRUN_ERROR 33U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RCV_VL15DROPPED_ERROR 34U
|
||||
/* Link Other Errors Detail */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LINK_INTEGRITY_ERRORS 35U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_BUFFER_OVERRUN_ERRORS 36U
|
||||
/* Link Transmit Errors */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_WAIT_TIME 37U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_XMIT_ERRORS 38U
|
||||
/* FEC Block Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_SINGLE_ERROR_BLOCKS 39U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BLOCKS 40U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_UNCORRECTED_BLOCKS 41U
|
||||
/* FEC Symbol Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_0 42U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_LANE_1 43U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_SYMBOLS_TOTAL 44U
|
||||
/* FEC Raw Error Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_0 45U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RAW_ERRORS_LANE_1 46U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_CORRECTED_BITS 47U
|
||||
/* FEC Raw BER */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_0 48U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_LANE_1 49U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RAW_BER_TOTAL 50U
|
||||
/* FEC Effective BER */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NO_ERROR_BLOCKS 51U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_ERRORS 52U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_EFFECTIVE_BER 53U
|
||||
/* Phy Symbol Errors Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_ERRORS 54U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_SYMBOL_BER 55U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_RECEIVED_BITS 56U
|
||||
/* Phy Other Errors Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_SYNC_HEADER_ERRORS 57U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_TIME_SINCE_LAST_CLEAR 58U
|
||||
/* PLR Receive Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS 59U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_UNCORRECTABLE_ERRORS 60U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_RCV_BLOCKS_WITH_ERRORS 61U
|
||||
/* PLR Transmit Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_BLOCKS 62U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_BLOCKS 63U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_XMIT_RETRY_EVENTS 64U
|
||||
/* PLR BW Loss Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_PLR_BW_LOSS 65U
|
||||
/* NVLE Rx counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_GOOD 66U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_ERROR 67U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_RX_AUTH 68U
|
||||
/* NVLE Tx Counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_GOOD 69U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_NVLE_TX_ERROR 70U
|
||||
/* FEC Histogram */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_0 71U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_1 72U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_2 73U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_3 74U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_4 75U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_5 76U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_6 77U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_7 78U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_8 79U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_9 80U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_10 81U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_11 82U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_12 83U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_13 84U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_14 85U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_HISTORY_15 86U
|
||||
|
||||
/* Throughput counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_DATA 87U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_DATA 88U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_TP_RX_RAW 89U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_TP_TX_RAW 90U
|
||||
|
||||
/* Low power counters */
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY 91U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_ENTRY_FORCE 92U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT 93U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_RECAL 94U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_EXIT_REMOTE 95U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_LP_STEADY_STATE_TIME 96U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_HIGH_SPEED_STEADY_STATE_TIME 97U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_L1_OTHER_STATE_TIME 98U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_ENTRY_TIME 99U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_EXIT_TIME 100U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_ENTRY_TIME 101U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_LOCAL_FULL_BW_EXIT_TIME 102U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_ENTRY_TIME 103U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_EXIT_TIME 104U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_ENTRY_TIME 105U
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_LP_REMOTE_FULL_BW_EXIT_TIME 106U
|
||||
|
||||
#define NV2080_CTRL_NVLINK_COUNTERS_MAX 107U
|
||||
|
||||
|
||||
|
||||
#define NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS 2U
|
||||
@@ -945,14 +1065,145 @@ typedef struct NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS {
|
||||
} NV2080_CTRL_NVLINK_INJECT_ERROR_PARAMS;
|
||||
|
||||
/* NVLINK unit list - to be used with error notifiers */
|
||||
#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_DL 0x01U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TL 0x02U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_0 0x03U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_RX_1 0x04U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_TLC_TX_0 0x05U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MIF_RX_0 0x06U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MIF_TX_0 0x07U
|
||||
#define NV2080_CTRL_NVLINK_UNIT_MINION 0x08U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_NVLINK_ERROR_INJECT_CFG
|
||||
*
|
||||
* [in] errType
|
||||
* This parameter specifies the type of error injection settings
|
||||
* [in] errSettings
|
||||
* This parameter specifies the settings for the error type in NVL5
|
||||
*/
|
||||
|
||||
typedef enum NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE {
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_TX_ERR = 1,
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_PKT_ERR = 2,
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_AUTH_TAG_ERR = 3,
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_LINK_ERR = 4,
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE_MAX = 5,
|
||||
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE;
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_ERR_TYPE errType;
|
||||
NV_DECLARE_ALIGNED(NvU64 errSettings, 8);
|
||||
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG;
|
||||
|
||||
/*
|
||||
* Tx error type settings
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE 31:28
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_NO_ERROR 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_RAW_BER 0x00000001U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_TYPE_EFFECTIVE_BER 0x00000002U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_ERR_INJECT_DURATION 27:12 // Error Injection Duration, in 10ms units.
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_MANTISSA 11:8
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_TX_ERR_BER_EXPONENT 7:0
|
||||
|
||||
/*
|
||||
* Packet error type settings
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_INJECT_COUNT 15:0
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP 16:16
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_DIS 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_STOMP_EN 0x00000001U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON 17:17
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_DIS 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_POISON_EN 0x00000001U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_PKT_ERR_CLEAR_COUNTERS 18:18
|
||||
|
||||
/*
|
||||
* Authentication error type settings
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_PIPE_INDEX 3:0
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR 4:4
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_DIS 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_AUTH_TAG_ERR_AUTH_ERR_EN 0x00000001U
|
||||
|
||||
/*
|
||||
* Link Error type settings
|
||||
*/
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN 0:0
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_DIS 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_LINK_ERR_FORCE_LINK_DOWN_EN 0x00000001U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT
|
||||
* This command causes all the same actions to occur as if the related
|
||||
* error were to occur, either fatal or recoverable.
|
||||
*
|
||||
* [in] linkMask size: 64 bits
|
||||
* Mask of the links to be configured.
|
||||
* [in] errCfg
|
||||
* This parameter specifies that the error configurations.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x81U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
|
||||
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
|
||||
} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE 1:0
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_UP 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_REQUEST 0x00000001U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_LINK_STATE_DOWN_BY_HW_ERR 0x00000002U
|
||||
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS 0:0
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_NO_ERR_INJECT 0x00000000U
|
||||
#define NV2080_CTRL_NVLINK_HW_ERROR_INJECT_STS_OPER_STS_PERFORMING_ERR_INJECT 0x00000001U
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO
|
||||
*
|
||||
* [out] txErrInfo
|
||||
* This info specifies the settings for Tx errs in NVL5
|
||||
* [out] packetErrSettings
|
||||
* This info specifies the settings for Pkt errs in NVL5
|
||||
* [out] authErrSettings
|
||||
* This info specifies the settings for NVLE errs in NVL5
|
||||
* [out] linkStatus
|
||||
* This specifies the status of the link in NVL5
|
||||
* [out] errInjectStatus
|
||||
* This specifies the status of error injection
|
||||
*/
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
|
||||
NvU32 txErrInfo;
|
||||
NvU32 packetErrInfo;
|
||||
NvU32 authErrInfo;
|
||||
NvU32 linkStatus;
|
||||
NvU32 errInjectStatus;
|
||||
} NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO;
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT
|
||||
* This command get all the current nvlink error config
|
||||
*
|
||||
* [in] linkMask size: 64 bits
|
||||
* Mask of the links to be configured.
|
||||
* [in] errCfg
|
||||
* This parameter specifies that the error configurations.
|
||||
*/
|
||||
|
||||
#define NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID (0x82U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
|
||||
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
|
||||
} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
/*
|
||||
* NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES
|
||||
@@ -3233,6 +3484,34 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_IS_REDUCED_CONFIG (0x20803046U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH 496U
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_DATA {
|
||||
NvU8 data[NV2080_CTRL_NVLINK_PRM_ACCESS_MAX_LENGTH];
|
||||
} NV2080_CTRL_NVLINK_PRM_DATA;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PAOS (0x20803047U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS_MESSAGE_ID (0x47U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 plane_ind;
|
||||
NvU8 admin_status;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 swid;
|
||||
NvU8 e;
|
||||
NvU8 fd;
|
||||
NvU8 ps_e;
|
||||
NvU8 ls_e;
|
||||
NvU8 ee_ps;
|
||||
NvU8 ee_ls;
|
||||
NvU8 ee;
|
||||
NvU8 ase;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PAOS_PARAMS;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
@@ -3246,6 +3525,621 @@ typedef struct NV2080_CTRL_NVLINK_IS_REDUCED_CONFIG_PARAMS {
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_FATAL_ERROR_RECOVERY (0x20803048U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x48" */
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLTC (0x20803053U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS_MESSAGE_ID (0x53U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 lane_mask;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 local_tx_precoding_admin;
|
||||
NvU8 local_rx_precoding_admin;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PLTC_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLM (0x20803054U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS_MESSAGE_ID (0x54U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool test_mode;
|
||||
NvU8 plane_ind;
|
||||
NvU8 port_type;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 fec_override_admin_10g_40g;
|
||||
NvU8 fec_override_admin_25g;
|
||||
NvU8 fec_override_admin_50g;
|
||||
NvU8 fec_override_admin_100g;
|
||||
NvU8 fec_override_admin_56g;
|
||||
NvU8 rs_fec_correction_bypass_admin;
|
||||
NvU16 fec_override_admin_200g_4x;
|
||||
NvU16 fec_override_admin_400g_8x;
|
||||
NvU16 fec_override_admin_50g_1x;
|
||||
NvU16 fec_override_admin_100g_2x;
|
||||
NvU16 fec_override_admin_400g_4x;
|
||||
NvU16 fec_override_admin_800g_8x;
|
||||
NvU16 fec_override_admin_100g_1x;
|
||||
NvU16 fec_override_admin_200g_2x;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLC (0x20803055U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS_MESSAGE_ID (0x55U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvBool l1_req_en;
|
||||
NvBool l1_fw_req_en;
|
||||
NvBool l1_cap_adv;
|
||||
NvBool l1_fw_cap_adv;
|
||||
NvU32 hp_queues_bitmap;
|
||||
NvU16 l1_hw_active_time;
|
||||
NvU16 l1_hw_inactive_time;
|
||||
NvU8 qem[8];
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLC_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCAM (0x20803056U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS_MESSAGE_ID (0x56U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 access_reg_group;
|
||||
NvU8 feature_group;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCAM_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTECR (0x2080305cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS_MESSAGE_ID (0x5cU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTECR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTWE (0x2080305dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS_MESSAGE_ID (0x5dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTWE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEWE (0x2080305eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS_MESSAGE_ID (0x5eU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTEWE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSDE (0x2080305fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS_MESSAGE_ID (0x5fU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTSDE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGCR (0x20803060U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS_MESSAGE_ID (0x60U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 segment;
|
||||
NvU32 GPIO_set;
|
||||
NvU32 GPIO_clear;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MGCR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTCAP (0x20803061U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS_MESSAGE_ID (0x61U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTCAP_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMTU (0x20803062U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS_MESSAGE_ID (0x62U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool itre;
|
||||
NvU8 i_e;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 protocol;
|
||||
NvU16 admin_mtu;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMTU_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MCIA (0x20803063U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS_MESSAGE_ID (0x63U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 slot_index;
|
||||
NvU8 module;
|
||||
NvBool pnv;
|
||||
NvBool l;
|
||||
NvU16 device_address;
|
||||
NvU8 page_number;
|
||||
NvU8 i2c_device_address;
|
||||
NvU16 size;
|
||||
NvU8 bank_number;
|
||||
NvBool passwd_length;
|
||||
NvU32 password;
|
||||
NvU32 dword[32];
|
||||
NvU32 password_msb;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MCIA_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMLP (0x20803064U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS_MESSAGE_ID (0x64U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 width;
|
||||
NvU8 plane_ind;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvBool m_lane_m;
|
||||
NvBool rxtx;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMLP_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_GHPKT (0x20803065U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS_MESSAGE_ID (0x65U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU16 trap_id;
|
||||
NvU8 action;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_GHPKT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PDDR (0x20803066U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS_MESSAGE_ID (0x66U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 port_type;
|
||||
NvU8 plane_ind;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 page_select;
|
||||
NvU8 module_info_ext;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PDDR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTMP (0x20803067U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS_MESSAGE_ID (0x67U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU16 sensor_index;
|
||||
NvU8 slot_index;
|
||||
NvU8 sdme;
|
||||
NvU8 weme;
|
||||
NvU8 mtr;
|
||||
NvU8 mte;
|
||||
NvU16 temperature_threshold_hi;
|
||||
NvU8 sdee;
|
||||
NvU8 tee;
|
||||
NvU16 temperature_threshold_lo;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTMP_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPTT (0x20803068U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS_MESSAGE_ID (0x68U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool le;
|
||||
NvU8 port_type;
|
||||
NvU8 lane;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvBool sw;
|
||||
NvBool dm_ig;
|
||||
NvBool p;
|
||||
NvBool e;
|
||||
NvU8 modulation;
|
||||
NvU8 prbs_mode_admin;
|
||||
NvBool prbs_fec_admin;
|
||||
NvU16 lane_rate_admin;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPTT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPCNT (0x20803069U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS_MESSAGE_ID (0x69U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 grp;
|
||||
NvU8 port_type;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 swid;
|
||||
NvU8 prio_tc;
|
||||
NvU8 grp_profile;
|
||||
NvU8 plane_ind;
|
||||
NvBool counters_cap;
|
||||
NvBool lp_gl;
|
||||
NvBool clr;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPCNT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MGIR (0x2080306aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS_MESSAGE_ID (0x6aU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MGIR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPAOS (0x2080306bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS_MESSAGE_ID (0x6bU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 port_type;
|
||||
NvU8 phy_test_mode_admin;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 swid;
|
||||
NvU8 plane_ind;
|
||||
NvU8 phy_status_admin;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPAOS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPHCR (0x2080306cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS_MESSAGE_ID (0x6cU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 plane_ind;
|
||||
NvU8 port_type;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 hist_type;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPHCR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLTP (0x2080306dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS_MESSAGE_ID (0x6dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool c_db;
|
||||
NvU8 port_type;
|
||||
NvU8 lane_speed;
|
||||
NvU8 lane;
|
||||
NvBool tx_policy;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvU8 lp_msb;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PGUID (0x2080306eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS_MESSAGE_ID (0x6eU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 plane_ind;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPRT (0x2080306fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS_MESSAGE_ID (0x6fU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool le;
|
||||
NvU8 port_type;
|
||||
NvU8 lane;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
NvBool sw;
|
||||
NvBool dm_ig;
|
||||
NvBool p;
|
||||
NvBool tun_ovr;
|
||||
NvBool s;
|
||||
NvBool e;
|
||||
NvU8 modulation;
|
||||
NvU8 prbs_mode_admin;
|
||||
NvU16 lane_rate_oper;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PTYS (0x20803070U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS_MESSAGE_ID (0x70U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 proto_mask;
|
||||
NvBool transmit_allowed;
|
||||
NvU8 plane_ind;
|
||||
NvU8 port_type;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 tx_ready_e;
|
||||
NvBool ee_tx_ready;
|
||||
NvBool an_disable_admin;
|
||||
NvU32 ext_eth_proto_admin;
|
||||
NvU32 eth_proto_admin;
|
||||
NvU16 ib_proto_admin;
|
||||
NvU16 ib_link_width_admin;
|
||||
NvBool xdr_2x_slow_admin;
|
||||
NvU8 force_lt_frames_admin;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PTYS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_SLRG (0x20803071U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS_MESSAGE_ID (0x71U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 port_type;
|
||||
NvU8 lane;
|
||||
NvU8 lp_msb;
|
||||
NvU8 pnat;
|
||||
NvU8 local_port;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_SLRG_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PMAOS (0x20803072U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS_MESSAGE_ID (0x72U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 admin_status;
|
||||
NvU8 module;
|
||||
NvU8 slot_index;
|
||||
NvBool rst;
|
||||
NvU8 e;
|
||||
NvBool ee;
|
||||
NvBool ase;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PMAOS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPLR (0x20803073U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS_MESSAGE_ID (0x73U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 plane_ind;
|
||||
NvU8 port_type;
|
||||
NvBool op_mod;
|
||||
NvBool apply_im;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU16 lb_en;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPLR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_SUPPORTED_COUNTERS (0x20803074U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID" */
|
||||
#define NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS_MESSAGE_ID (0x74U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS {
|
||||
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
|
||||
} NV2080_CTRL_NVLINK_GET_SUPPORTED_COUNTERS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MORD (0x20803075U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS_MESSAGE_ID (0x75U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU16 segment_type;
|
||||
NvU8 seq_num;
|
||||
NvBool vhca_id_valid;
|
||||
NvBool inline_dump;
|
||||
NvU16 vhca_id;
|
||||
NvU32 index1;
|
||||
NvU32 index2;
|
||||
NvU16 num_of_obj2;
|
||||
NvU16 num_of_obj1;
|
||||
NV_DECLARE_ALIGNED(NvU64 device_opaque, 8);
|
||||
NvU32 mkey;
|
||||
NV_DECLARE_ALIGNED(NvU64 address, 8);
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MORD_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CAP (0x20803076U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS_MESSAGE_ID (0x76U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvBool trace_owner;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CAP_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CONF (0x20803077U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS_MESSAGE_ID (0x77U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 trace_mode;
|
||||
NvU8 log_trace_buffer_size;
|
||||
NvU8 trace_mkey;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CONF_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTRC_CTRL (0x20803078U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS_MESSAGE_ID (0x78U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU16 modify_field_select;
|
||||
NvBool arm_event;
|
||||
NvU8 trace_status;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTRC_CTRL_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTEIM (0x20803079U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS_MESSAGE_ID (0x79U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTEIM_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIE (0x2080307aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS_MESSAGE_ID (0x7aU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 enable_all;
|
||||
NvU8 log_delay;
|
||||
NvU32 source_id_bitmask[8];
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTIE_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTIM (0x2080307bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS_MESSAGE_ID (0x7bU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 log_level;
|
||||
NvU32 log_bit_mask;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTIM_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MPSCR (0x2080307cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS_MESSAGE_ID (0x7cU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 warning_inactive_time;
|
||||
NvU8 warning_active_time;
|
||||
NvU8 critical_inactive_time;
|
||||
NvU8 critical_active_time;
|
||||
NvBool cc;
|
||||
NvU16 queue_depth_th;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID (0x7dU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PPSLS (0x2080307eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS_MESSAGE_ID (0x7eU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PPSLS_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MLPC (0x2080307fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS_MESSAGE_ID (0x7fU)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 cnt_64bit;
|
||||
NvBool stop_at_ff;
|
||||
NvBool counter_rst;
|
||||
NvBool counter_en;
|
||||
NvU8 force_count_mask;
|
||||
NvU8 cnt_type[8];
|
||||
NvU8 cnt_val[8];
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_MLPC_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_PLIB (0x20803080U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS_MESSAGE_ID (0x80U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS {
|
||||
NvBool bWrite;
|
||||
NV2080_CTRL_NVLINK_PRM_DATA prm;
|
||||
NvU16 ib_port;
|
||||
NvU8 lp_msb;
|
||||
NvU8 local_port;
|
||||
NvU8 split_num;
|
||||
} NV2080_CTRL_NVLINK_PRM_ACCESS_PLIB_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_CMD_NVLINK_GET_PLATFORM_INFO (0x20803083U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS_MESSAGE_ID (0x83U)
|
||||
|
||||
typedef struct NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS {
|
||||
NvU8 ibGuid[16];
|
||||
NvU8 rackGuid[16];
|
||||
NvU8 chassisPhysicalSlotNumber;
|
||||
NvU8 computeSlotIndex;
|
||||
NvU8 nodeIndex;
|
||||
NvU8 peerType;
|
||||
NvU8 moduleId;
|
||||
} NV2080_CTRL_NVLINK_GET_PLATFORM_INFO_PARAMS;
|
||||
|
||||
|
||||
|
||||
/* _ctrl2080nvlink_h_ */
|
||||
|
||||
@@ -288,6 +288,42 @@ typedef enum NV2080_CTRL_PERF_RATED_TDP_ACTION {
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_FLOOR = 4,
|
||||
} NV2080_CTRL_PERF_RATED_TDP_ACTION;
|
||||
|
||||
/*!
|
||||
* Enumeration VPstates - these are possible VPStates that clients can
|
||||
* request
|
||||
*/
|
||||
typedef enum NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE {
|
||||
/*!
|
||||
* Choise of the RATED TDP VPstate
|
||||
*/
|
||||
NV2080_CTRL_PERF_VPSTATE_RATED_TDP = 0,
|
||||
/*!
|
||||
* Choise of the TURBO BOOST VPstate
|
||||
*/
|
||||
NV2080_CTRL_PERF_VPSTATE_TURBO_BOOST = 1,
|
||||
/*!
|
||||
* Number of supported vpstates.
|
||||
*
|
||||
* @Note MUST ALWAYS BE LAST!
|
||||
*/
|
||||
NV2080_CTRL_PERF_VPSTATE_NUM_VPSTATES = 2,
|
||||
} NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE;
|
||||
|
||||
/*!
|
||||
* Enumeration VPstates - these are possible VPStates that clients can
|
||||
* request
|
||||
*/
|
||||
typedef struct NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST {
|
||||
/*!
|
||||
* [in] - Specified client for request.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION action;
|
||||
/*!
|
||||
* [in/out] - Client's requested action.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
|
||||
} NV2080_CTRL_PERF_RATED_TDP_CLIENT_REQUEST;
|
||||
|
||||
/*!
|
||||
* Structure describing dynamic state of the RATED_TDP feature.
|
||||
*/
|
||||
@@ -323,7 +359,12 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED or @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_LIMIT.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION output;
|
||||
/*
|
||||
* [out] - Arbitrated output VPStates of all client requests (@ref inputs).
|
||||
* This is the current VPState of the RATED_TDP feature.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE outputVPstate;
|
||||
/*!
|
||||
* [out] - Array of input client request actions, indexed via @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
|
||||
@@ -331,7 +372,15 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS {
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION inputs[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
|
||||
/*!
|
||||
* [out] - Array of input client request VPstates, indexed via @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_CLIENT_<xyz>. RM will arbitrate between these
|
||||
* requests, choosing the highest priority request != @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_DEFAULT or fallback to choosing @ref
|
||||
* NV2080_CTRL_PERF_RATED_TDP_ACTION_FORCE_EXCEED.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateTypes[NV2080_CTRL_PERF_RATED_TDP_CLIENT_NUM_CLIENTS];
|
||||
} NV2080_CTRL_PERF_RATED_TDP_STATUS_PARAMS;
|
||||
|
||||
/*!
|
||||
@@ -357,11 +406,15 @@ typedef struct NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS {
|
||||
/*!
|
||||
* [in] - Specified client for request.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
|
||||
NV2080_CTRL_PERF_RATED_TDP_CLIENT client;
|
||||
/*!
|
||||
* [in/out] - Client's requested action.
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
|
||||
NV2080_CTRL_PERF_RATED_TDP_ACTION input;
|
||||
/*
|
||||
* [in] - Specified VPState of the request
|
||||
*/
|
||||
NV2080_CTRL_PERF_RATED_TDP_VPSTATE_TYPE vPstateType;
|
||||
} NV2080_CTRL_PERF_RATED_TDP_CONTROL_PARAMS;
|
||||
|
||||
#define NV2080_CTRL_PERF_RATED_TDP_GET_CONTROL_PARAMS_MESSAGE_ID (0x6EU)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -34,6 +34,8 @@
|
||||
|
||||
/*************************** SPDM COMMANDS ************************************/
|
||||
|
||||
#include "cc_drv.h"
|
||||
|
||||
/*!
|
||||
* @brief SPDM Command Types
|
||||
*
|
||||
@@ -43,6 +45,7 @@
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_CMD_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_CMD_ID_FIPS_SELFTEST (0x6)
|
||||
|
||||
|
||||
#define RM_GSP_SPDM_CMD_ID_INVALID_COMMAND (0xFF)
|
||||
@@ -114,6 +117,25 @@ typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL {
|
||||
typedef struct RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL *PRM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* HCC FIPS Self-test.
|
||||
*/
|
||||
#define CE_FIPS_SELF_TEST_DATA_SIZE 16
|
||||
#define CE_FIPS_SELF_TEST_AUTH_TAG_SIZE 16
|
||||
#define CE_FIPS_SELF_TEST_IV_SIZE 12
|
||||
|
||||
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST {
|
||||
NvU8 cmdType;
|
||||
NvU8 isEnc;
|
||||
CC_KMB kmb;
|
||||
NvU8 text[CE_FIPS_SELF_TEST_DATA_SIZE];
|
||||
NvU8 authTag[CE_FIPS_SELF_TEST_AUTH_TAG_SIZE];
|
||||
} RM_GSP_SPDM_CMD_FIPS_SELFTEST;
|
||||
typedef struct RM_GSP_SPDM_CMD_FIPS_SELFTEST *PRM_GSP_SPDM_CMD_FIPS_SELFTEST;
|
||||
|
||||
|
||||
|
||||
/*!
|
||||
* NOTE : Do not include structure members that have alignment requirement >= 8 to avoid alignment directives
|
||||
* getting added in FINN generated structures / unions as RM_GSP_SPDM_CMD / RM_GSP_SPDM_MSG are pragma packed in
|
||||
@@ -132,6 +154,9 @@ typedef union RM_GSP_SPDM_CMD {
|
||||
RM_GSP_SPDM_CMD_CC_INIT_RM_DATA rmDataInitCmd;
|
||||
RM_GSP_SPDM_CMD_CC_HEARTBEAT_CTRL ccHeartbeatCtrl;
|
||||
|
||||
|
||||
RM_GSP_SPDM_CMD_FIPS_SELFTEST ccFipsTest;
|
||||
|
||||
} RM_GSP_SPDM_CMD;
|
||||
typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
|
||||
|
||||
@@ -149,6 +174,7 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_CTRL (0x3)
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_INIT_RM_DATA (0x4)
|
||||
#define RM_GSP_SPDM_MSG_ID_CC_HEARTBEAT_CTRL (0x5)
|
||||
#define RM_GSP_SPDM_MSG_ID_FIPS_SELFTEST (0x6)
|
||||
|
||||
|
||||
|
||||
@@ -168,20 +194,20 @@ typedef union RM_GSP_SPDM_CMD *PRM_GSP_SPDM_CMD;
|
||||
* SPDM message structure.
|
||||
*/
|
||||
typedef struct RM_GSP_SPDM_MSG {
|
||||
NvU8 msgType;
|
||||
NvU8 msgType;
|
||||
|
||||
// status returned from GSP message infrastructure.
|
||||
NvU32 status;
|
||||
NvU32 status;
|
||||
|
||||
NvU32 rsvd1;
|
||||
NvU32 rsvd1;
|
||||
|
||||
NvU32 rsvd2;
|
||||
NvU32 rsvd2;
|
||||
|
||||
NvU32 rsvd3;
|
||||
NvU32 rsvd3;
|
||||
|
||||
NvU32 rsvd4;
|
||||
NvU32 rsvd4;
|
||||
|
||||
NvBool rsvd5;
|
||||
NvU32 rsvd5;
|
||||
} RM_GSP_SPDM_MSG;
|
||||
typedef struct RM_GSP_SPDM_MSG *PRM_GSP_SPDM_MSG;
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -61,7 +61,7 @@
|
||||
#define NV2080_CTRL_MAX_VMMU_SEGMENTS 384
|
||||
|
||||
/* Must match NV2080_ENGINE_TYPE_LAST from cl2080.h */
|
||||
#define NV2080_GPU_MAX_ENGINES 0x40
|
||||
#define NV2080_GPU_MAX_ENGINES 0x54
|
||||
|
||||
#define NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAMS_MESSAGE_ID (0x1U)
|
||||
|
||||
@@ -85,6 +85,8 @@ typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_BOOTLOAD_GSP_VGPU_PLUGIN_TASK_PARAM
|
||||
NV_DECLARE_ALIGNED(NvU64 initTaskLogBuffSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffOffset, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 vgpuTaskLogBuffSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffOffset, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 kernelLogBuffSize, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryPhysAddr, 8);
|
||||
NV_DECLARE_ALIGNED(NvU64 migRmHeapMemoryLength, 8);
|
||||
NvBool bDeviceProfilingEnabled;
|
||||
|
||||
Reference in New Issue
Block a user