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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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560.28.03
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@@ -110,15 +110,15 @@ typedef enum _TEGRASOC_WHICH_CLK
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TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTPN,
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TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTA,
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TEGRASOC_WHICH_CLK_SPPLL0_VCO,
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TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN,
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TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTA,
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TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTB,
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TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN,
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TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN,
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TEGRASOC_WHICH_CLK_SPPLL0_DIV27,
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TEGRASOC_WHICH_CLK_SPPLL1_DIV27,
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TEGRASOC_WHICH_CLK_SPPLL0_DIV10,
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TEGRASOC_WHICH_CLK_SPPLL0_DIV25,
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TEGRASOC_WHICH_CLK_SPPLL0_DIV27,
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TEGRASOC_WHICH_CLK_SPPLL1_VCO,
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TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN,
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TEGRASOC_WHICH_CLK_SPPLL1_DIV27,
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TEGRASOC_WHICH_CLK_VPLL0_REF,
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TEGRASOC_WHICH_CLK_VPLL0,
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TEGRASOC_WHICH_CLK_VPLL1,
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@@ -132,7 +132,7 @@ typedef enum _TEGRASOC_WHICH_CLK
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TEGRASOC_WHICH_CLK_DSI_PIXEL,
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TEGRASOC_WHICH_CLK_PRE_SOR0,
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TEGRASOC_WHICH_CLK_PRE_SOR1,
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TEGRASOC_WHICH_CLK_DP_LINK_REF,
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TEGRASOC_WHICH_CLK_DP_LINKA_REF,
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TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT,
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TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO,
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TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M,
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@@ -143,7 +143,7 @@ typedef enum _TEGRASOC_WHICH_CLK
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TEGRASOC_WHICH_CLK_PLLHUB,
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TEGRASOC_WHICH_CLK_SOR0,
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TEGRASOC_WHICH_CLK_SOR1,
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TEGRASOC_WHICH_CLK_SOR_PAD_INPUT,
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TEGRASOC_WHICH_CLK_SOR_PADA_INPUT,
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TEGRASOC_WHICH_CLK_PRE_SF0,
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TEGRASOC_WHICH_CLK_SF0,
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TEGRASOC_WHICH_CLK_SF1,
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@@ -332,7 +332,9 @@ typedef struct nv_soc_irq_info_s {
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#define NV_MAX_SOC_IRQS 6
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#define NV_MAX_DPAUX_NUM_DEVICES 4
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#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING
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#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2
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#define NV_IGPU_LEGACY_STALL_IRQ 70
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#define NV_IGPU_MAX_STALL_IRQS 3
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@@ -495,12 +497,6 @@ typedef struct nv_state_t
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} iommus;
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} nv_state_t;
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// These define need to be in sync with defines in system.h
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#define OS_TYPE_LINUX 0x1
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#define OS_TYPE_FREEBSD 0x2
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#define OS_TYPE_SUNOS 0x3
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#define OS_TYPE_VMWARE 0x4
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#define NVFP_TYPE_NONE 0x0
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#define NVFP_TYPE_REFCOUNTED 0x1
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#define NVFP_TYPE_REGISTERED 0x2
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@@ -893,8 +889,6 @@ void NV_API_CALL nv_cap_drv_exit(void);
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NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *);
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NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *);
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NvU32 NV_API_CALL nv_get_os_type(void);
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void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end);
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void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *);
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@@ -1081,6 +1075,9 @@ NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t
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void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *);
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void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *);
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// Host1x specific functions.
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NV_STATUS NV_API_CALL nv_get_syncpoint_aperture(NvU32, NvU64 *, NvU64 *, NvU32 *);
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#if defined(NVCPU_X86_64)
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static inline NvU64 nv_rdtsc(void)
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