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550.54.14

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This commit is contained in:
Bernhard Stoeckner
2024-02-23 16:37:56 +01:00
parent 91676d6628
commit 476bd34534
186 changed files with 42509 additions and 37629 deletions
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22
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r551_06
#define NV_BUILD_BRANCH r551_40
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r551_06
#define NV_PUBLIC_BRANCH r551_40
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_06-132"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r551_40-170"
#define NV_BUILD_CHANGELIST_NUM (33933991)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_06-132"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r551_40-170"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33933991)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r551_06-14"
#define NV_BUILD_CHANGELIST_NUM (33773930)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "551.23"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33773930)
#define NV_BUILD_BRANCH_VERSION "r551_40-13"
#define NV_BUILD_CHANGELIST_NUM (33924744)
#define NV_BUILD_TYPE "Nightly"
#define NV_BUILD_NAME "r551_40-240221"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (33921227)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

28
src/common/inc/nvSemaphoreCommon.h
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@@ -94,8 +94,9 @@ static inline void NvTimeSemFermiSetMaxSubmitted(
NvTimeSemFermiSetMaxSubmittedVal(&report->timer, value);
}
static inline NvU64 NvTimeSemFermiGetPayload(
NvReportSemaphore32 *report)
static inline NvU64 NvTimeSemFermiGetPayloadVal(
volatile void *payloadPtr,
volatile void *maxSubmittedPtr)
{
// The ordering of the two operations below is critical. Other threads
// may be submitting GPU work that modifies the semaphore value, or
@@ -129,11 +130,11 @@ static inline NvU64 NvTimeSemFermiGetPayload(
// adjust the max submitted value back down if a wrap occurs between these
// two operations, but has no way to bump the max submitted value up if a
// wrap occurs with the opposite ordering.
NvU64 current = report->payload;
NvU64 current = *(volatile NvU32*)payloadPtr;
// Use an atomic exchange to ensure the 64-bit read is atomic even on 32-bit
// CPUs.
NvU64 submitted = (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)&report->timer, 0ll, 0ll);
__NVatomicCompareExchange64((volatile NvS64 *)maxSubmittedPtr, 0ll, 0ll);
nvAssert(!(current & 0xFFFFFFFF00000000ull));
@@ -152,6 +153,12 @@ static inline NvU64 NvTimeSemFermiGetPayload(
return current;
}
static inline NvU64 NvTimeSemFermiGetPayload(
NvReportSemaphore32 *report)
{
return NvTimeSemFermiGetPayloadVal(&report->payload, &report->timer);
}
static inline void NvTimeSemFermiSetPayload(
NvReportSemaphore32 *report,
const NvU64 payload)
@@ -167,12 +174,19 @@ static inline void NvTimeSemFermiSetPayload(
* Volta and up.
*/
static inline NvU64 NvTimeSemVoltaGetPayloadVal(
volatile void *payloadPtr)
{
nvAssert(payloadPtr);
return (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)payloadPtr,
0, 0);
}
static inline NvU64 NvTimeSemVoltaGetPayload(
NvReportSemaphore64 *report)
{
return (NvU64)
__NVatomicCompareExchange64((volatile NvS64 *)&report->reportValue,
0, 0);
return NvTimeSemVoltaGetPayloadVal(&report->reportValue);
}
static inline void NvTimeSemVoltaSetPayload(

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.40.07"
#define NV_VERSION_STRING "550.54.14"
#else

32
src/common/inc/swref/published/ampere/ga100/dev_ctxsw_prog.h Normal file
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@@ -0,0 +1,32 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2023 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef GA100_DEV_CTXSW_PROG_H
#define GA100_DEV_CTXSW_PROG_H
#define NV_CTXSW_TIMESTAMP_BUFFER_RD_WR_POINTER 30:0 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE 31:31 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_ENABLED 0x1 /* */
#define NV_CTXSW_TIMESTAMP_BUFFER_MAILBOX1_TRACE_FEATURE_DISABLED 0x0 /* */
#endif

11
src/common/inc/swref/published/ampere/ga100/dev_vm.h
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@@ -123,9 +123,10 @@
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_VIRTUAL_FUNCTION_PRIV_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_VIRTUAL_FUNCTION_TIME_0 0x30080 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_TIME_1 0x30084 /* R--4R */
#define NV_VIRTUAL_FUNCTION_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_VIRTUAL_FUNCTION_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#endif // __ga100_dev_vm_h__

85
src/common/modeset/timing/nvt_edid.c
View File

@@ -991,7 +991,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
pInfo->cc_white_y |= (p->Chromaticity[1] & NVT_PVT_EDID_CC_WHITE_Y1_Y0_MASK) >> NVT_PVT_EDID_CC_WHITE_Y1_Y0_SHIFT;
// copy established timings
pInfo->established_timings_1_2 = (NvU16)p->bEstablishedTimings1 << 8;
pInfo->established_timings_1_2 = (NvU16)p->bEstablishedTimings1 << 8;
pInfo->established_timings_1_2 |= (NvU16)p->bEstablishedTimings2;
// copy manuf reserved timings
@@ -1039,7 +1039,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
p861Info = (k == 0) ? &pInfo->ext861 : &pInfo->ext861_2;
get861ExtInfo(pExt, sizeof(EDIDV1STRUC), p861Info);
// HF EEODB is present in edid v1.3 and v1.4 does not need this.Also, it is always present in the 1st CTA extension block.
if (j == 1 && pInfo->version == NVT_EDID_VER_1_3)
{
@@ -1106,11 +1106,6 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
pInfo->ext_displayid20.interface_features.yuv420_min_pclk = 0;
}
if (pInfo->ext861.revision == 0 && pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
{
pInfo->ext861.revision = NVT_CEA861_REV_B;
}
if (pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
{
pInfo->ext861.basic_caps |= pInfo->ext_displayid20.basic_caps;
@@ -1157,7 +1152,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
}
}
// Copy all the timings(could include type 7/8/9/10) from displayid20->timings[] to pEdidInfo->timings[]
// Copy all the timings(could include type 7/8/9/10) from displayid20->timings[] to pEdidInfo->timings[]
for (i = 0; i < pInfo->ext_displayid20.total_timings; i++)
{
if (!assignNextAvailableTiming(pInfo, &(pInfo->ext_displayid20.timing[i])))
@@ -1215,7 +1210,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
CODE_SEGMENT(PAGE_DD_CODE)
void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
{
{
NvU32 i, j, data;
for (i = 0; i < pInfo->total_timings; i++)
@@ -1226,8 +1221,8 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
case NVT_TYPE_HDMI_STEREO:
case NVT_TYPE_HDMI_EXT:
// VTB timing use the base EDID (block 0) to determine the color format support
case NVT_TYPE_EDID_VTB_EXT:
case NVT_TYPE_EDID_VTB_EXT_STD:
case NVT_TYPE_EDID_VTB_EXT:
case NVT_TYPE_EDID_VTB_EXT_STD:
case NVT_TYPE_EDID_VTB_EXT_DTD:
case NVT_TYPE_EDID_VTB_EXT_CVT:
// pInfo->u.feature_ver_1_3.color_type provides mono, rgb, rgy, undefined
@@ -1245,7 +1240,7 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
}
updateBpcForTiming(pInfo, i);
break;
default:
default:
// * the displayID_v1.3/v2.0 EDID extension need to follow the EDID bpc definition.
// * all other default to base edid
updateBpcForTiming(pInfo, i);
@@ -1319,7 +1314,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
for (j = 0; j < pInfo->total_timings; j++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD &&
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD &&
NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
{
return NV_TRUE;
@@ -1335,7 +1330,7 @@ NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
for (j = 0; j < pInfo->total_timings; j++)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST &&
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST &&
NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
{
return NV_TRUE;
@@ -1405,7 +1400,7 @@ void updateBpcForTiming(NVT_EDID_INFO *pInfo, NvU32 index)
}
}
else if ((pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED ||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_UNDEFINED) &&
p861Info->revision >= NVT_CEA861_REV_A)
{
@@ -1462,7 +1457,7 @@ NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr,
// the timing mapping index :
//
// native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators
// native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators
// if the Source supports NVRDB and the NVRDB was found in the E-EDID
// preferred_cta - the "prefer SVD" in CTA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB)
// preferred_displayid_dtd - the "prefer detailed timing of DispalyID" extension
@@ -1546,7 +1541,7 @@ NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr,
if (native_cta == pEdidInfo->total_timings && NVT_NATIVE_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
{
native_cta = i;
}
}
if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
{
@@ -2063,10 +2058,10 @@ NVT_STATUS NvTiming_GetEDIDBasedASPRTiming( NvU16 width, NvU16 height, NvU16 rr,
*
* @brief check EDID raw data is valid or not, and it will return the err flags if it existed
* @param pEdid : this is a pointer to EDID data
* @param length : read length of EDID
* @param length : read length of EDID
* @param bIsTrongValidation : true - added more check
* false- only header and checksum and size check
*
*
*/
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation)
@@ -2086,12 +2081,12 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
return ret;
}
// check the EDID version and signature
// check the EDID version and signature
if (getEdidVersion(pEdid, &version) != NVT_STATUS_SUCCESS)
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION);
return ret;
}
}
// check block 0 checksum value
if (!isChecksumValid(pEdid))
@@ -2239,11 +2234,11 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
/**
*
* @brief sanity check EDID binary frequently used data block is valid or not,
* @brief sanity check EDID binary frequently used data block is valid or not,
* and it will return error checkpoint flag if it existed
* @param pEdid : this is a pointer to EDID raw data
* @param length : read length of EDID
*
*
*/
CODE_SEGMENT(PAGE_DD_CODE)
NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
@@ -2255,7 +2250,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
DETAILEDTIMINGDESCRIPTOR *pDTD;
// For CTA861
NvU8 ctaDTD_Offset;
NvU8 *pData_collection;
NvU8 *pData_collection;
NvU32 ctaBlockTag, ctaPayload, vic;
// For DisplayID
DIDEXTENSION *pDisplayid;
@@ -2283,7 +2278,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION);
}
// 18bytes in DTD or Display Descriptor check
for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++)
{
@@ -2313,7 +2308,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
}
}
else
{
{
pLdd = (EDID_LONG_DISPLAY_DESCRIPTOR *)&p->DetailedTimingDesc[i];
// This block is a display descriptor, validate
@@ -2327,7 +2322,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
NvU8 max_v_rate_offset, min_v_rate_offset, max_h_rate_offset, min_h_rate_offset;
// add 255Hz offsets as needed before doing the check, use descriptor->rsvd2
nvt_assert(!(pLdd->rsvd2 & 0xF0));
nvt_assert(!(pLdd->rsvd2 & 0xF0));
max_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MAX ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0;
min_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MIN ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0;
@@ -2340,19 +2335,19 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
pRangeLimit->maxHRate == 0)
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_RANGE_LIMIT);
}
}
}
}
}
// extension and size check
if ((NvU32)(p->bExtensionFlag + 1) * sizeof(EDIDV1STRUC) > length)
{
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT);
}
// we shall not trust any extension blocks with wrong input EDID size
if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) ||
// we shall not trust any extension blocks with wrong input EDID size
if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) ||
NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT))
return ret;
@@ -2384,7 +2379,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
// validate SVD block
ctaBlockTag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(((EIA861EXTENSION *)pExt)->data[0]);
pData_collection = ((EIA861EXTENSION *)pExt)->data;
while ((ctaDTD_Offset - 4) > 0 && pData_collection != &pExt[ctaDTD_Offset] &&
ctaBlockTag > NVT_CEA861_TAG_RSVD && ctaBlockTag <= NVT_CEA861_TAG_EXTENDED_FLAG)
{
@@ -2451,7 +2446,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD);
else
{
// check the max image size and
// check the max image size and
if (p->bMaxHorizImageSize != 0 && p->bMaxVertImageSize != 0)
{
NvU16 hDTDImageSize = (pDTD->bDTHorizVertImage & 0xF0) << 4 | pDTD->bDTHorizontalImage;
@@ -2466,7 +2461,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
if(!isChecksumValid(pExt))
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM);
break;
break;
case NVT_EDID_EXTENSION_DISPLAYID:
pDisplayid = ((DIDEXTENSION *)pExt);
if (pDisplayid->ext_count != 0)
@@ -2483,10 +2478,10 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
{
if ((pDisplayid->struct_version & 0xFF) == 0x21)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION);
did2ExtCount++;
if (pDisplayid->use_case == 0 && did2ExtCount == 1)
if (pDisplayid->use_case == 0 && did2ExtCount == 1)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_USE_CASE);
// check the DisplayId2 valid timing
@@ -2506,7 +2501,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE7);
if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_ADAPTIVE_SYNC);
@@ -2527,9 +2522,9 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
}
// if the first tag failed, ignore all the tags afterward then
if (!bAllZero &&
(pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY ||
(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE &&
if (!bAllZero &&
(pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY ||
(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE &&
pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC &&
pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA)) &&
(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
@@ -2537,7 +2532,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TAG);
continue;
}
}
}
else if ((pDisplayid->struct_version & 0xFF) == 0x12 || (pDisplayid->struct_version & 0xFF) == 0x13)
{
if ((pDisplayid->struct_version & 0xFF) == 0x13)
@@ -2559,7 +2554,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
if (pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_RANGE_LIMITS)
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
// add more data blocks tag here to evaluate
}
pData_collection += block_length;
@@ -2580,7 +2575,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
if (!bAllZero &&
pHeader->type > NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY &&
pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA &&
pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC &&
pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC &&
(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
{
ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID13_TAG);
@@ -2939,7 +2934,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
// Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year
NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6);
// Wipe out the checksums
CommonEDIDBuffer[CommonEDIDBuffer[1]+5/*mandatory bytes*/-1] = 0;
CommonEDIDBuffer[0xFF] = 0;
@@ -2954,7 +2949,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
// displayId2 standalone uses 256 length sections
commonEDIDBufferSize = 256;
}
else
else
{
// Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year
NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6);

82
src/common/modeset/timing/nvt_edidext_displayid.c
View File

@@ -111,7 +111,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
nvt_assert((timingIdx) <= COUNT(pInfo->timing));
if ((pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED ||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
pInfo->ext861.valid.H14B_VSDB || pInfo->ext861.valid.H20_HF_VSDB) && pInfo->ext861.revision >= NVT_CEA861_REV_A)
{
if (!pInfo->ext_displayid.supported_displayId2_0)
@@ -153,7 +153,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_10b,
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_12b,
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_14b,
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_16b);
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_16b);
}
}
@@ -174,7 +174,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
pDisplayIdInfo->u4.display_interface.ycbcr422_depth.support_14b,
pDisplayIdInfo->u4.display_interface.ycbcr422_depth.support_16b);
}
else
else
{
// yuv444
UPDATE_BPC_FOR_COLORFORMAT(pT->etc.yuv444, 0, /* yuv444 does not support 6bpc */
@@ -264,7 +264,7 @@ static NVT_STATUS parseDisplayIdSection(DISPLAYID_SECTION * section,
* @brief Parses a displayID data block
* @param block The DisplayID data block to parse
* @param max_length The indicated total length of the each data block for checking
* @param pLength return the indicated length of the each data block
* @param pLength return the indicated length of the each data block
* @param pEdidInfo EDID struct containing DisplayID information and
* the timings or validation purpose if it is NULL
*/
@@ -285,7 +285,7 @@ NVT_STATUS parseDisplayIdBlock(NvU8* pBlock,
return NVT_STATUS_ERR;
pInfo = pEdidInfo == NULL ? NULL : &pEdidInfo->ext_displayid;
*pLength = hdr->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN;
switch (hdr->type)
@@ -386,9 +386,9 @@ static NVT_STATUS parseDisplayIdColorChar(NvU8 * block, NVT_DISPLAYID_INFO *pInf
for (i = 0; i < prim_num; i++)
{
x_p = (blk->points)[i].color_x_bits_low +
x_p = (blk->points)[i].color_x_bits_low +
(DRF_VAL(T_DISPLAYID, _COLOR, _POINT_X, (blk->points)[i].color_bits_mid) << 8);
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
((blk->points)[i].color_y_bits_high << 4);
pInfo->primaries[i].x = x_p;
pInfo->primaries[i].y = y_p;
@@ -396,9 +396,9 @@ static NVT_STATUS parseDisplayIdColorChar(NvU8 * block, NVT_DISPLAYID_INFO *pInf
for (j = 0; j < wp_num; j++)
{
x_p = (blk->points)[i].color_x_bits_low +
x_p = (blk->points)[i].color_x_bits_low +
(DRF_VAL(T_DISPLAYID, _COLOR, _POINT_X, (blk->points)[i].color_bits_mid) << 8);
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
((blk->points)[i].color_y_bits_high << 4);
pInfo->white_points[pInfo->total_primaries + j].x = x_p;
pInfo->white_points[pInfo->total_primaries + j].y = y_p;
@@ -508,7 +508,6 @@ static NVT_STATUS parseDisplayIdTiming1(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS parseDisplayIdTiming1Descriptor(DISPLAYID_TIMING_1_DESCRIPTOR * type1, NVT_TIMING *pT)
{
NvU32 totalPixels_in_2_fields;
if (type1 == NULL || pT == NULL)
return NVT_STATUS_ERR;
@@ -569,30 +568,17 @@ static NVT_STATUS parseDisplayIdTiming1Descriptor(DISPLAYID_TIMING_1_DESCRIPTOR
}
// the refresh rate
if (pT->interlaced)
{
// in interlaced mode, adjust for one extra line in every other frame. pT->VTotal is field based here
totalPixels_in_2_fields = (NvU32)pT->HTotal * ((NvU32)pT->VTotal * 2 + 1);
// calculate the field rate in interlaced mode
pT->etc.rr = (NvU16)axb_div_c(pT->pclk * 2, 10000, totalPixels_in_2_fields);
pT->etc.rrx1k = axb_div_c(pT->pclk * 2, 10000000, totalPixels_in_2_fields);
}
else
{
// calculate frame rate in progressive mode
// in progressive mode filed = frame
pT->etc.rr = (NvU16)axb_div_c(pT->pclk, 10000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c(pT->pclk, 10000000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
}
pT->etc.rr = NvTiming_CalcRR(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
pT->etc.rrx1k = NvTiming_CalcRRx1k(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
pT->etc.name[39] = '\0';
pT->etc.rep = 0x1; // bit mask for no pixel repetition
pT->etc.status = NVT_STATUS_DISPLAYID_1;
// Unlike the PTM in EDID base block, DisplayID type I/II preferred timing does not have dependency on sequence
// so we'll just update the preferred flag, not sequence them
//pT->etc.status = NVT_STATUS_DISPLAYID_1N(1);
pT->etc.flag |= type1->options.is_preferred_detailed_timing ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
/* Fields currently not used. Uncomment them for future use
type1->options.stereo_support;
*/
@@ -651,7 +637,6 @@ static NVT_STATUS parseDisplayIdTiming2(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
CODE_SEGMENT(PAGE_DD_CODE)
static NVT_STATUS parseDisplayIdTiming2Descriptor(DISPLAYID_TIMING_2_DESCRIPTOR * type2, NVT_TIMING *pT)
{
NvU32 totalPixels_in_2_fields;
if (type2 == NULL || pT == NULL)
return NVT_STATUS_ERR;
@@ -679,32 +664,19 @@ static NVT_STATUS parseDisplayIdTiming2Descriptor(DISPLAYID_TIMING_2_DESCRIPTOR
pT->interlaced = type2->options.interface_frame_scanning_type;
// the refresh rate
if (pT->interlaced)
{
// in interlaced mode, adjust for one extra line in every other frame. pT->VTotal is field based here
totalPixels_in_2_fields = (NvU32)pT->HTotal * ((NvU32)pT->VTotal * 2 + 1);
// calculate the field rate in interlaced mode
pT->etc.rr = (NvU16)axb_div_c(pT->pclk * 2, 10000, totalPixels_in_2_fields);
pT->etc.rrx1k = axb_div_c(pT->pclk * 2, 10000000, totalPixels_in_2_fields);
}
else
{
// calculate frame rate in progressive mode
// in progressive mode filed = frame
pT->etc.rr = (NvU16)axb_div_c(pT->pclk, 10000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
pT->etc.rrx1k = axb_div_c(pT->pclk, 10000000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
}
pT->etc.rr = NvTiming_CalcRR(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
pT->etc.rrx1k = NvTiming_CalcRRx1k(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
pT->etc.aspect = 0;
pT->etc.name[39] = '\0';
pT->etc.rep = 0x1; // Bit mask for no pixel repetition
pT->etc.status = NVT_STATUS_DISPLAYID_2;
// Unlike the PTM in EDID base block, DisplayID type I/II preferred timing does not have dependency on sequence
// so we'll just update the preferred flag, not sequence them
//pT->etc.status = NVT_STATUS_DISPLAYID_1N(1);
pT->etc.flag |= type2->options.is_preferred_detailed_timing ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
/* Fields currently not used. Uncomment them for future use
type1->options.stereo_support;
*/
@@ -861,12 +833,12 @@ static NVT_STATUS parseDisplayIdTiming5Descriptor(DISPLAYID_TIMING_5_DESCRIPTOR
{
NvU32 width, height, rr;
NvBool is1000div1001 = NV_FALSE;
// we don't handle stereo type nor custom reduced blanking yet
//NvU8 stereoType, formula;
//stereoType = (desc->optns & NVT_DISPLAYID_TIMING_5_STEREO_SUPPORT_MASK);
//formula = desc->optns & NVT_DISPLAYID_TIMING_5_FORMULA_SUPPORT_MASK;
if (desc->optns & NVT_DISPLAYID_TIMING_5_FRACTIONAL_RR_SUPPORT_MASK)
{
is1000div1001 = NV_TRUE;
@@ -892,7 +864,7 @@ static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
for (i = 0; i * sizeof(DISPLAYID_TIMING_5_DESCRIPTOR) < blk->header.data_bytes; i++)
{
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
if (parseDisplayIdTiming5Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS)
{
if (pEdidInfo == NULL) continue;
@@ -1030,7 +1002,7 @@ static NVT_STATUS parseDisplayIdRangeLimits(NvU8 * block, NVT_DISPLAYID_INFO *pI
rl = pInfo->range_limits + pInfo->rl_num;
(pInfo->rl_num)++;
rl->pclk_min = minPclk;
rl->pclk_max = maxPclk;
@@ -1105,7 +1077,7 @@ static NVT_STATUS parseDisplayIdDeviceData(NvU8 * block, NVT_DISPLAYID_INFO *pIn
pInfo->device_op_mode = DRF_VAL(T_DISPLAYID, _DEVICE, _OPERATING_MODE, blk->operating_mode);
pInfo->support_backlight = DRF_VAL(T_DISPLAYID, _DEVICE, _BACKLIGHT, blk->operating_mode);
pInfo->support_intensity = DRF_VAL(T_DISPLAYID, _DEVICE, _INTENSITY, blk->operating_mode);
pInfo->horiz_pixel_count = blk->horizontal_pixel_count;
pInfo->vert_pixel_count = blk->vertical_pixel_count;
@@ -1278,7 +1250,7 @@ static NVT_STATUS parseDisplayIdStereo(NvU8 * block, NVT_DISPLAYID_INFO *pInfo)
nvt_assert(0);
return NVT_STATUS_ERR;
}
return NVT_STATUS_SUCCESS;
}
@@ -1322,7 +1294,7 @@ static NVT_STATUS parseDisplayIdTiledDisplay(NvU8 * block, NVT_DISPLAYID_INFO *p
pInfo->bezel_info.left = (blk->bezel_info.left * blk->bezel_info.pixel_density) / 10;
pInfo->tile_topology_id.vendor_id = (blk->topology_id.vendor_id[2] << 16) |
(blk->topology_id.vendor_id[1] << 8 ) |
(blk->topology_id.vendor_id[1] << 8 ) |
blk->topology_id.vendor_id[0];
pInfo->tile_topology_id.product_id = (blk->topology_id.product_id[1] << 8) | blk->topology_id.product_id[0];
@@ -1350,7 +1322,7 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo)
if (pInfo == NULL) return NVT_STATUS_SUCCESS;
p861info = &pInfo->ext861;
pInfo->ext_displayid.cea_data_block_present = 1;
p861info->revision = blk->revision;
@@ -1366,7 +1338,7 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo)
//parse HDR related information from the HDR static metadata data block
parseCea861HdrStaticMetadataDataBlock(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
// base video
parse861bShortTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
// yuv420-only video
@@ -1422,7 +1394,7 @@ static NVT_STATUS parseDisplayIdDisplayInterfaceFeatures(NvU8 * block, NVT_DISPL
// Minimum Pixel Rate at Which YCbCr 4:2:0 Encoding Is Supported
pInfo->u4.display_interface_features.minimum_pixel_rate_ycbcr420 = blk->minimum_pixel_rate_ycbcr420;
// Audio capability
pInfo->u4.display_interface_features.audio_capability.support_32khz = DRF_VAL(T_DISPLAYID, _INTERFACE_FEATURES, _AUDIO_SUPPORTED_32KHZ, blk->supported_audio_capability);
pInfo->u4.display_interface_features.audio_capability.support_44_1khz = DRF_VAL(T_DISPLAYID, _INTERFACE_FEATURES, _AUDIO_SUPPORTED_44_1KHZ, blk->supported_audio_capability);

8
src/common/modeset/timing/nvt_util.c
View File

@@ -235,7 +235,7 @@ NvU16 NvTiming_CalcRR(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal)
if (totalPixelsIn2Fields != 0)
{
rr = (NvU16)axb_div_c(pclk * 2, 10000, totalPixelsIn2Fields);
rr = (NvU16)axb_div_c_64((NvU64)pclk * 2, (NvU64)10000, (NvU64)totalPixelsIn2Fields);
}
}
else
@@ -244,7 +244,7 @@ NvU16 NvTiming_CalcRR(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal)
if (totalPixels != 0)
{
rr = (NvU16)axb_div_c(pclk, 10000, totalPixels);
rr = (NvU16)axb_div_c_64((NvU64)pclk, (NvU64)10000, (NvU64)totalPixels);
}
}
return rr;
@@ -261,7 +261,7 @@ NvU32 NvTiming_CalcRRx1k(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTota
if (totalPixelsIn2Fields != 0)
{
rrx1k = (NvU32)axb_div_c(pclk * 2, 10000000, totalPixelsIn2Fields);
rrx1k = (NvU32)axb_div_c_64((NvU64)pclk * 2, (NvU64)10000000, (NvU64)totalPixelsIn2Fields);
}
}
else
@@ -270,7 +270,7 @@ NvU32 NvTiming_CalcRRx1k(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTota
if (totalPixels != 0)
{
rrx1k = (NvU32)axb_div_c(pclk, 10000000, totalPixels);
rrx1k = (NvU32)axb_div_c_64((NvU64)pclk, (NvU64)10000000, (NvU64)totalPixels);
}
}

4
src/common/nvlink/interface/nvlink.h
View File

@@ -70,8 +70,8 @@ extern "C" {
// Link Transition Timeouts in miliseconds
#define NVLINK_TRANSITION_OFF_TIMEOUT 1
#define NVLINK_TRANSITION_SAFE_TIMEOUT 300
#define NVLINK_TRANSITION_HS_TIMEOUT 8000
#define NVLINK_TRANSITION_SAFE_TIMEOUT 70
#define NVLINK_TRANSITION_HS_TIMEOUT 7000
#define NVLINK_TRANSITION_ACTIVE_PENDING 2000
#define NVLINK_TRANSITION_POST_HS_TIMEOUT 70

18
src/common/nvswitch/kernel/cci/cables/cci_common.c
View File

@@ -222,8 +222,7 @@ _cci_module_cable_detect
}
default:
{
NVSWITCH_ASSERT(0);
break;
return -NVL_ERR_NOT_SUPPORTED;
}
}
@@ -348,8 +347,9 @@ _cci_module_identify
// Mark as faulty
device->pCci->isFaulty[moduleId] = NV_TRUE;
NVSWITCH_PRINT(device, ERROR,
"%s: Module HW check failed. Module %d\n", __FUNCTION__, moduleId);
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE,
"Module %d faulty\n", moduleId);
return -NVL_ERR_GENERIC;
}
@@ -612,6 +612,9 @@ _cci_module_identify_async
NvlStatus retval;
PCCI pCci = device->pCci;
CCI_MODULE_ONBOARD_STATE nextState;
CCI_MODULE_STATE *pOnboardState;
pOnboardState = &device->pCci->moduleState[moduleId];
nvswitch_os_memset(&nextState, 0, sizeof(CCI_MODULE_ONBOARD_STATE));
@@ -637,8 +640,9 @@ _cci_module_identify_async
}
default:
{
// Not expected
NVSWITCH_ASSERT(0);
// Invalid cable type
pOnboardState->onboardError.bOnboardFailure = NV_TRUE;
pOnboardState->onboardError.failedOnboardState = pOnboardState->currOnboardState;
nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION;
break;
}
@@ -646,6 +650,8 @@ _cci_module_identify_async
}
else
{
pOnboardState->onboardError.bOnboardFailure = NV_TRUE;
pOnboardState->onboardError.failedOnboardState = pOnboardState->currOnboardState;
nextState.onboardPhase = CCI_ONBOARD_PHASE_CHECK_CONDITION;
}

4
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -7727,11 +7727,11 @@ nvswitch_ctrl_get_err_info_lr10
}
// TODO NVidia TL not supported
NVSWITCH_PRINT(device, WARN,
NVSWITCH_PRINT(device, NOISY,
"%s WARNING: Nvidia %s register %s does not exist!\n",
__FUNCTION__, "NVLTL", "NV_NVLTL_TL_ERRLOG_REG");
NVSWITCH_PRINT(device, WARN,
NVSWITCH_PRINT(device, NOISY,
"%s WARNING: Nvidia %s register %s does not exist!\n",
__FUNCTION__, "NVLTL", "NV_NVLTL_TL_INTEN_REG");

3
src/common/nvswitch/kernel/ls10/cci_ls10.c
View File

@@ -1638,6 +1638,9 @@ nvswitch_cci_module_access_cmd_ls10
// Mark as faulty
device->pCci->isFaulty[osfp] = NV_TRUE;
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_CCI_MODULE,
"Module %d access error\n", osfp);
return -NVL_IO_ERROR;
}

30
src/common/nvswitch/kernel/ls10/intr_ls10.c
View File

@@ -5549,6 +5549,29 @@ _nvswitch_emit_link_errors_nvldl_fatal_link_ls10
}
}
static void
_nvswitch_dump_minion_ali_debug_registers_ls10
(
nvswitch_device *device,
NvU32 link
)
{
NVSWITCH_MINION_ALI_DEBUG_REGISTERS params;
nvlink_link *nvlink = nvswitch_get_link(device, link);
if ((nvlink != NULL) &&
(nvswitch_minion_get_ali_debug_registers_ls10(device, nvlink, &params) == NVL_SUCCESS))
{
NVSWITCH_PRINT(device, ERROR,
"%s: Minion error on link #%d!:\n"
"Minion DLSTAT MN00 = 0x%x\n"
"Minion DLSTAT UC01 = 0x%x\n"
"Minion DLSTAT UC01 = 0x%x\n",
__FUNCTION__, link,
params.dlstatMn00, params.dlstatUc01, params.dlstatLinkIntr);
}
}
static void
_nvswitch_emit_link_errors_minion_fatal_ls10
(
@@ -5611,6 +5634,8 @@ _nvswitch_emit_link_errors_minion_fatal_ls10
enabledLinks &= ~bit;
regData = DRF_NUM(_MINION, _MINION_INTR_STALL_EN, _LINK, enabledLinks);
NVSWITCH_MINION_LINK_WR32_LS10(device, link, _MINION, _MINION_INTR_STALL_EN, regData);
_nvswitch_dump_minion_ali_debug_registers_ls10(device, link);
}
static void
@@ -5647,8 +5672,8 @@ _nvswitch_emit_link_errors_minion_nonfatal_ls10
switch(DRF_VAL(_MINION, _NVLINK_LINK_INTR, _CODE, regData))
{
case NV_MINION_NVLINK_LINK_INTR_CODE_DLREQ:
NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link DLREQ interrupt");
break;
NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link DLREQ interrupt");
break;
case NV_MINION_NVLINK_LINK_INTR_CODE_PMDISABLED:
NVSWITCH_REPORT_NONFATAL(_HW_MINION_NONFATAL, "Minion Link PMDISABLED interrupt");
break;
@@ -5660,6 +5685,7 @@ _nvswitch_emit_link_errors_minion_nonfatal_ls10
break;
}
_nvswitch_dump_minion_ali_debug_registers_ls10(device, link);
}
static void

85
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -42,6 +42,11 @@
#include "nvswitch/ls10/dev_minion_ip_addendum.h"
#include "ls10/minion_nvlink_defines_public_ls10.h"
#define NV_NVLINK_TLREQ_TIMEOUT_ACTIVE 10000
#define NV_NVLINK_TLREQ_TIMEOUT_SHUTDOWN 10
#define NV_NVLINK_TLREQ_TIMEOUT_RESET 4
#define NV_NVLINK_TLREQ_TIMEOUT_L2 5
static void
_nvswitch_configure_reserved_throughput_counters
(
@@ -143,9 +148,9 @@ nvswitch_init_lpwr_regs_ls10
if (status != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR, "%s: Failed to set L1 Threshold\n",
__FUNCTION__);
__FUNCTION__);
}
}
}
void
nvswitch_corelib_training_complete_ls10
@@ -1433,7 +1438,7 @@ nvswitch_load_link_disable_settings_ls10
nvswitch_device *device,
nvlink_link *link
)
{
{
NvU32 regVal;
// Read state from NVLIPT HW
@@ -1443,7 +1448,7 @@ nvswitch_load_link_disable_settings_ls10
if (FLD_TEST_DRF(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, _DISABLE, regVal))
{
NVSWITCH_ASSERT(!cciIsLinkManaged(device, link->linkNumber));
// Set link to invalid and unregister from corelib
device->link[link->linkNumber].valid = NV_FALSE;
nvlink_lib_unregister_link(link);
@@ -1589,7 +1594,7 @@ nvswitch_reset_and_train_link_ls10
link_intr_subcode = DRF_VAL(_NVLSTAT, _MN00, _LINK_INTR_SUBCODE, stat_data);
if ((link_state == NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_STATUS_MINION_REQUEST_FAIL) &&
(link_intr_subcode == MINION_ALARM_BUSY))
(link_intr_subcode == MINION_ALARM_BUSY))
{
status = nvswitch_request_tl_link_state_ls10(link,
@@ -1683,6 +1688,39 @@ nvswitch_are_link_clocks_on_ls10
return NV_TRUE;
}
static
NvlStatus
_nvswitch_tl_request_get_timeout_value_ls10
(
nvswitch_device *device,
NvU32 tlLinkState,
NvU32 *timeoutVal
)
{
switch (tlLinkState)
{
case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_ACTIVE:
*timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_ACTIVE;
break;
case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_RESET:
*timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_RESET;
break;
case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_SHUTDOWN:
*timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_SHUTDOWN;
break;
case NV_NVLIPT_LNK_CTRL_LINK_STATE_REQUEST_REQUEST_L2:
*timeoutVal = NV_NVLINK_TLREQ_TIMEOUT_L2;
break;
default:
NVSWITCH_PRINT(device, ERROR,
"%s: Invalid tlLinkState %d provided!\n",
__FUNCTION__, tlLinkState);
return NVL_BAD_ARGS;
}
return NVL_SUCCESS;
}
NvlStatus
nvswitch_request_tl_link_state_ls10
(
@@ -1696,6 +1734,9 @@ nvswitch_request_tl_link_state_ls10
NvU32 linkStatus;
NvU32 lnkErrStatus;
NvU32 bit;
NvU32 timeoutVal;
NVSWITCH_TIMEOUT timeout;
NvBool keepPolling;
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber))
{
@@ -1729,17 +1770,43 @@ nvswitch_request_tl_link_state_ls10
if (bSync)
{
// Wait for the TL link state register to complete
status = nvswitch_wait_for_tl_request_ready_lr10(link);
// setup timeouts for the TL request
status = _nvswitch_tl_request_get_timeout_value_ls10(device, tlLinkState, &timeoutVal);
if (status != NVL_SUCCESS)
{
return status;
return NVL_ERR_INVALID_STATE;
}
nvswitch_timeout_create(NVSWITCH_INTERVAL_1MSEC_IN_NS * timeoutVal, &timeout);
status = NVL_MORE_PROCESSING_REQUIRED;
do
{
keepPolling = (nvswitch_timeout_check(&timeout)) ? NV_FALSE : NV_TRUE;
// Check for state requested
linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber,
NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS);
if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) ==
tlLinkState)
{
status = NVL_SUCCESS;
break;
}
nvswitch_os_sleep(1);
}
while(keepPolling);
// Do one final check if the polling loop didn't see the target linkState
if (status == NVL_MORE_PROCESSING_REQUIRED)
{
// Check for state requested
linkStatus = NVSWITCH_LINK_RD32_LS10(device, link->linkNumber,
NVLIPT_LNK , _NVLIPT_LNK , _CTRL_LINK_STATE_STATUS);
if (DRF_VAL(_NVLIPT_LNK, _CTRL_LINK_STATE_STATUS, _CURRENTLINKSTATE, linkStatus) !=
tlLinkState)
{
@@ -1750,6 +1817,8 @@ nvswitch_request_tl_link_state_ls10
}
}
}
return status;
}

37
src/common/sdk/nvidia/inc/class/cl00de.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -36,7 +36,36 @@ extern "C" {
#define RUSD_TIMESTAMP_WRITE_IN_PROGRESS (NV_U64_MAX)
#define RUSD_TIMESTAMP_INVALID 0
#define RUSD_SEQ_DATA_VALID(x) ((((NvU32)(x)) & 0x1U) == 0)
// seq = c_0 * b_0 + c_1 * (b_0 - 1) where c_0 == open_count and c_1 == close_count
// When they are equal, data is valid, otherwise data is being written.
// b_0 == 1 mod (b_0 - 1) and b_0 - 1 == (-1) mod b_0
// So, c_0 == seq mod (b_0 - 1) and c_1 == (-1 * seq) mod b_0
// c_1 cannot be calculated quite so naively because negative modulos aren't fun, so we
// instead do c_1 == (b_0 - (seq mod b_0)) mod b_0
//
#define RUSD_SEQ_BASE_SHIFT 20llu
#define RUSD_SEQ_BASE0 (1llu << RUSD_SEQ_BASE_SHIFT)
#define RUSD_SEQ_BASE1 (RUSD_SEQ_BASE0 - 1llu)
#define RUSD_SEQ_COEFF1(x) ((RUSD_SEQ_BASE0 - ((x) % RUSD_SEQ_BASE0)) % RUSD_SEQ_BASE0)
#define RUSD_SEQ_COEFF0(x) ((x) % RUSD_SEQ_BASE1)
#define RUSD_SEQ_WRAP_SHIFT 18llu
#define RUSD_SEQ_WRAP_VAL (1llu << RUSD_SEQ_WRAP_SHIFT)
#define RUSD_SEQ_DATA_VALID(x) (RUSD_SEQ_COEFF0(x) == RUSD_SEQ_COEFF1(x))
//
// Helper macros to check seq before reading RUSD.
// No dowhile wrap as it is using continue/break
//
#define RUSD_SEQ_CHECK1(SHARED_DATA) \
NvU64 seq = (SHARED_DATA)->seq; \
portAtomicMemoryFenceLoad(); \
if (!RUSD_SEQ_DATA_VALID(seq)) \
continue;
#define RUSD_SEQ_CHECK2(SHARED_DATA) \
portAtomicMemoryFenceLoad(); \
if (seq == (SHARED_DATA)->seq) \
break;
enum {
RUSD_CLK_PUBLIC_DOMAIN_GRAPHICS = 0,
@@ -166,10 +195,12 @@ typedef struct RUSD_INST_POWER_USAGE {
} RUSD_INST_POWER_USAGE;
typedef struct NV00DE_SHARED_DATA {
volatile NvU32 seq;
volatile NvU64 seq;
NvU32 bar1Size;
NvU32 bar1AvailSize;
NvU64 totalPmaMemory;
NvU64 freePmaMemory;
// GSP polling data section
NV_DECLARE_ALIGNED(RUSD_CLK_PUBLIC_DOMAIN_INFOS clkPublicDomainInfos, 8);

31
src/common/sdk/nvidia/inc/ctrl/ctrla081.h
View File

@@ -853,7 +853,8 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
} NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS;
/* vGPU capabilities */
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
#define NVA081_CTRL_VGPU_CAPABILITY_MINI_QUARTER_GPU 0
#define NVA081_CTRL_VGPU_CAPABILITY_COMPUTE_MEDIA_ENGINE_GPU 1
/*
* NVA081_CTRL_CMD_VGPU_SET_CAPABILITY
@@ -872,7 +873,7 @@ typedef struct NVA081_CTRL_PGPU_GET_VGPU_STREAMING_CAPABILITY_PARAMS {
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_CMD_VGPU_SET_CAPABILITY (0xa081011e) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS_MESSAGE_ID (0x1eU)
@@ -881,4 +882,30 @@ typedef struct NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS {
NvBool state;
} NVA081_CTRL_VGPU_SET_CAPABILITY_PARAMS;
/*
* NVA081_CTRL_CMD_VGPU_GET_CAPABILITY
*
* This command is to get state of vGPU capability for the physical GPU.
*
* capability [IN]
* This param specifies the requested capabiity of the device that is to be set
* One of NVA081_CTRL_VGPU_CAPABILITY* values
*
* state [OUT]
* This param specifies the state of the capability
*
* Possible status values returned are:
* NV_OK
* NV_ERR_OBJECT_NOT_FOUND
* NV_ERR_INVALID_ARGUMENT
*/
#define NVA081_CTRL_CMD_VGPU_GET_CAPABILITY (0xa081011f) /* finn: Evaluated from "(FINN_NVA081_VGPU_CONFIG_VGPU_CONFIG_INTERFACE_ID << 8) | NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID" */
#define NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS_MESSAGE_ID (0x1fU)
typedef struct NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS {
NvU32 capability;
NvBool state;
} NVA081_CTRL_VGPU_GET_CAPABILITY_PARAMS;
/* _ctrlA081vgpuconfig_h_ */

286
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -44,151 +44,6 @@ ENTRY(0x13BD, 0x11D6, 0x10de, "GRID M10-8A"),
ENTRY(0x13BD, 0x1286, 0x10de, "GRID M10-2B"),
ENTRY(0x13BD, 0x12EE, 0x10de, "GRID M10-2B4"),
ENTRY(0x13BD, 0x1339, 0x10de, "GRID M10-1B4"),
ENTRY(0x13F2, 0x114C, 0x10de, "GRID M60-0Q"),
ENTRY(0x13F2, 0x114D, 0x10de, "GRID M60-1Q"),
ENTRY(0x13F2, 0x114E, 0x10de, "GRID M60-2Q"),
ENTRY(0x13F2, 0x114F, 0x10de, "GRID M60-4Q"),
ENTRY(0x13F2, 0x1150, 0x10de, "GRID M60-8Q"),
ENTRY(0x13F2, 0x1176, 0x10de, "GRID M60-0B"),
ENTRY(0x13F2, 0x1177, 0x10de, "GRID M60-1B"),
ENTRY(0x13F2, 0x117D, 0x10de, "GRID M60-2B"),
ENTRY(0x13F2, 0x11AE, 0x10de, "GRID M60-1A"),
ENTRY(0x13F2, 0x11AF, 0x10de, "GRID M60-2A"),
ENTRY(0x13F2, 0x11B0, 0x10de, "GRID M60-4A"),
ENTRY(0x13F2, 0x11B1, 0x10de, "GRID M60-8A"),
ENTRY(0x13F2, 0x12EC, 0x10de, "GRID M60-2B4"),
ENTRY(0x13F2, 0x1337, 0x10de, "GRID M60-1B4"),
ENTRY(0x13F3, 0x117C, 0x10de, "GRID M6-2B"),
ENTRY(0x13F3, 0x117E, 0x10de, "GRID M6-0B"),
ENTRY(0x13F3, 0x117F, 0x10de, "GRID M6-1B"),
ENTRY(0x13F3, 0x1180, 0x10de, "GRID M6-0Q"),
ENTRY(0x13F3, 0x1181, 0x10de, "GRID M6-1Q"),
ENTRY(0x13F3, 0x1182, 0x10de, "GRID M6-2Q"),
ENTRY(0x13F3, 0x1183, 0x10de, "GRID M6-4Q"),
ENTRY(0x13F3, 0x1184, 0x10de, "GRID M6-8Q"),
ENTRY(0x13F3, 0x11AA, 0x10de, "GRID M6-1A"),
ENTRY(0x13F3, 0x11AB, 0x10de, "GRID M6-2A"),
ENTRY(0x13F3, 0x11AC, 0x10de, "GRID M6-4A"),
ENTRY(0x13F3, 0x11AD, 0x10de, "GRID M6-8A"),
ENTRY(0x13F3, 0x12ED, 0x10de, "GRID M6-2B4"),
ENTRY(0x13F3, 0x1338, 0x10de, "GRID M6-1B4"),
ENTRY(0x15F7, 0x1265, 0x10de, "GRID P100C-1B"),
ENTRY(0x15F7, 0x1266, 0x10de, "GRID P100C-1Q"),
ENTRY(0x15F7, 0x1267, 0x10de, "GRID P100C-2Q"),
ENTRY(0x15F7, 0x1268, 0x10de, "GRID P100C-4Q"),
ENTRY(0x15F7, 0x1269, 0x10de, "GRID P100C-6Q"),
ENTRY(0x15F7, 0x126A, 0x10de, "GRID P100C-12Q"),
ENTRY(0x15F7, 0x126B, 0x10de, "GRID P100C-1A"),
ENTRY(0x15F7, 0x126C, 0x10de, "GRID P100C-2A"),
ENTRY(0x15F7, 0x126D, 0x10de, "GRID P100C-4A"),
ENTRY(0x15F7, 0x126E, 0x10de, "GRID P100C-6A"),
ENTRY(0x15F7, 0x126F, 0x10de, "GRID P100C-12A"),
ENTRY(0x15F7, 0x128D, 0x10de, "GRID P100C-2B"),
ENTRY(0x15F7, 0x12F4, 0x10de, "GRID P100C-2B4"),
ENTRY(0x15F7, 0x133F, 0x10de, "GRID P100C-1B4"),
ENTRY(0x15F7, 0x137D, 0x10de, "GRID P100C-12C"),
ENTRY(0x15F7, 0x138C, 0x10de, "GRID P100C-4C"),
ENTRY(0x15F7, 0x138D, 0x10de, "GRID P100C-6C"),
ENTRY(0x15F8, 0x1221, 0x10de, "GRID P100-1B"),
ENTRY(0x15F8, 0x1222, 0x10de, "GRID P100-1Q"),
ENTRY(0x15F8, 0x1223, 0x10de, "GRID P100-2Q"),
ENTRY(0x15F8, 0x1224, 0x10de, "GRID P100-4Q"),
ENTRY(0x15F8, 0x1225, 0x10de, "GRID P100-8Q"),
ENTRY(0x15F8, 0x1226, 0x10de, "GRID P100-16Q"),
ENTRY(0x15F8, 0x1227, 0x10de, "GRID P100-1A"),
ENTRY(0x15F8, 0x1228, 0x10de, "GRID P100-2A"),
ENTRY(0x15F8, 0x1229, 0x10de, "GRID P100-4A"),
ENTRY(0x15F8, 0x122A, 0x10de, "GRID P100-8A"),
ENTRY(0x15F8, 0x122B, 0x10de, "GRID P100-16A"),
ENTRY(0x15F8, 0x128C, 0x10de, "GRID P100-2B"),
ENTRY(0x15F8, 0x12F2, 0x10de, "GRID P100-2B4"),
ENTRY(0x15F8, 0x133D, 0x10de, "GRID P100-1B4"),
ENTRY(0x15F8, 0x137C, 0x10de, "GRID P100-16C"),
ENTRY(0x15F8, 0x138A, 0x10de, "GRID P100-4C"),
ENTRY(0x15F8, 0x138B, 0x10de, "GRID P100-8C"),
ENTRY(0x15F9, 0x122C, 0x10de, "GRID P100X-1B"),
ENTRY(0x15F9, 0x122D, 0x10de, "GRID P100X-1Q"),
ENTRY(0x15F9, 0x122E, 0x10de, "GRID P100X-2Q"),
ENTRY(0x15F9, 0x122F, 0x10de, "GRID P100X-4Q"),
ENTRY(0x15F9, 0x1230, 0x10de, "GRID P100X-8Q"),
ENTRY(0x15F9, 0x1231, 0x10de, "GRID P100X-16Q"),
ENTRY(0x15F9, 0x1232, 0x10de, "GRID P100X-1A"),
ENTRY(0x15F9, 0x1233, 0x10de, "GRID P100X-2A"),
ENTRY(0x15F9, 0x1234, 0x10de, "GRID P100X-4A"),
ENTRY(0x15F9, 0x1235, 0x10de, "GRID P100X-8A"),
ENTRY(0x15F9, 0x1236, 0x10de, "GRID P100X-16A"),
ENTRY(0x15F9, 0x128B, 0x10de, "GRID P100X-2B"),
ENTRY(0x15F9, 0x12F3, 0x10de, "GRID P100X-2B4"),
ENTRY(0x15F9, 0x133E, 0x10de, "GRID P100X-1B4"),
ENTRY(0x15F9, 0x137B, 0x10de, "GRID P100X-16C"),
ENTRY(0x15F9, 0x1388, 0x10de, "GRID P100X-4C"),
ENTRY(0x15F9, 0x1389, 0x10de, "GRID P100X-8C"),
ENTRY(0x1B38, 0x11E7, 0x10de, "GRID P40-1B"),
ENTRY(0x1B38, 0x11E8, 0x10de, "GRID P40-1Q"),
ENTRY(0x1B38, 0x11E9, 0x10de, "GRID P40-2Q"),
ENTRY(0x1B38, 0x11EA, 0x10de, "GRID P40-3Q"),
ENTRY(0x1B38, 0x11EB, 0x10de, "GRID P40-4Q"),
ENTRY(0x1B38, 0x11EC, 0x10de, "GRID P40-6Q"),
ENTRY(0x1B38, 0x11ED, 0x10de, "GRID P40-8Q"),
ENTRY(0x1B38, 0x11EE, 0x10de, "GRID P40-12Q"),
ENTRY(0x1B38, 0x11EF, 0x10de, "GRID P40-24Q"),
ENTRY(0x1B38, 0x11F0, 0x10de, "GRID P40-1A"),
ENTRY(0x1B38, 0x11F1, 0x10de, "GRID P40-2A"),
ENTRY(0x1B38, 0x11F2, 0x10de, "GRID P40-3A"),
ENTRY(0x1B38, 0x11F3, 0x10de, "GRID P40-4A"),
ENTRY(0x1B38, 0x11F4, 0x10de, "GRID P40-6A"),
ENTRY(0x1B38, 0x11F5, 0x10de, "GRID P40-8A"),
ENTRY(0x1B38, 0x11F6, 0x10de, "GRID P40-12A"),
ENTRY(0x1B38, 0x11F7, 0x10de, "GRID P40-24A"),
ENTRY(0x1B38, 0x1287, 0x10de, "GRID P40-2B"),
ENTRY(0x1B38, 0x12B1, 0x10de, "GeForce GTX P40-24"),
ENTRY(0x1B38, 0x12B2, 0x10de, "GeForce GTX P40-12"),
ENTRY(0x1B38, 0x12B3, 0x10de, "GeForce GTX P40-6"),
ENTRY(0x1B38, 0x12EF, 0x10de, "GRID P40-2B4"),
ENTRY(0x1B38, 0x133A, 0x10de, "GRID P40-1B4"),
ENTRY(0x1B38, 0x137E, 0x10de, "GRID P40-24C"),
ENTRY(0x1B38, 0x1381, 0x10de, "GRID P40-4C"),
ENTRY(0x1B38, 0x1382, 0x10de, "GRID P40-6C"),
ENTRY(0x1B38, 0x1383, 0x10de, "GRID P40-8C"),
ENTRY(0x1B38, 0x1384, 0x10de, "GRID P40-12C"),
ENTRY(0x1B38, 0x13B0, 0x10de, "GRID GTX P40-6"),
ENTRY(0x1B38, 0x13B1, 0x10de, "GRID GTX P40-12"),
ENTRY(0x1B38, 0x13B2, 0x10de, "GRID GTX P40-24"),
ENTRY(0x1B38, 0x13D0, 0x10de, "GRID GTX P40-8"),
ENTRY(0x1BB3, 0x1203, 0x10de, "GRID P4-1B"),
ENTRY(0x1BB3, 0x1204, 0x10de, "GRID P4-1Q"),
ENTRY(0x1BB3, 0x1205, 0x10de, "GRID P4-2Q"),
ENTRY(0x1BB3, 0x1206, 0x10de, "GRID P4-4Q"),
ENTRY(0x1BB3, 0x1207, 0x10de, "GRID P4-8Q"),
ENTRY(0x1BB3, 0x1208, 0x10de, "GRID P4-1A"),
ENTRY(0x1BB3, 0x1209, 0x10de, "GRID P4-2A"),
ENTRY(0x1BB3, 0x120A, 0x10de, "GRID P4-4A"),
ENTRY(0x1BB3, 0x120B, 0x10de, "GRID P4-8A"),
ENTRY(0x1BB3, 0x1288, 0x10de, "GRID P4-2B"),
ENTRY(0x1BB3, 0x12F1, 0x10de, "GRID P4-2B4"),
ENTRY(0x1BB3, 0x133C, 0x10de, "GRID P4-1B4"),
ENTRY(0x1BB3, 0x136D, 0x10de, "GRID GTX P4-2"),
ENTRY(0x1BB3, 0x136E, 0x10de, "GRID GTX P4-4"),
ENTRY(0x1BB3, 0x136F, 0x10de, "GRID GTX P4-8"),
ENTRY(0x1BB3, 0x1380, 0x10de, "GRID P4-8C"),
ENTRY(0x1BB3, 0x1385, 0x10de, "GRID P4-4C"),
ENTRY(0x1BB4, 0x11F8, 0x10de, "GRID P6-1B"),
ENTRY(0x1BB4, 0x11F9, 0x10de, "GRID P6-1Q"),
ENTRY(0x1BB4, 0x11FA, 0x10de, "GRID P6-2Q"),
ENTRY(0x1BB4, 0x11FB, 0x10de, "GRID P6-4Q"),
ENTRY(0x1BB4, 0x11FC, 0x10de, "GRID P6-8Q"),
ENTRY(0x1BB4, 0x11FD, 0x10de, "GRID P6-16Q"),
ENTRY(0x1BB4, 0x11FE, 0x10de, "GRID P6-1A"),
ENTRY(0x1BB4, 0x11FF, 0x10de, "GRID P6-2A"),
ENTRY(0x1BB4, 0x1200, 0x10de, "GRID P6-4A"),
ENTRY(0x1BB4, 0x1201, 0x10de, "GRID P6-8A"),
ENTRY(0x1BB4, 0x1202, 0x10de, "GRID P6-16A"),
ENTRY(0x1BB4, 0x1289, 0x10de, "GRID P6-2B"),
ENTRY(0x1BB4, 0x12F0, 0x10de, "GRID P6-2B4"),
ENTRY(0x1BB4, 0x133B, 0x10de, "GRID P6-1B4"),
ENTRY(0x1BB4, 0x137F, 0x10de, "GRID P6-16C"),
ENTRY(0x1BB4, 0x1386, 0x10de, "GRID P6-4C"),
ENTRY(0x1BB4, 0x1387, 0x10de, "GRID P6-8C"),
ENTRY(0x1DB1, 0x1259, 0x10de, "GRID V100X-1B"),
ENTRY(0x1DB1, 0x125A, 0x10de, "GRID V100X-1Q"),
ENTRY(0x1DB1, 0x125B, 0x10de, "GRID V100X-2Q"),
@@ -813,6 +668,20 @@ ENTRY(0x2324, 0x18E0, 0x10de, "NVIDIA H800XM-16C"),
ENTRY(0x2324, 0x18E1, 0x10de, "NVIDIA H800XM-20C"),
ENTRY(0x2324, 0x18E2, 0x10de, "NVIDIA H800XM-40C"),
ENTRY(0x2324, 0x18E3, 0x10de, "NVIDIA H800XM-80C"),
ENTRY(0x2329, 0x2028, 0x10de, "NVIDIA H20-1-12CME"),
ENTRY(0x2329, 0x2029, 0x10de, "NVIDIA H20-1-12C"),
ENTRY(0x2329, 0x202A, 0x10de, "NVIDIA H20-1-24C"),
ENTRY(0x2329, 0x202B, 0x10de, "NVIDIA H20-2-24C"),
ENTRY(0x2329, 0x202C, 0x10de, "NVIDIA H20-3-48C"),
ENTRY(0x2329, 0x202D, 0x10de, "NVIDIA H20-4-48C"),
ENTRY(0x2329, 0x202E, 0x10de, "NVIDIA H20-7-96C"),
ENTRY(0x2329, 0x202F, 0x10de, "NVIDIA H20-4C"),
ENTRY(0x2329, 0x2030, 0x10de, "NVIDIA H20-6C"),
ENTRY(0x2329, 0x2031, 0x10de, "NVIDIA H20-12C"),
ENTRY(0x2329, 0x2032, 0x10de, "NVIDIA H20-16C"),
ENTRY(0x2329, 0x2033, 0x10de, "NVIDIA H20-24C"),
ENTRY(0x2329, 0x2034, 0x10de, "NVIDIA H20-48C"),
ENTRY(0x2329, 0x2035, 0x10de, "NVIDIA H20-96C"),
ENTRY(0x2330, 0x187A, 0x10de, "NVIDIA H100XM-1-10CME"),
ENTRY(0x2330, 0x187B, 0x10de, "NVIDIA H100XM-1-10C"),
ENTRY(0x2330, 0x187C, 0x10de, "NVIDIA H100XM-1-20C"),
@@ -883,14 +752,14 @@ ENTRY(0x233A, 0x186B, 0x10de, "NVIDIA H800L-15C"),
ENTRY(0x233A, 0x186C, 0x10de, "NVIDIA H800L-23C"),
ENTRY(0x233A, 0x186D, 0x10de, "NVIDIA H800L-47C"),
ENTRY(0x233A, 0x186E, 0x10de, "NVIDIA H800L-94C"),
ENTRY(0x2342, 0x18C2, 0x10de, "NVIDIA H100GL-1-12CME"),
ENTRY(0x2342, 0x18C3, 0x10de, "NVIDIA H100GL-1-12C"),
ENTRY(0x2342, 0x18C4, 0x10de, "NVIDIA H100GL-1-24C"),
ENTRY(0x2342, 0x18C5, 0x10de, "NVIDIA H100GL-2-24C"),
ENTRY(0x2342, 0x18C6, 0x10de, "NVIDIA H100GL-3-48C"),
ENTRY(0x2342, 0x18C7, 0x10de, "NVIDIA H100GL-4-48C"),
ENTRY(0x2342, 0x18C8, 0x10de, "NVIDIA H100GL-7-96C"),
ENTRY(0x2342, 0x18C9, 0x10de, "NVIDIA H100GL-96C"),
ENTRY(0x2342, 0x18C2, 0x10de, "NVIDIA GH200-1-12CME"),
ENTRY(0x2342, 0x18C3, 0x10de, "NVIDIA GH200-1-12C"),
ENTRY(0x2342, 0x18C4, 0x10de, "NVIDIA GH200-1-24C"),
ENTRY(0x2342, 0x18C5, 0x10de, "NVIDIA GH200-2-24C"),
ENTRY(0x2342, 0x18C6, 0x10de, "NVIDIA GH200-3-48C"),
ENTRY(0x2342, 0x18C7, 0x10de, "NVIDIA GH200-4-48C"),
ENTRY(0x2342, 0x18C8, 0x10de, "NVIDIA GH200-7-96C"),
ENTRY(0x2342, 0x18C9, 0x10de, "NVIDIA GH200-96C"),
ENTRY(0x25B6, 0x159D, 0x10de, "NVIDIA A16-1B"),
ENTRY(0x25B6, 0x159E, 0x10de, "NVIDIA A16-2B"),
ENTRY(0x25B6, 0x159F, 0x10de, "NVIDIA A16-1Q"),
@@ -987,6 +856,45 @@ ENTRY(0x26B2, 0x1835, 0x10de, "NVIDIA RTX5000-Ada-4C"),
ENTRY(0x26B2, 0x1836, 0x10de, "NVIDIA RTX5000-Ada-8C"),
ENTRY(0x26B2, 0x1837, 0x10de, "NVIDIA RTX5000-Ada-16C"),
ENTRY(0x26B2, 0x1838, 0x10de, "NVIDIA RTX5000-Ada-32C"),
ENTRY(0x26B3, 0x1958, 0x10de, "NVIDIA RTX 5880-Ada-1B"),
ENTRY(0x26B3, 0x1959, 0x10de, "NVIDIA RTX 5880-Ada-2B"),
ENTRY(0x26B3, 0x195A, 0x10de, "NVIDIA RTX 5880-Ada-1Q"),
ENTRY(0x26B3, 0x195B, 0x10de, "NVIDIA RTX 5880-Ada-2Q"),
ENTRY(0x26B3, 0x195C, 0x10de, "NVIDIA RTX 5880-Ada-3Q"),
ENTRY(0x26B3, 0x195D, 0x10de, "NVIDIA RTX 5880-Ada-4Q"),
ENTRY(0x26B3, 0x195E, 0x10de, "NVIDIA RTX 5880-Ada-6Q"),
ENTRY(0x26B3, 0x195F, 0x10de, "NVIDIA RTX 5880-Ada-8Q"),
ENTRY(0x26B3, 0x1960, 0x10de, "NVIDIA RTX 5880-Ada-12Q"),
ENTRY(0x26B3, 0x1961, 0x10de, "NVIDIA RTX 5880-Ada-16Q"),
ENTRY(0x26B3, 0x1962, 0x10de, "NVIDIA RTX 5880-Ada-24Q"),
ENTRY(0x26B3, 0x1963, 0x10de, "NVIDIA RTX 5880-Ada-48Q"),
ENTRY(0x26B3, 0x1964, 0x10de, "NVIDIA RTX 5880-Ada-1A"),
ENTRY(0x26B3, 0x1965, 0x10de, "NVIDIA RTX 5880-Ada-2A"),
ENTRY(0x26B3, 0x1966, 0x10de, "NVIDIA RTX 5880-Ada-3A"),
ENTRY(0x26B3, 0x1967, 0x10de, "NVIDIA RTX 5880-Ada-4A"),
ENTRY(0x26B3, 0x1968, 0x10de, "NVIDIA RTX 5880-Ada-6A"),
ENTRY(0x26B3, 0x1969, 0x10de, "NVIDIA RTX 5880-Ada-8A"),
ENTRY(0x26B3, 0x196A, 0x10de, "NVIDIA RTX 5880-Ada-12A"),
ENTRY(0x26B3, 0x196B, 0x10de, "NVIDIA RTX 5880-Ada-16A"),
ENTRY(0x26B3, 0x196C, 0x10de, "NVIDIA RTX 5880-Ada-24A"),
ENTRY(0x26B3, 0x196D, 0x10de, "NVIDIA RTX 5880-Ada-48A"),
ENTRY(0x26B3, 0x196E, 0x10de, "NVIDIA RTX 5880-Ada-1"),
ENTRY(0x26B3, 0x196F, 0x10de, "NVIDIA RTX 5880-Ada-2"),
ENTRY(0x26B3, 0x1970, 0x10de, "NVIDIA RTX 5880-Ada-3"),
ENTRY(0x26B3, 0x1971, 0x10de, "NVIDIA RTX 5880-Ada-4"),
ENTRY(0x26B3, 0x1972, 0x10de, "NVIDIA RTX 5880-Ada-6"),
ENTRY(0x26B3, 0x1973, 0x10de, "NVIDIA RTX 5880-Ada-8"),
ENTRY(0x26B3, 0x1974, 0x10de, "NVIDIA RTX 5880-Ada-12"),
ENTRY(0x26B3, 0x1975, 0x10de, "NVIDIA RTX 5880-Ada-16"),
ENTRY(0x26B3, 0x1976, 0x10de, "NVIDIA RTX 5880-Ada-24"),
ENTRY(0x26B3, 0x1977, 0x10de, "NVIDIA RTX 5880-Ada-48"),
ENTRY(0x26B3, 0x1978, 0x10de, "NVIDIA RTX 5880-Ada-4C"),
ENTRY(0x26B3, 0x1979, 0x10de, "NVIDIA RTX 5880-Ada-6C"),
ENTRY(0x26B3, 0x197A, 0x10de, "NVIDIA RTX 5880-Ada-8C"),
ENTRY(0x26B3, 0x197B, 0x10de, "NVIDIA RTX 5880-Ada-12C"),
ENTRY(0x26B3, 0x197C, 0x10de, "NVIDIA RTX 5880-Ada-16C"),
ENTRY(0x26B3, 0x197D, 0x10de, "NVIDIA RTX 5880-Ada-24C"),
ENTRY(0x26B3, 0x197E, 0x10de, "NVIDIA RTX 5880-Ada-48C"),
ENTRY(0x26B5, 0x176D, 0x10de, "NVIDIA L40-1B"),
ENTRY(0x26B5, 0x176E, 0x10de, "NVIDIA L40-2B"),
ENTRY(0x26B5, 0x176F, 0x10de, "NVIDIA L40-1Q"),
@@ -1102,6 +1010,78 @@ ENTRY(0x26B9, 0x18AE, 0x10de, "NVIDIA L40S-12C"),
ENTRY(0x26B9, 0x18AF, 0x10de, "NVIDIA L40S-16C"),
ENTRY(0x26B9, 0x18B0, 0x10de, "NVIDIA L40S-24C"),
ENTRY(0x26B9, 0x18B1, 0x10de, "NVIDIA L40S-48C"),
ENTRY(0x26BA, 0x1909, 0x10de, "NVIDIA L20-1B"),
ENTRY(0x26BA, 0x190A, 0x10de, "NVIDIA L20-2B"),
ENTRY(0x26BA, 0x190B, 0x10de, "NVIDIA L20-1Q"),
ENTRY(0x26BA, 0x190C, 0x10de, "NVIDIA L20-2Q"),
ENTRY(0x26BA, 0x190D, 0x10de, "NVIDIA L20-3Q"),
ENTRY(0x26BA, 0x190E, 0x10de, "NVIDIA L20-4Q"),
ENTRY(0x26BA, 0x190F, 0x10de, "NVIDIA L20-6Q"),
ENTRY(0x26BA, 0x1910, 0x10de, "NVIDIA L20-8Q"),
ENTRY(0x26BA, 0x1911, 0x10de, "NVIDIA L20-12Q"),
ENTRY(0x26BA, 0x1912, 0x10de, "NVIDIA L20-16Q"),
ENTRY(0x26BA, 0x1913, 0x10de, "NVIDIA L20-24Q"),
ENTRY(0x26BA, 0x1914, 0x10de, "NVIDIA L20-48Q"),
ENTRY(0x26BA, 0x1915, 0x10de, "NVIDIA L20-1A"),
ENTRY(0x26BA, 0x1916, 0x10de, "NVIDIA L20-2A"),
ENTRY(0x26BA, 0x1917, 0x10de, "NVIDIA L20-3A"),
ENTRY(0x26BA, 0x1918, 0x10de, "NVIDIA L20-4A"),
ENTRY(0x26BA, 0x1919, 0x10de, "NVIDIA L20-6A"),
ENTRY(0x26BA, 0x191A, 0x10de, "NVIDIA L20-8A"),
ENTRY(0x26BA, 0x191B, 0x10de, "NVIDIA L20-12A"),
ENTRY(0x26BA, 0x191C, 0x10de, "NVIDIA L20-16A"),
ENTRY(0x26BA, 0x191D, 0x10de, "NVIDIA L20-24A"),
ENTRY(0x26BA, 0x191E, 0x10de, "NVIDIA L20-48A"),
ENTRY(0x26BA, 0x191F, 0x10de, "NVIDIA GeForce RTX 3050"),
ENTRY(0x26BA, 0x1920, 0x10de, "NVIDIA GeForce RTX 3060"),
ENTRY(0x26BA, 0x1921, 0x10de, "NVIDIA L20-1"),
ENTRY(0x26BA, 0x1922, 0x10de, "NVIDIA L20-2"),
ENTRY(0x26BA, 0x1923, 0x10de, "NVIDIA L20-3"),
ENTRY(0x26BA, 0x1924, 0x10de, "NVIDIA L20-4"),
ENTRY(0x26BA, 0x1925, 0x10de, "NVIDIA L20-6"),
ENTRY(0x26BA, 0x1926, 0x10de, "NVIDIA L20-8"),
ENTRY(0x26BA, 0x1927, 0x10de, "NVIDIA L20-12"),
ENTRY(0x26BA, 0x1928, 0x10de, "NVIDIA L20-16"),
ENTRY(0x26BA, 0x1929, 0x10de, "NVIDIA L20-24"),
ENTRY(0x26BA, 0x192A, 0x10de, "NVIDIA L20-48"),
ENTRY(0x26BA, 0x192B, 0x10de, "NVIDIA L20-4C"),
ENTRY(0x26BA, 0x192C, 0x10de, "NVIDIA L20-6C"),
ENTRY(0x26BA, 0x192D, 0x10de, "NVIDIA L20-8C"),
ENTRY(0x26BA, 0x192E, 0x10de, "NVIDIA L20-12C"),
ENTRY(0x26BA, 0x192F, 0x10de, "NVIDIA L20-16C"),
ENTRY(0x26BA, 0x1930, 0x10de, "NVIDIA L20-24C"),
ENTRY(0x26BA, 0x1931, 0x10de, "NVIDIA L20-48C"),
ENTRY(0x27B6, 0x1938, 0x10de, "NVIDIA L2-1B"),
ENTRY(0x27B6, 0x1939, 0x10de, "NVIDIA L2-2B"),
ENTRY(0x27B6, 0x193A, 0x10de, "NVIDIA L2-1Q"),
ENTRY(0x27B6, 0x193B, 0x10de, "NVIDIA L2-2Q"),
ENTRY(0x27B6, 0x193C, 0x10de, "NVIDIA L2-3Q"),
ENTRY(0x27B6, 0x193D, 0x10de, "NVIDIA L2-4Q"),
ENTRY(0x27B6, 0x193E, 0x10de, "NVIDIA L2-6Q"),
ENTRY(0x27B6, 0x193F, 0x10de, "NVIDIA L2-8Q"),
ENTRY(0x27B6, 0x1940, 0x10de, "NVIDIA L2-12Q"),
ENTRY(0x27B6, 0x1941, 0x10de, "NVIDIA L2-24Q"),
ENTRY(0x27B6, 0x1942, 0x10de, "NVIDIA L2-1A"),
ENTRY(0x27B6, 0x1943, 0x10de, "NVIDIA L2-2A"),
ENTRY(0x27B6, 0x1944, 0x10de, "NVIDIA L2-3A"),
ENTRY(0x27B6, 0x1945, 0x10de, "NVIDIA L2-4A"),
ENTRY(0x27B6, 0x1946, 0x10de, "NVIDIA L2-6A"),
ENTRY(0x27B6, 0x1947, 0x10de, "NVIDIA L2-8A"),
ENTRY(0x27B6, 0x1948, 0x10de, "NVIDIA L2-12A"),
ENTRY(0x27B6, 0x1949, 0x10de, "NVIDIA L2-24A"),
ENTRY(0x27B6, 0x194A, 0x10de, "NVIDIA L2-1"),
ENTRY(0x27B6, 0x194B, 0x10de, "NVIDIA L2-2"),
ENTRY(0x27B6, 0x194C, 0x10de, "NVIDIA L2-3"),
ENTRY(0x27B6, 0x194D, 0x10de, "NVIDIA L2-4"),
ENTRY(0x27B6, 0x194E, 0x10de, "NVIDIA L2-6"),
ENTRY(0x27B6, 0x194F, 0x10de, "NVIDIA L2-8"),
ENTRY(0x27B6, 0x1950, 0x10de, "NVIDIA L2-12"),
ENTRY(0x27B6, 0x1951, 0x10de, "NVIDIA L2-24"),
ENTRY(0x27B6, 0x1952, 0x10de, "NVIDIA L2-4C"),
ENTRY(0x27B6, 0x1953, 0x10de, "NVIDIA L2-6C"),
ENTRY(0x27B6, 0x1954, 0x10de, "NVIDIA L2-8C"),
ENTRY(0x27B6, 0x1955, 0x10de, "NVIDIA L2-12C"),
ENTRY(0x27B6, 0x1956, 0x10de, "NVIDIA L2-24C"),
ENTRY(0x27B8, 0x172F, 0x10de, "NVIDIA L4-1B"),
ENTRY(0x27B8, 0x1730, 0x10de, "NVIDIA L4-2B"),
ENTRY(0x27B8, 0x1731, 0x10de, "NVIDIA L4-1Q"),

23
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -18,9 +18,9 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x2330, 0x16C0, 0x2330, 0x16C1 },
{ 0x2336, 0x16C2, 0x2330, 0x16C1 },
{ 0x2342, 0x1809, 0x2342, 0x1805 },
};
for (NvU32 i = 0; i < (sizeof(vgpu_aliases) / sizeof(struct vgpu_alias_details)); ++i) {
@@ -136,6 +136,13 @@ static const struct {
{0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1280}, // NVIDIA H800XM-3-40C
{0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1281}, // NVIDIA H800XM-4-40C
{0x232410DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1282}, // NVIDIA H800XM-7-80C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1397}, // NVIDIA H20-1-12CME
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1398}, // NVIDIA H20-1-12C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1399}, // NVIDIA H20-1-24C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1400}, // NVIDIA H20-2-24C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1401}, // NVIDIA H20-3-48C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1402}, // NVIDIA H20-4-48C
{0x232910DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1403}, // NVIDIA H20-7-96C
{0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME
{0x233610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1130}, // NVIDIA H100XM-1-10CME
{0x233010DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1131}, // NVIDIA H100XM-1-10C
@@ -178,13 +185,13 @@ static const struct {
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1079}, // NVIDIA H800L-3-47C
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1080}, // NVIDIA H800L-4-47C
{0x233A10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1081}, // NVIDIA H800L-7-94C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1196}, // NVIDIA H100GL-1-12CME
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1197}, // NVIDIA H100GL-1-12C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1198}, // NVIDIA H100GL-1-24C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1199}, // NVIDIA H100GL-2-24C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1200}, // NVIDIA H100GL-3-48C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1201}, // NVIDIA H100GL-4-48C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1202}, // NVIDIA H100GL-7-96C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1196}, // NVIDIA GH200-1-12CME
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1197}, // NVIDIA GH200-1-12C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1198}, // NVIDIA GH200-1-24C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1199}, // NVIDIA GH200-2-24C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1200}, // NVIDIA GH200-3-48C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1201}, // NVIDIA GH200-4-48C
{0x234210DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1202}, // NVIDIA GH200-7-96C
};
#endif // GENERATE_vgpuSmcTypeIdMappings