mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-02 06:29:47 +00:00
550.54.14
This commit is contained in:
@@ -991,7 +991,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
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pInfo->cc_white_y |= (p->Chromaticity[1] & NVT_PVT_EDID_CC_WHITE_Y1_Y0_MASK) >> NVT_PVT_EDID_CC_WHITE_Y1_Y0_SHIFT;
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// copy established timings
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pInfo->established_timings_1_2 = (NvU16)p->bEstablishedTimings1 << 8;
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pInfo->established_timings_1_2 = (NvU16)p->bEstablishedTimings1 << 8;
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pInfo->established_timings_1_2 |= (NvU16)p->bEstablishedTimings2;
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// copy manuf reserved timings
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@@ -1039,7 +1039,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
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p861Info = (k == 0) ? &pInfo->ext861 : &pInfo->ext861_2;
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get861ExtInfo(pExt, sizeof(EDIDV1STRUC), p861Info);
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// HF EEODB is present in edid v1.3 and v1.4 does not need this.Also, it is always present in the 1st CTA extension block.
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if (j == 1 && pInfo->version == NVT_EDID_VER_1_3)
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{
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@@ -1106,11 +1106,6 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
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pInfo->ext_displayid20.interface_features.yuv420_min_pclk = 0;
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}
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if (pInfo->ext861.revision == 0 && pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
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{
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pInfo->ext861.revision = NVT_CEA861_REV_B;
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}
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if (pInfo->ext_displayid20.valid_data_blocks.interface_feature_present)
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{
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pInfo->ext861.basic_caps |= pInfo->ext_displayid20.basic_caps;
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@@ -1157,7 +1152,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
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}
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}
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// Copy all the timings(could include type 7/8/9/10) from displayid20->timings[] to pEdidInfo->timings[]
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// Copy all the timings(could include type 7/8/9/10) from displayid20->timings[] to pEdidInfo->timings[]
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for (i = 0; i < pInfo->ext_displayid20.total_timings; i++)
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{
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if (!assignNextAvailableTiming(pInfo, &(pInfo->ext_displayid20.timing[i])))
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@@ -1215,7 +1210,7 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
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CODE_SEGMENT(PAGE_DD_CODE)
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void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
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{
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{
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NvU32 i, j, data;
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for (i = 0; i < pInfo->total_timings; i++)
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@@ -1226,8 +1221,8 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
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case NVT_TYPE_HDMI_STEREO:
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case NVT_TYPE_HDMI_EXT:
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// VTB timing use the base EDID (block 0) to determine the color format support
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case NVT_TYPE_EDID_VTB_EXT:
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case NVT_TYPE_EDID_VTB_EXT_STD:
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case NVT_TYPE_EDID_VTB_EXT:
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case NVT_TYPE_EDID_VTB_EXT_STD:
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case NVT_TYPE_EDID_VTB_EXT_DTD:
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case NVT_TYPE_EDID_VTB_EXT_CVT:
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// pInfo->u.feature_ver_1_3.color_type provides mono, rgb, rgy, undefined
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@@ -1245,7 +1240,7 @@ void updateColorFormatAndBpcTiming(NVT_EDID_INFO *pInfo)
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}
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updateBpcForTiming(pInfo, i);
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break;
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default:
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default:
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// * the displayID_v1.3/v2.0 EDID extension need to follow the EDID bpc definition.
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// * all other default to base edid
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updateBpcForTiming(pInfo, i);
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@@ -1319,7 +1314,7 @@ NvBool isMatchedStandardTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
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for (j = 0; j < pInfo->total_timings; j++)
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{
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if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD &&
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if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_STD &&
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NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
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{
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return NV_TRUE;
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@@ -1335,7 +1330,7 @@ NvBool isMatchedEstablishedTiming(NVT_EDID_INFO *pInfo, NVT_TIMING *pT)
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for (j = 0; j < pInfo->total_timings; j++)
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{
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if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST &&
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if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[j].etc.status) == NVT_TYPE_EDID_EST &&
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NvTiming_IsTimingRelaxedEqual(&pInfo->timing[j], pT))
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{
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return NV_TRUE;
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@@ -1405,7 +1400,7 @@ void updateBpcForTiming(NVT_EDID_INFO *pInfo, NvU32 index)
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}
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}
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else if ((pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED ||
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pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
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pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
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pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_UNDEFINED) &&
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p861Info->revision >= NVT_CEA861_REV_A)
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{
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@@ -1462,7 +1457,7 @@ NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr,
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// the timing mapping index :
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//
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// native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators
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// native_cta - the "native resoluiotn of the sink" in the CTA861.6 A Source shall override any other native video resolution indicators
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// if the Source supports NVRDB and the NVRDB was found in the E-EDID
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// preferred_cta - the "prefer SVD" in CTA-861-F (i.e. A Sink that prefers a Video Format that is not listed as an SVD in Video Data Block, but instead listed in YCBCR 4:2:0 VDB)
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// preferred_displayid_dtd - the "prefer detailed timing of DispalyID" extension
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@@ -1546,7 +1541,7 @@ NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr,
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if (native_cta == pEdidInfo->total_timings && NVT_NATIVE_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
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{
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native_cta = i;
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}
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}
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if (preferred_cta == pEdidInfo->total_timings && NVT_PREFERRED_TIMING_IS_CTA(pEdidTiming[i].etc.flag))
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{
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@@ -2063,10 +2058,10 @@ NVT_STATUS NvTiming_GetEDIDBasedASPRTiming( NvU16 width, NvU16 height, NvU16 rr,
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*
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* @brief check EDID raw data is valid or not, and it will return the err flags if it existed
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* @param pEdid : this is a pointer to EDID data
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* @param length : read length of EDID
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* @param length : read length of EDID
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* @param bIsTrongValidation : true - added more check
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* false- only header and checksum and size check
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*
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*
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*/
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CODE_SEGMENT(PAGE_DD_CODE)
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NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation)
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@@ -2086,12 +2081,12 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
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return ret;
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}
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// check the EDID version and signature
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// check the EDID version and signature
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if (getEdidVersion(pEdid, &version) != NVT_STATUS_SUCCESS)
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{
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION);
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return ret;
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}
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}
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// check block 0 checksum value
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if (!isChecksumValid(pEdid))
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@@ -2239,11 +2234,11 @@ NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongVal
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/**
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*
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* @brief sanity check EDID binary frequently used data block is valid or not,
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* @brief sanity check EDID binary frequently used data block is valid or not,
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* and it will return error checkpoint flag if it existed
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* @param pEdid : this is a pointer to EDID raw data
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* @param length : read length of EDID
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*
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*
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*/
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CODE_SEGMENT(PAGE_DD_CODE)
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NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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@@ -2255,7 +2250,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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DETAILEDTIMINGDESCRIPTOR *pDTD;
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// For CTA861
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NvU8 ctaDTD_Offset;
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NvU8 *pData_collection;
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NvU8 *pData_collection;
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NvU32 ctaBlockTag, ctaPayload, vic;
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// For DisplayID
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DIDEXTENSION *pDisplayid;
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@@ -2283,7 +2278,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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{
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_VERSION);
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}
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// 18bytes in DTD or Display Descriptor check
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for (i = 0; i < NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR; i++)
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{
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@@ -2313,7 +2308,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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}
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}
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else
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{
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{
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pLdd = (EDID_LONG_DISPLAY_DESCRIPTOR *)&p->DetailedTimingDesc[i];
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// This block is a display descriptor, validate
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@@ -2327,7 +2322,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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NvU8 max_v_rate_offset, min_v_rate_offset, max_h_rate_offset, min_h_rate_offset;
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// add 255Hz offsets as needed before doing the check, use descriptor->rsvd2
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nvt_assert(!(pLdd->rsvd2 & 0xF0));
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nvt_assert(!(pLdd->rsvd2 & 0xF0));
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max_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MAX ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0;
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min_v_rate_offset = pLdd->rsvd2 & NVT_PVT_EDID_RANGE_OFFSET_VER_MIN ? NVT_PVT_EDID_RANGE_OFFSET_AMOUNT : 0;
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@@ -2340,19 +2335,19 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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pRangeLimit->maxHRate == 0)
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{
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_RANGE_LIMIT);
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}
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}
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}
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}
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}
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// extension and size check
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if ((NvU32)(p->bExtensionFlag + 1) * sizeof(EDIDV1STRUC) > length)
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{
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{
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT);
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}
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// we shall not trust any extension blocks with wrong input EDID size
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if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) ||
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// we shall not trust any extension blocks with wrong input EDID size
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if (NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_SIZE) ||
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NVT_IS_EDID_VALIDATION_FLAGS(ret, NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT))
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return ret;
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@@ -2384,7 +2379,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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// validate SVD block
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ctaBlockTag = NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(((EIA861EXTENSION *)pExt)->data[0]);
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pData_collection = ((EIA861EXTENSION *)pExt)->data;
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while ((ctaDTD_Offset - 4) > 0 && pData_collection != &pExt[ctaDTD_Offset] &&
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ctaBlockTag > NVT_CEA861_TAG_RSVD && ctaBlockTag <= NVT_CEA861_TAG_EXTENDED_FLAG)
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{
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@@ -2451,7 +2446,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DTD);
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else
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{
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// check the max image size and
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// check the max image size and
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if (p->bMaxHorizImageSize != 0 && p->bMaxVertImageSize != 0)
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{
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NvU16 hDTDImageSize = (pDTD->bDTHorizVertImage & 0xF0) << 4 | pDTD->bDTHorizontalImage;
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@@ -2466,7 +2461,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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if(!isChecksumValid(pExt))
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM);
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break;
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break;
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case NVT_EDID_EXTENSION_DISPLAYID:
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pDisplayid = ((DIDEXTENSION *)pExt);
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if (pDisplayid->ext_count != 0)
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@@ -2483,10 +2478,10 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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{
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if ((pDisplayid->struct_version & 0xFF) == 0x21)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION);
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did2ExtCount++;
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if (pDisplayid->use_case == 0 && did2ExtCount == 1)
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if (pDisplayid->use_case == 0 && did2ExtCount == 1)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_USE_CASE);
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// check the DisplayId2 valid timing
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@@ -2506,7 +2501,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE7);
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if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_RANGE_LIMITS)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
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if (pDID2Header->type == DISPLAYID_2_0_BLOCK_TYPE_ADAPTIVE_SYNC)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_ADAPTIVE_SYNC);
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@@ -2527,9 +2522,9 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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}
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// if the first tag failed, ignore all the tags afterward then
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if (!bAllZero &&
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(pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY ||
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(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE &&
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if (!bAllZero &&
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(pDID2Header->type < DISPLAYID_2_0_BLOCK_TYPE_PRODUCT_IDENTITY ||
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(pDID2Header->type > DISPLAYID_2_0_BLOCK_TYPE_BRIGHTNESS_LUMINANCE_RANGE &&
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pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_VENDOR_SPEC &&
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pDID2Header->type != DISPLAYID_2_0_BLOCK_TYPE_CTA_DATA)) &&
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(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
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@@ -2537,7 +2532,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID2_TAG);
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continue;
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}
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}
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}
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else if ((pDisplayid->struct_version & 0xFF) == 0x12 || (pDisplayid->struct_version & 0xFF) == 0x13)
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{
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if ((pDisplayid->struct_version & 0xFF) == 0x13)
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@@ -2559,7 +2554,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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if (pHeader->type == NVT_DISPLAYID_BLOCK_TYPE_RANGE_LIMITS)
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT);
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// add more data blocks tag here to evaluate
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}
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pData_collection += block_length;
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@@ -2580,7 +2575,7 @@ NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length)
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if (!bAllZero &&
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pHeader->type > NVT_DISPLAYID_BLOCK_TYPE_TILEDDISPLAY &&
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pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_CTA_DATA &&
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pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC &&
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pHeader->type != NVT_DISPLAYID_BLOCK_TYPE_VENDOR_SPEC &&
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(pData_collection - pExt < (int)sizeof(DIDEXTENSION)))
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{
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ret |= NVT_EDID_VALIDATION_ERR_MASK(NVT_EDID_VALIDATION_ERR_EXT_DID13_TAG);
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@@ -2939,7 +2934,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
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// Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year
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NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6);
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// Wipe out the checksums
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CommonEDIDBuffer[CommonEDIDBuffer[1]+5/*mandatory bytes*/-1] = 0;
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CommonEDIDBuffer[0xFF] = 0;
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@@ -2954,7 +2949,7 @@ NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion)
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// displayId2 standalone uses 256 length sections
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commonEDIDBufferSize = 256;
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}
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else
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else
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{
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// Wipe out the Serial Number, Week of Manufacture, and Year of Manufacture or Model Year
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NVMISC_MEMSET(CommonEDIDBuffer + 0x0C, 0, 6);
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@@ -111,7 +111,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
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nvt_assert((timingIdx) <= COUNT(pInfo->timing));
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||||
|
||||
if ((pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED ||
|
||||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
|
||||
pInfo->input.u.digital.video_interface == NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED ||
|
||||
pInfo->ext861.valid.H14B_VSDB || pInfo->ext861.valid.H20_HF_VSDB) && pInfo->ext861.revision >= NVT_CEA861_REV_A)
|
||||
{
|
||||
if (!pInfo->ext_displayid.supported_displayId2_0)
|
||||
@@ -153,7 +153,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
|
||||
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_10b,
|
||||
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_12b,
|
||||
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_14b,
|
||||
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_16b);
|
||||
pDisplayIdInfo->u4.display_interface_features.rgb_depth.support_16b);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -174,7 +174,7 @@ void updateColorFormatForDisplayIdExtnTimings(NVT_EDID_INFO *pInfo,
|
||||
pDisplayIdInfo->u4.display_interface.ycbcr422_depth.support_14b,
|
||||
pDisplayIdInfo->u4.display_interface.ycbcr422_depth.support_16b);
|
||||
}
|
||||
else
|
||||
else
|
||||
{
|
||||
// yuv444
|
||||
UPDATE_BPC_FOR_COLORFORMAT(pT->etc.yuv444, 0, /* yuv444 does not support 6bpc */
|
||||
@@ -264,7 +264,7 @@ static NVT_STATUS parseDisplayIdSection(DISPLAYID_SECTION * section,
|
||||
* @brief Parses a displayID data block
|
||||
* @param block The DisplayID data block to parse
|
||||
* @param max_length The indicated total length of the each data block for checking
|
||||
* @param pLength return the indicated length of the each data block
|
||||
* @param pLength return the indicated length of the each data block
|
||||
* @param pEdidInfo EDID struct containing DisplayID information and
|
||||
* the timings or validation purpose if it is NULL
|
||||
*/
|
||||
@@ -285,7 +285,7 @@ NVT_STATUS parseDisplayIdBlock(NvU8* pBlock,
|
||||
return NVT_STATUS_ERR;
|
||||
|
||||
pInfo = pEdidInfo == NULL ? NULL : &pEdidInfo->ext_displayid;
|
||||
|
||||
|
||||
*pLength = hdr->data_bytes + NVT_DISPLAYID_DATABLOCK_HEADER_LEN;
|
||||
|
||||
switch (hdr->type)
|
||||
@@ -386,9 +386,9 @@ static NVT_STATUS parseDisplayIdColorChar(NvU8 * block, NVT_DISPLAYID_INFO *pInf
|
||||
|
||||
for (i = 0; i < prim_num; i++)
|
||||
{
|
||||
x_p = (blk->points)[i].color_x_bits_low +
|
||||
x_p = (blk->points)[i].color_x_bits_low +
|
||||
(DRF_VAL(T_DISPLAYID, _COLOR, _POINT_X, (blk->points)[i].color_bits_mid) << 8);
|
||||
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
|
||||
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
|
||||
((blk->points)[i].color_y_bits_high << 4);
|
||||
pInfo->primaries[i].x = x_p;
|
||||
pInfo->primaries[i].y = y_p;
|
||||
@@ -396,9 +396,9 @@ static NVT_STATUS parseDisplayIdColorChar(NvU8 * block, NVT_DISPLAYID_INFO *pInf
|
||||
|
||||
for (j = 0; j < wp_num; j++)
|
||||
{
|
||||
x_p = (blk->points)[i].color_x_bits_low +
|
||||
x_p = (blk->points)[i].color_x_bits_low +
|
||||
(DRF_VAL(T_DISPLAYID, _COLOR, _POINT_X, (blk->points)[i].color_bits_mid) << 8);
|
||||
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
|
||||
y_p = DRF_VAL(T_DISPLAYID, _COLOR, _POINT_Y, (blk->points)[i].color_bits_mid) +
|
||||
((blk->points)[i].color_y_bits_high << 4);
|
||||
pInfo->white_points[pInfo->total_primaries + j].x = x_p;
|
||||
pInfo->white_points[pInfo->total_primaries + j].y = y_p;
|
||||
@@ -508,7 +508,6 @@ static NVT_STATUS parseDisplayIdTiming1(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
|
||||
CODE_SEGMENT(PAGE_DD_CODE)
|
||||
static NVT_STATUS parseDisplayIdTiming1Descriptor(DISPLAYID_TIMING_1_DESCRIPTOR * type1, NVT_TIMING *pT)
|
||||
{
|
||||
NvU32 totalPixels_in_2_fields;
|
||||
if (type1 == NULL || pT == NULL)
|
||||
return NVT_STATUS_ERR;
|
||||
|
||||
@@ -569,30 +568,17 @@ static NVT_STATUS parseDisplayIdTiming1Descriptor(DISPLAYID_TIMING_1_DESCRIPTOR
|
||||
}
|
||||
|
||||
// the refresh rate
|
||||
if (pT->interlaced)
|
||||
{
|
||||
// in interlaced mode, adjust for one extra line in every other frame. pT->VTotal is field based here
|
||||
totalPixels_in_2_fields = (NvU32)pT->HTotal * ((NvU32)pT->VTotal * 2 + 1);
|
||||
// calculate the field rate in interlaced mode
|
||||
pT->etc.rr = (NvU16)axb_div_c(pT->pclk * 2, 10000, totalPixels_in_2_fields);
|
||||
pT->etc.rrx1k = axb_div_c(pT->pclk * 2, 10000000, totalPixels_in_2_fields);
|
||||
}
|
||||
else
|
||||
{
|
||||
// calculate frame rate in progressive mode
|
||||
// in progressive mode filed = frame
|
||||
pT->etc.rr = (NvU16)axb_div_c(pT->pclk, 10000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
|
||||
pT->etc.rrx1k = axb_div_c(pT->pclk, 10000000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
|
||||
}
|
||||
pT->etc.rr = NvTiming_CalcRR(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
|
||||
pT->etc.rrx1k = NvTiming_CalcRRx1k(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
|
||||
pT->etc.name[39] = '\0';
|
||||
pT->etc.rep = 0x1; // bit mask for no pixel repetition
|
||||
|
||||
|
||||
pT->etc.status = NVT_STATUS_DISPLAYID_1;
|
||||
// Unlike the PTM in EDID base block, DisplayID type I/II preferred timing does not have dependency on sequence
|
||||
// so we'll just update the preferred flag, not sequence them
|
||||
//pT->etc.status = NVT_STATUS_DISPLAYID_1N(1);
|
||||
pT->etc.flag |= type1->options.is_preferred_detailed_timing ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
|
||||
|
||||
|
||||
/* Fields currently not used. Uncomment them for future use
|
||||
type1->options.stereo_support;
|
||||
*/
|
||||
@@ -651,7 +637,6 @@ static NVT_STATUS parseDisplayIdTiming2(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
|
||||
CODE_SEGMENT(PAGE_DD_CODE)
|
||||
static NVT_STATUS parseDisplayIdTiming2Descriptor(DISPLAYID_TIMING_2_DESCRIPTOR * type2, NVT_TIMING *pT)
|
||||
{
|
||||
NvU32 totalPixels_in_2_fields;
|
||||
if (type2 == NULL || pT == NULL)
|
||||
return NVT_STATUS_ERR;
|
||||
|
||||
@@ -679,32 +664,19 @@ static NVT_STATUS parseDisplayIdTiming2Descriptor(DISPLAYID_TIMING_2_DESCRIPTOR
|
||||
pT->interlaced = type2->options.interface_frame_scanning_type;
|
||||
|
||||
// the refresh rate
|
||||
if (pT->interlaced)
|
||||
{
|
||||
// in interlaced mode, adjust for one extra line in every other frame. pT->VTotal is field based here
|
||||
totalPixels_in_2_fields = (NvU32)pT->HTotal * ((NvU32)pT->VTotal * 2 + 1);
|
||||
// calculate the field rate in interlaced mode
|
||||
pT->etc.rr = (NvU16)axb_div_c(pT->pclk * 2, 10000, totalPixels_in_2_fields);
|
||||
pT->etc.rrx1k = axb_div_c(pT->pclk * 2, 10000000, totalPixels_in_2_fields);
|
||||
}
|
||||
else
|
||||
{
|
||||
// calculate frame rate in progressive mode
|
||||
// in progressive mode filed = frame
|
||||
pT->etc.rr = (NvU16)axb_div_c(pT->pclk, 10000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
|
||||
pT->etc.rrx1k = axb_div_c(pT->pclk, 10000000, (NvU32)pT->HTotal * (NvU32)pT->VTotal);
|
||||
}
|
||||
pT->etc.rr = NvTiming_CalcRR(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
|
||||
pT->etc.rrx1k = NvTiming_CalcRRx1k(pT->pclk, pT->interlaced, pT->HTotal, pT->VTotal);
|
||||
|
||||
pT->etc.aspect = 0;
|
||||
pT->etc.name[39] = '\0';
|
||||
pT->etc.rep = 0x1; // Bit mask for no pixel repetition
|
||||
|
||||
|
||||
pT->etc.status = NVT_STATUS_DISPLAYID_2;
|
||||
// Unlike the PTM in EDID base block, DisplayID type I/II preferred timing does not have dependency on sequence
|
||||
// so we'll just update the preferred flag, not sequence them
|
||||
//pT->etc.status = NVT_STATUS_DISPLAYID_1N(1);
|
||||
pT->etc.flag |= type2->options.is_preferred_detailed_timing ? NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING : 0;
|
||||
|
||||
|
||||
/* Fields currently not used. Uncomment them for future use
|
||||
type1->options.stereo_support;
|
||||
*/
|
||||
@@ -861,12 +833,12 @@ static NVT_STATUS parseDisplayIdTiming5Descriptor(DISPLAYID_TIMING_5_DESCRIPTOR
|
||||
{
|
||||
NvU32 width, height, rr;
|
||||
NvBool is1000div1001 = NV_FALSE;
|
||||
|
||||
|
||||
// we don't handle stereo type nor custom reduced blanking yet
|
||||
//NvU8 stereoType, formula;
|
||||
//stereoType = (desc->optns & NVT_DISPLAYID_TIMING_5_STEREO_SUPPORT_MASK);
|
||||
//formula = desc->optns & NVT_DISPLAYID_TIMING_5_FORMULA_SUPPORT_MASK;
|
||||
|
||||
|
||||
if (desc->optns & NVT_DISPLAYID_TIMING_5_FRACTIONAL_RR_SUPPORT_MASK)
|
||||
{
|
||||
is1000div1001 = NV_TRUE;
|
||||
@@ -892,7 +864,7 @@ static NVT_STATUS parseDisplayIdTiming5(NvU8 * block, NVT_EDID_INFO *pEdidInfo)
|
||||
for (i = 0; i * sizeof(DISPLAYID_TIMING_5_DESCRIPTOR) < blk->header.data_bytes; i++)
|
||||
{
|
||||
NVMISC_MEMSET(&newTiming, 0, sizeof(newTiming));
|
||||
|
||||
|
||||
if (parseDisplayIdTiming5Descriptor(blk->descriptors + i, &newTiming) == NVT_STATUS_SUCCESS)
|
||||
{
|
||||
if (pEdidInfo == NULL) continue;
|
||||
@@ -1030,7 +1002,7 @@ static NVT_STATUS parseDisplayIdRangeLimits(NvU8 * block, NVT_DISPLAYID_INFO *pI
|
||||
|
||||
rl = pInfo->range_limits + pInfo->rl_num;
|
||||
(pInfo->rl_num)++;
|
||||
|
||||
|
||||
rl->pclk_min = minPclk;
|
||||
rl->pclk_max = maxPclk;
|
||||
|
||||
@@ -1105,7 +1077,7 @@ static NVT_STATUS parseDisplayIdDeviceData(NvU8 * block, NVT_DISPLAYID_INFO *pIn
|
||||
pInfo->device_op_mode = DRF_VAL(T_DISPLAYID, _DEVICE, _OPERATING_MODE, blk->operating_mode);
|
||||
pInfo->support_backlight = DRF_VAL(T_DISPLAYID, _DEVICE, _BACKLIGHT, blk->operating_mode);
|
||||
pInfo->support_intensity = DRF_VAL(T_DISPLAYID, _DEVICE, _INTENSITY, blk->operating_mode);
|
||||
|
||||
|
||||
pInfo->horiz_pixel_count = blk->horizontal_pixel_count;
|
||||
pInfo->vert_pixel_count = blk->vertical_pixel_count;
|
||||
|
||||
@@ -1278,7 +1250,7 @@ static NVT_STATUS parseDisplayIdStereo(NvU8 * block, NVT_DISPLAYID_INFO *pInfo)
|
||||
nvt_assert(0);
|
||||
return NVT_STATUS_ERR;
|
||||
}
|
||||
|
||||
|
||||
return NVT_STATUS_SUCCESS;
|
||||
}
|
||||
|
||||
@@ -1322,7 +1294,7 @@ static NVT_STATUS parseDisplayIdTiledDisplay(NvU8 * block, NVT_DISPLAYID_INFO *p
|
||||
pInfo->bezel_info.left = (blk->bezel_info.left * blk->bezel_info.pixel_density) / 10;
|
||||
|
||||
pInfo->tile_topology_id.vendor_id = (blk->topology_id.vendor_id[2] << 16) |
|
||||
(blk->topology_id.vendor_id[1] << 8 ) |
|
||||
(blk->topology_id.vendor_id[1] << 8 ) |
|
||||
blk->topology_id.vendor_id[0];
|
||||
|
||||
pInfo->tile_topology_id.product_id = (blk->topology_id.product_id[1] << 8) | blk->topology_id.product_id[0];
|
||||
@@ -1350,7 +1322,7 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo)
|
||||
if (pInfo == NULL) return NVT_STATUS_SUCCESS;
|
||||
|
||||
p861info = &pInfo->ext861;
|
||||
|
||||
|
||||
pInfo->ext_displayid.cea_data_block_present = 1;
|
||||
p861info->revision = blk->revision;
|
||||
|
||||
@@ -1366,7 +1338,7 @@ static NVT_STATUS parseDisplayIdCtaData(NvU8 * block, NVT_EDID_INFO *pInfo)
|
||||
|
||||
//parse HDR related information from the HDR static metadata data block
|
||||
parseCea861HdrStaticMetadataDataBlock(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
|
||||
|
||||
|
||||
// base video
|
||||
parse861bShortTiming(p861info, pInfo, FROM_DISPLAYID_13_DATA_BLOCK);
|
||||
// yuv420-only video
|
||||
@@ -1422,7 +1394,7 @@ static NVT_STATUS parseDisplayIdDisplayInterfaceFeatures(NvU8 * block, NVT_DISPL
|
||||
|
||||
// Minimum Pixel Rate at Which YCbCr 4:2:0 Encoding Is Supported
|
||||
pInfo->u4.display_interface_features.minimum_pixel_rate_ycbcr420 = blk->minimum_pixel_rate_ycbcr420;
|
||||
|
||||
|
||||
// Audio capability
|
||||
pInfo->u4.display_interface_features.audio_capability.support_32khz = DRF_VAL(T_DISPLAYID, _INTERFACE_FEATURES, _AUDIO_SUPPORTED_32KHZ, blk->supported_audio_capability);
|
||||
pInfo->u4.display_interface_features.audio_capability.support_44_1khz = DRF_VAL(T_DISPLAYID, _INTERFACE_FEATURES, _AUDIO_SUPPORTED_44_1KHZ, blk->supported_audio_capability);
|
||||
|
||||
@@ -235,7 +235,7 @@ NvU16 NvTiming_CalcRR(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal)
|
||||
|
||||
if (totalPixelsIn2Fields != 0)
|
||||
{
|
||||
rr = (NvU16)axb_div_c(pclk * 2, 10000, totalPixelsIn2Fields);
|
||||
rr = (NvU16)axb_div_c_64((NvU64)pclk * 2, (NvU64)10000, (NvU64)totalPixelsIn2Fields);
|
||||
}
|
||||
}
|
||||
else
|
||||
@@ -244,7 +244,7 @@ NvU16 NvTiming_CalcRR(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal)
|
||||
|
||||
if (totalPixels != 0)
|
||||
{
|
||||
rr = (NvU16)axb_div_c(pclk, 10000, totalPixels);
|
||||
rr = (NvU16)axb_div_c_64((NvU64)pclk, (NvU64)10000, (NvU64)totalPixels);
|
||||
}
|
||||
}
|
||||
return rr;
|
||||
@@ -261,7 +261,7 @@ NvU32 NvTiming_CalcRRx1k(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTota
|
||||
|
||||
if (totalPixelsIn2Fields != 0)
|
||||
{
|
||||
rrx1k = (NvU32)axb_div_c(pclk * 2, 10000000, totalPixelsIn2Fields);
|
||||
rrx1k = (NvU32)axb_div_c_64((NvU64)pclk * 2, (NvU64)10000000, (NvU64)totalPixelsIn2Fields);
|
||||
}
|
||||
}
|
||||
else
|
||||
@@ -270,7 +270,7 @@ NvU32 NvTiming_CalcRRx1k(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTota
|
||||
|
||||
if (totalPixels != 0)
|
||||
{
|
||||
rrx1k = (NvU32)axb_div_c(pclk, 10000000, totalPixels);
|
||||
rrx1k = (NvU32)axb_div_c_64((NvU64)pclk, (NvU64)10000000, (NvU64)totalPixels);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user