mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-07 00:29:58 +00:00
550.54.14
This commit is contained in:
Bernhard Stoeckner
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -223,7 +223,8 @@ typedef struct
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#define GSP_FW_HEAP_FREE_LIST_MAGIC 0x4845415046524545ULL
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#define GSP_FW_FLAGS 8:0
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#define GSP_FW_FLAGS_CLOCK_BOOST NVBIT(0)
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#define GSP_FW_FLAGS 8:0
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#define GSP_FW_FLAGS_CLOCK_BOOST NVBIT(0)
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#define GSP_FW_FLAGS_RECOVERY_MARGIN_PRESENT NVBIT(1)
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#endif // GSP_FW_WPR_META_H_
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160
src/nvidia/arch/nvalloc/common/inc/spdm/rmspdmrsakeys.h
Normal file
160
src/nvidia/arch/nvalloc/common/inc/spdm/rmspdmrsakeys.h
Normal file
@@ -0,0 +1,160 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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||||
* SPDX-License-Identifier: MIT
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||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
|
||||
*
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||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
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||||
*
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||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/*!
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* @file rmspdmrsakeys.h
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* @brief SPDM Interfaces - RSA keys
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*/
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#ifndef _RM_SPDM_RSA_KEYS_H_
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#define _RM_SPDM_RSA_KEYS_H_
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//
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// Note !!
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// All key components order must be big-endian(network order).
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// If any change for these key components, need to rebuild GSP/RM code as well.
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//
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#ifndef USE_MBEDTLS
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const NvU8 g_rsa3k_modulus_mutual_authentication_prod[] =
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{
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0xcd, 0x65, 0xd2, 0xca, 0x74, 0xd1, 0x76, 0x76, 0x9f, 0x18, 0x23, 0x64, 0x55, 0x84, 0x98, 0x60,
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||||
0x71, 0xeb, 0x42, 0x6d, 0xa4, 0x98, 0xf9, 0x92, 0xea, 0x83, 0x5b, 0x9b, 0xe2, 0x66, 0x8b, 0x43,
|
||||
0x14, 0x4d, 0x5a, 0xb8, 0xdb, 0x68, 0x2b, 0xfa, 0x5f, 0xdf, 0x7f, 0xf4, 0xfd, 0x5e, 0x42, 0x34,
|
||||
0x09, 0x98, 0xa1, 0x21, 0x98, 0x4c, 0x8d, 0xbc, 0x99, 0xdb, 0xea, 0xc1, 0xe3, 0x42, 0xe6, 0x67,
|
||||
0x26, 0x86, 0x2c, 0xd0, 0xdb, 0xf3, 0x9c, 0x12, 0xad, 0xb3, 0x82, 0x93, 0x9c, 0xb9, 0xae, 0x98,
|
||||
0x82, 0xeb, 0x59, 0xb6, 0x5c, 0x09, 0x9f, 0xa6, 0x15, 0x30, 0xa0, 0xc6, 0x77, 0xd5, 0xae, 0xa2,
|
||||
0x91, 0x65, 0x24, 0xc3, 0x7d, 0x9b, 0xa4, 0x2c, 0x31, 0x73, 0x41, 0x26, 0x72, 0xe7, 0x2f, 0xb8,
|
||||
0x60, 0xd8, 0xce, 0xb8, 0xd8, 0x4b, 0x90, 0x6c, 0xa3, 0x19, 0x7e, 0x2b, 0xd5, 0xf6, 0x05, 0x8a,
|
||||
0x2b, 0xb9, 0x9e, 0x27, 0xba, 0x2e, 0x16, 0x81, 0x9a, 0x9e, 0xf5, 0x6c, 0x38, 0x0a, 0x01, 0xea,
|
||||
0xd6, 0xe1, 0xa4, 0x83, 0x76, 0xd0, 0x68, 0xbb, 0x90, 0x63, 0xce, 0x1c, 0x8c, 0x6f, 0x0f, 0x6b,
|
||||
0x65, 0x5b, 0x12, 0xe2, 0x92, 0x60, 0x79, 0x88, 0x99, 0x5e, 0x17, 0x89, 0x4d, 0x54, 0xb1, 0x87,
|
||||
0x9c, 0xe6, 0x6d, 0x3c, 0x56, 0x1c, 0x3a, 0x3e, 0xb9, 0x16, 0x2c, 0xc8, 0xda, 0x1a, 0xfb, 0x5c,
|
||||
0xd7, 0x16, 0x3c, 0x74, 0xda, 0x78, 0xf1, 0x53, 0xd7, 0x66, 0x97, 0x8a, 0x57, 0x0b, 0x86, 0x57,
|
||||
0x2c, 0x45, 0xa1, 0x5e, 0xae, 0x39, 0x39, 0xde, 0xe0, 0x40, 0x6f, 0xdb, 0x4c, 0xd8, 0xc1, 0x8c,
|
||||
0xdb, 0xce, 0xea, 0x05, 0xc0, 0xbc, 0x89, 0x72, 0x15, 0xfd, 0xbf, 0xb2, 0xb7, 0xf2, 0x5d, 0x05,
|
||||
0xdd, 0x2b, 0x53, 0xa4, 0x03, 0x1e, 0x11, 0x67, 0xa7, 0x0f, 0x87, 0xfb, 0x57, 0x48, 0x91, 0xc8,
|
||||
0x02, 0xb7, 0x46, 0x3d, 0x82, 0xcd, 0x06, 0x4a, 0x79, 0x0f, 0xa5, 0x8a, 0xac, 0xfb, 0xb7, 0xc2,
|
||||
0xf0, 0x95, 0x19, 0x4c, 0x78, 0x7a, 0xc7, 0xd7, 0x70, 0xee, 0x6e, 0x59, 0xaf, 0x51, 0x9b, 0x11,
|
||||
0x03, 0xd3, 0x56, 0xb3, 0x05, 0x5a, 0xbb, 0x1f, 0xbd, 0xc2, 0x0e, 0x89, 0x77, 0xb4, 0xc1, 0x02,
|
||||
0xf9, 0x97, 0x56, 0x07, 0x2e, 0x4e, 0x2d, 0x01, 0x73, 0x89, 0x7d, 0xf3, 0xc9, 0x8c, 0x88, 0x2c,
|
||||
0x79, 0xd9, 0x47, 0x34, 0x9e, 0x32, 0x51, 0xd4, 0xa6, 0x7e, 0xd1, 0x08, 0xda, 0xc0, 0x76, 0x24,
|
||||
0x8e, 0x25, 0x73, 0x14, 0x30, 0xd2, 0x17, 0x37, 0xbc, 0xe0, 0x3e, 0xa2, 0x47, 0xff, 0xe2, 0x4e,
|
||||
0x9b, 0x31, 0x6c, 0xe6, 0x54, 0xaf, 0x62, 0x3a, 0xcd, 0xfa, 0x2f, 0xaf, 0x73, 0x2e, 0x73, 0x4a,
|
||||
0x3a, 0x60, 0xa8, 0xa9, 0xfc, 0x77, 0xb2, 0x57, 0xdd, 0x3a, 0xfa, 0xce, 0x35, 0xc3, 0xea, 0xa9
|
||||
};
|
||||
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const NvU8 g_rsa3k_public_exponent_mutual_authentication_prod[] = {0x00, 0x01, 0x00, 0x01};
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||||
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||||
const NvU8 g_rsa3k_private_exponent_mutual_authentication_prod[] =
|
||||
{
|
||||
0x04, 0x85, 0xc0, 0x6d, 0x6a, 0xc3, 0x0d, 0xeb, 0xb0, 0xb7, 0x14, 0x58, 0x6a, 0x35, 0xa0, 0x31,
|
||||
0x47, 0x70, 0xd9, 0xa6, 0x96, 0x60, 0x33, 0xe6, 0x93, 0x39, 0x4f, 0x34, 0x10, 0x79, 0x17, 0x89,
|
||||
0xe3, 0x91, 0x8c, 0x74, 0xd3, 0x87, 0xe8, 0xa7, 0xfb, 0xa2, 0x6d, 0x2b, 0xd4, 0xc4, 0x55, 0x8a,
|
||||
0xd5, 0xc7, 0x41, 0x8c, 0xfe, 0xd0, 0x78, 0xb2, 0x75, 0x64, 0xcd, 0x37, 0x75, 0xac, 0x8c, 0x6c,
|
||||
0x2b, 0x01, 0xfb, 0x4c, 0xa1, 0xfb, 0x2c, 0x2d, 0x91, 0x1b, 0x89, 0xbd, 0x7c, 0x4e, 0xee, 0x54,
|
||||
0x37, 0x55, 0xbd, 0x44, 0xf1, 0xa3, 0xd8, 0x9b, 0x0c, 0x8e, 0x64, 0x8b, 0xda, 0x29, 0x9f, 0x4d,
|
||||
0xbf, 0x0b, 0xce, 0x12, 0x6b, 0xda, 0x98, 0x73, 0xcc, 0xa6, 0xf0, 0x01, 0x4b, 0xb8, 0x61, 0x69,
|
||||
0x9a, 0xe0, 0x4b, 0x34, 0xf0, 0xb6, 0x41, 0x38, 0xd3, 0x22, 0x85, 0x8f, 0xab, 0x87, 0x5e, 0x39,
|
||||
0xdb, 0x9a, 0x9b, 0xab, 0xde, 0x42, 0x93, 0x86, 0x49, 0x04, 0x44, 0xfd, 0x1c, 0x02, 0xc4, 0x66,
|
||||
0x0a, 0x53, 0x2f, 0x8f, 0x21, 0x77, 0x97, 0x46, 0xc1, 0xf8, 0x20, 0x9a, 0xaa, 0x50, 0xeb, 0xb2,
|
||||
0xfe, 0xa9, 0x51, 0xb2, 0x21, 0x6c, 0xf4, 0x60, 0x18, 0x98, 0x64, 0xc6, 0x46, 0x28, 0x9e, 0x3c,
|
||||
0x11, 0x2d, 0x55, 0xac, 0x65, 0x6c, 0xfb, 0xaf, 0x53, 0xdd, 0xf4, 0x20, 0x7c, 0x04, 0xea, 0x11,
|
||||
0xe8, 0x25, 0x65, 0x15, 0x32, 0x8e, 0x08, 0x84, 0xc7, 0x41, 0x13, 0x58, 0x73, 0x61, 0x63, 0x1f,
|
||||
0xef, 0x30, 0x1d, 0x3d, 0x36, 0x08, 0x3a, 0xb2, 0xf7, 0x25, 0x56, 0xfc, 0x03, 0x78, 0xb5, 0x45,
|
||||
0xf4, 0x60, 0x47, 0x95, 0x1c, 0x6a, 0x2b, 0xfa, 0xe3, 0x1c, 0x2f, 0x0d, 0x2a, 0x90, 0x43, 0x65,
|
||||
0x09, 0xbe, 0x63, 0x71, 0x33, 0xd3, 0x29, 0x31, 0xd5, 0x29, 0x26, 0xa3, 0x15, 0xc2, 0x46, 0x70,
|
||||
0xb4, 0x3e, 0x23, 0xaf, 0xb6, 0xfb, 0x87, 0x8f, 0x39, 0xf0, 0xd2, 0x3e, 0x35, 0x3c, 0xec, 0x7a,
|
||||
0xd2, 0x0f, 0xd8, 0xa4, 0x0c, 0x19, 0xc8, 0xee, 0x47, 0x7c, 0x1e, 0xd6, 0x67, 0x31, 0xe2, 0x9d,
|
||||
0xc0, 0x65, 0x64, 0x60, 0xe7, 0xd2, 0xeb, 0xe1, 0x02, 0xd5, 0x92, 0x7c, 0x51, 0xf1, 0x3b, 0x12,
|
||||
0x00, 0x65, 0xfd, 0x2b, 0x13, 0x15, 0xfa, 0x6d, 0x99, 0x1d, 0xd3, 0x03, 0x77, 0xb1, 0xb0, 0xf0,
|
||||
0x39, 0x7c, 0x27, 0x13, 0x30, 0xba, 0xff, 0x4d, 0x2e, 0xda, 0xe0, 0x37, 0xad, 0xf4, 0x49, 0x0a,
|
||||
0xdd, 0x1e, 0x87, 0x8c, 0xc9, 0x6b, 0xf8, 0xc6, 0xb3, 0x05, 0xeb, 0x6c, 0x5f, 0x84, 0x64, 0x62,
|
||||
0x1c, 0xf6, 0x04, 0x6f, 0xd7, 0xa9, 0xbc, 0x22, 0x97, 0xdb, 0x8d, 0xa5, 0xe1, 0x3a, 0x5c, 0x0d,
|
||||
0x7b, 0x78, 0x25, 0x98, 0x04, 0x7f, 0x2b, 0x59, 0x5b, 0x7c, 0xf7, 0x73, 0x37, 0x7f, 0x92, 0x8d
|
||||
};
|
||||
|
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#else
|
||||
|
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const NvU8 g_rsa3k_modulus_mutual_authentication_prod[] =
|
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{
|
||||
0xa9, 0xea, 0xc3, 0x35, 0xce, 0xfa, 0x3a, 0xdd, 0x57, 0xb2, 0x77, 0xfc, 0xa9, 0xa8, 0x60, 0x3a,
|
||||
0x4a, 0x73, 0x2e, 0x73, 0xaf, 0x2f, 0xfa, 0xcd, 0x3a, 0x62, 0xaf, 0x54, 0xe6, 0x6c, 0x31, 0x9b,
|
||||
0x4e, 0xe2, 0xff, 0x47, 0xa2, 0x3e, 0xe0, 0xbc, 0x37, 0x17, 0xd2, 0x30, 0x14, 0x73, 0x25, 0x8e,
|
||||
0x24, 0x76, 0xc0, 0xda, 0x08, 0xd1, 0x7e, 0xa6, 0xd4, 0x51, 0x32, 0x9e, 0x34, 0x47, 0xd9, 0x79,
|
||||
0x2c, 0x88, 0x8c, 0xc9, 0xf3, 0x7d, 0x89, 0x73, 0x01, 0x2d, 0x4e, 0x2e, 0x07, 0x56, 0x97, 0xf9,
|
||||
0x02, 0xc1, 0xb4, 0x77, 0x89, 0x0e, 0xc2, 0xbd, 0x1f, 0xbb, 0x5a, 0x05, 0xb3, 0x56, 0xd3, 0x03,
|
||||
0x11, 0x9b, 0x51, 0xaf, 0x59, 0x6e, 0xee, 0x70, 0xd7, 0xc7, 0x7a, 0x78, 0x4c, 0x19, 0x95, 0xf0,
|
||||
0xc2, 0xb7, 0xfb, 0xac, 0x8a, 0xa5, 0x0f, 0x79, 0x4a, 0x06, 0xcd, 0x82, 0x3d, 0x46, 0xb7, 0x02,
|
||||
0xc8, 0x91, 0x48, 0x57, 0xfb, 0x87, 0x0f, 0xa7, 0x67, 0x11, 0x1e, 0x03, 0xa4, 0x53, 0x2b, 0xdd,
|
||||
0x05, 0x5d, 0xf2, 0xb7, 0xb2, 0xbf, 0xfd, 0x15, 0x72, 0x89, 0xbc, 0xc0, 0x05, 0xea, 0xce, 0xdb,
|
||||
0x8c, 0xc1, 0xd8, 0x4c, 0xdb, 0x6f, 0x40, 0xe0, 0xde, 0x39, 0x39, 0xae, 0x5e, 0xa1, 0x45, 0x2c,
|
||||
0x57, 0x86, 0x0b, 0x57, 0x8a, 0x97, 0x66, 0xd7, 0x53, 0xf1, 0x78, 0xda, 0x74, 0x3c, 0x16, 0xd7,
|
||||
0x5c, 0xfb, 0x1a, 0xda, 0xc8, 0x2c, 0x16, 0xb9, 0x3e, 0x3a, 0x1c, 0x56, 0x3c, 0x6d, 0xe6, 0x9c,
|
||||
0x87, 0xb1, 0x54, 0x4d, 0x89, 0x17, 0x5e, 0x99, 0x88, 0x79, 0x60, 0x92, 0xe2, 0x12, 0x5b, 0x65,
|
||||
0x6b, 0x0f, 0x6f, 0x8c, 0x1c, 0xce, 0x63, 0x90, 0xbb, 0x68, 0xd0, 0x76, 0x83, 0xa4, 0xe1, 0xd6,
|
||||
0xea, 0x01, 0x0a, 0x38, 0x6c, 0xf5, 0x9e, 0x9a, 0x81, 0x16, 0x2e, 0xba, 0x27, 0x9e, 0xb9, 0x2b,
|
||||
0x8a, 0x05, 0xf6, 0xd5, 0x2b, 0x7e, 0x19, 0xa3, 0x6c, 0x90, 0x4b, 0xd8, 0xb8, 0xce, 0xd8, 0x60,
|
||||
0xb8, 0x2f, 0xe7, 0x72, 0x26, 0x41, 0x73, 0x31, 0x2c, 0xa4, 0x9b, 0x7d, 0xc3, 0x24, 0x65, 0x91,
|
||||
0xa2, 0xae, 0xd5, 0x77, 0xc6, 0xa0, 0x30, 0x15, 0xa6, 0x9f, 0x09, 0x5c, 0xb6, 0x59, 0xeb, 0x82,
|
||||
0x98, 0xae, 0xb9, 0x9c, 0x93, 0x82, 0xb3, 0xad, 0x12, 0x9c, 0xf3, 0xdb, 0xd0, 0x2c, 0x86, 0x26,
|
||||
0x67, 0xe6, 0x42, 0xe3, 0xc1, 0xea, 0xdb, 0x99, 0xbc, 0x8d, 0x4c, 0x98, 0x21, 0xa1, 0x98, 0x09,
|
||||
0x34, 0x42, 0x5e, 0xfd, 0xf4, 0x7f, 0xdf, 0x5f, 0xfa, 0x2b, 0x68, 0xdb, 0xb8, 0x5a, 0x4d, 0x14,
|
||||
0x43, 0x8b, 0x66, 0xe2, 0x9b, 0x5b, 0x83, 0xea, 0x92, 0xf9, 0x98, 0xa4, 0x6d, 0x42, 0xeb, 0x71,
|
||||
0x60, 0x98, 0x84, 0x55, 0x64, 0x23, 0x18, 0x9f, 0x76, 0x76, 0xd1, 0x74, 0xca, 0xd2, 0x65, 0xcd,
|
||||
0x00
|
||||
};
|
||||
|
||||
const NvU8 g_rsa3k_public_exponent_mutual_authentication_prod[] = {0x01, 0x00, 0x01, 0x00};
|
||||
|
||||
const NvU8 g_rsa3k_private_exponent_mutual_authentication_prod[] =
|
||||
{
|
||||
0x8d, 0x92, 0x7f, 0x37, 0x73, 0xf7, 0x7c, 0x5b, 0x59, 0x2b, 0x7f, 0x04, 0x98, 0x25, 0x78, 0x7b,
|
||||
0x0d, 0x5c, 0x3a, 0xe1, 0xa5, 0x8d, 0xdb, 0x97, 0x22, 0xbc, 0xa9, 0xd7, 0x6f, 0x04, 0xf6, 0x1c,
|
||||
0x62, 0x64, 0x84, 0x5f, 0x6c, 0xeb, 0x05, 0xb3, 0xc6, 0xf8, 0x6b, 0xc9, 0x8c, 0x87, 0x1e, 0xdd,
|
||||
0x0a, 0x49, 0xf4, 0xad, 0x37, 0xe0, 0xda, 0x2e, 0x4d, 0xff, 0xba, 0x30, 0x13, 0x27, 0x7c, 0x39,
|
||||
0xf0, 0xb0, 0xb1, 0x77, 0x03, 0xd3, 0x1d, 0x99, 0x6d, 0xfa, 0x15, 0x13, 0x2b, 0xfd, 0x65, 0x00,
|
||||
0x12, 0x3b, 0xf1, 0x51, 0x7c, 0x92, 0xd5, 0x02, 0xe1, 0xeb, 0xd2, 0xe7, 0x60, 0x64, 0x65, 0xc0,
|
||||
0x9d, 0xe2, 0x31, 0x67, 0xd6, 0x1e, 0x7c, 0x47, 0xee, 0xc8, 0x19, 0x0c, 0xa4, 0xd8, 0x0f, 0xd2,
|
||||
0x7a, 0xec, 0x3c, 0x35, 0x3e, 0xd2, 0xf0, 0x39, 0x8f, 0x87, 0xfb, 0xb6, 0xaf, 0x23, 0x3e, 0xb4,
|
||||
0x70, 0x46, 0xc2, 0x15, 0xa3, 0x26, 0x29, 0xd5, 0x31, 0x29, 0xd3, 0x33, 0x71, 0x63, 0xbe, 0x09,
|
||||
0x65, 0x43, 0x90, 0x2a, 0x0d, 0x2f, 0x1c, 0xe3, 0xfa, 0x2b, 0x6a, 0x1c, 0x95, 0x47, 0x60, 0xf4,
|
||||
0x45, 0xb5, 0x78, 0x03, 0xfc, 0x56, 0x25, 0xf7, 0xb2, 0x3a, 0x08, 0x36, 0x3d, 0x1d, 0x30, 0xef,
|
||||
0x1f, 0x63, 0x61, 0x73, 0x58, 0x13, 0x41, 0xc7, 0x84, 0x08, 0x8e, 0x32, 0x15, 0x65, 0x25, 0xe8,
|
||||
0x11, 0xea, 0x04, 0x7c, 0x20, 0xf4, 0xdd, 0x53, 0xaf, 0xfb, 0x6c, 0x65, 0xac, 0x55, 0x2d, 0x11,
|
||||
0x3c, 0x9e, 0x28, 0x46, 0xc6, 0x64, 0x98, 0x18, 0x60, 0xf4, 0x6c, 0x21, 0xb2, 0x51, 0xa9, 0xfe,
|
||||
0xb2, 0xeb, 0x50, 0xaa, 0x9a, 0x20, 0xf8, 0xc1, 0x46, 0x97, 0x77, 0x21, 0x8f, 0x2f, 0x53, 0x0a,
|
||||
0x66, 0xc4, 0x02, 0x1c, 0xfd, 0x44, 0x04, 0x49, 0x86, 0x93, 0x42, 0xde, 0xab, 0x9b, 0x9a, 0xdb,
|
||||
0x39, 0x5e, 0x87, 0xab, 0x8f, 0x85, 0x22, 0xd3, 0x38, 0x41, 0xb6, 0xf0, 0x34, 0x4b, 0xe0, 0x9a,
|
||||
0x69, 0x61, 0xb8, 0x4b, 0x01, 0xf0, 0xa6, 0xcc, 0x73, 0x98, 0xda, 0x6b, 0x12, 0xce, 0x0b, 0xbf,
|
||||
0x4d, 0x9f, 0x29, 0xda, 0x8b, 0x64, 0x8e, 0x0c, 0x9b, 0xd8, 0xa3, 0xf1, 0x44, 0xbd, 0x55, 0x37,
|
||||
0x54, 0xee, 0x4e, 0x7c, 0xbd, 0x89, 0x1b, 0x91, 0x2d, 0x2c, 0xfb, 0xa1, 0x4c, 0xfb, 0x01, 0x2b,
|
||||
0x6c, 0x8c, 0xac, 0x75, 0x37, 0xcd, 0x64, 0x75, 0xb2, 0x78, 0xd0, 0xfe, 0x8c, 0x41, 0xc7, 0xd5,
|
||||
0x8a, 0x55, 0xc4, 0xd4, 0x2b, 0x6d, 0xa2, 0xfb, 0xa7, 0xe8, 0x87, 0xd3, 0x74, 0x8c, 0x91, 0xe3,
|
||||
0x89, 0x17, 0x79, 0x10, 0x34, 0x4f, 0x39, 0x93, 0xe6, 0x33, 0x60, 0x96, 0xa6, 0xd9, 0x70, 0x47,
|
||||
0x31, 0xa0, 0x35, 0x6a, 0x58, 0x14, 0xb7, 0xb0, 0xeb, 0x0d, 0xc3, 0x6a, 0x6d, 0xc0, 0x85, 0x04
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif // _RM_SPDM_RSA_KEYS_H_
|
||||
@@ -839,6 +839,45 @@
|
||||
#define __NV_ENABLE_NONBLOCKING_OPEN EnableNonblockingOpen
|
||||
#define NV_ENABLE_NONBLOCKING_OPEN NV_REG_STRING(__NV_ENABLE_NONBLOCKING_OPEN)
|
||||
|
||||
/*
|
||||
* Option: NVreg_ImexChannelCount
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* This option allows users to specify the number of IMEX (import/export)
|
||||
* channels. Within an IMEX domain, the channels allow sharing memory
|
||||
* securely in a multi-user environment using the CUDA driver's fabric handle
|
||||
* based APIs.
|
||||
*
|
||||
* An IMEX domain is either an OS instance or a group of securely
|
||||
* connected OS instances using the NVIDIA IMEX daemon. The option must
|
||||
* be set to the same value on each OS instance within the IMEX domain.
|
||||
*
|
||||
* An IMEX channel is a logical entity that is represented by a /dev node.
|
||||
* The IMEX channels are global resources within the IMEX domain. When
|
||||
* exporter and importer CUDA processes have been granted access to the
|
||||
* same IMEX channel, they can securely share memory.
|
||||
*
|
||||
* Note that the NVIDIA driver will not attempt to create the /dev nodes. Thus,
|
||||
* the related CUDA APIs will fail with an insufficient permission error until
|
||||
* the /dev nodes are set up. The creation of these /dev nodes,
|
||||
* /dev/nvidia-caps-imex-channels/channelN, must be handled by the
|
||||
* administrator, where N is the minor number. The major number can be
|
||||
* queried from /proc/devices.
|
||||
*
|
||||
* nvidia-modprobe CLI support is available to set up the /dev nodes.
|
||||
* NVreg_ModifyDeviceFiles, NVreg_DeviceFileGID, NVreg_DeviceFileUID
|
||||
* and NVreg_DeviceFileMode will be honored by nvidia-modprobe.
|
||||
*
|
||||
* Possible values:
|
||||
* 0 - Disable IMEX using CUDA driver's fabric handles.
|
||||
* N - N IMEX channels will be enabled in the driver to facilitate N
|
||||
* concurrent users. Default value is 2048 channels, and the current
|
||||
* maximum value is 20-bit, same as Linux dev_t's minor number limit.
|
||||
*/
|
||||
#define __NV_IMEX_CHANNEL_COUNT ImexChannelCount
|
||||
#define NV_REG_IMEX_CHANNEL_COUNT NV_REG_STRING(__NV_IMEX_CHANNEL_COUNT)
|
||||
|
||||
#if defined(NV_DEFINE_REGISTRY_KEY_TABLE)
|
||||
|
||||
/*
|
||||
@@ -887,6 +926,7 @@ NV_DEFINE_REG_STRING_ENTRY(__NV_TEMPORARY_FILE_PATH, NULL);
|
||||
NV_DEFINE_REG_STRING_ENTRY(__NV_EXCLUDED_GPUS, NULL);
|
||||
NV_DEFINE_REG_ENTRY(__NV_DMA_REMAP_PEER_MMIO, NV_DMA_REMAP_PEER_MMIO_ENABLE);
|
||||
NV_DEFINE_REG_STRING_ENTRY(__NV_RM_NVLINK_BW, NULL);
|
||||
NV_DEFINE_REG_ENTRY_GLOBAL(__NV_IMEX_CHANNEL_COUNT, 2048);
|
||||
|
||||
/*
|
||||
*----------------registry database definition----------------------
|
||||
@@ -933,6 +973,7 @@ nv_parm_t nv_parms[] = {
|
||||
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_ENABLE_DBG_BREAKPOINT),
|
||||
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_OPENRM_ENABLE_UNSUPPORTED_GPUS),
|
||||
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_DMA_REMAP_PEER_MMIO),
|
||||
NV_DEFINE_PARAMS_TABLE_ENTRY(__NV_IMEX_CHANNEL_COUNT),
|
||||
{NULL, NULL}
|
||||
};
|
||||
|
||||
|
||||
@@ -621,6 +621,14 @@ typedef enum
|
||||
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
|
||||
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
|
||||
|
||||
/*
|
||||
* For console setup by EFI GOP, the base address is BAR1.
|
||||
* For console setup by VBIOS, the base address is BAR2 + 16MB.
|
||||
*/
|
||||
#define NV_IS_CONSOLE_MAPPED(nv, addr) \
|
||||
(((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \
|
||||
((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000)))
|
||||
|
||||
#define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \
|
||||
((nv)->iommus.iso_iommu_present)
|
||||
|
||||
@@ -878,6 +886,8 @@ NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *);
|
||||
NvU32 NV_API_CALL nv_get_os_type(void);
|
||||
|
||||
void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end);
|
||||
void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *);
|
||||
|
||||
struct dma_buf;
|
||||
typedef struct nv_dma_buf nv_dma_buf_t;
|
||||
struct drm_gem_object;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -160,10 +160,9 @@ NvBool NV_API_CALL os_is_vgx_hyper (void);
|
||||
NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32);
|
||||
NvBool NV_API_CALL os_is_grid_supported (void);
|
||||
NvU32 NV_API_CALL os_get_grid_csp_support (void);
|
||||
void NV_API_CALL os_get_screen_info (NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64, NvU64);
|
||||
void NV_API_CALL os_bug_check (NvU32, const char *);
|
||||
NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **, void**);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **);
|
||||
NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *);
|
||||
NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_get_euid (NvU32 *);
|
||||
@@ -198,6 +197,8 @@ nv_cap_t* NV_API_CALL os_nv_cap_create_file_entry (nv_cap_t *, const char *,
|
||||
void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *);
|
||||
int NV_API_CALL os_nv_cap_validate_and_dup_fd(const nv_cap_t *, int);
|
||||
void NV_API_CALL os_nv_cap_close_fd (int);
|
||||
NvS32 NV_API_CALL os_imex_channel_get (NvU64);
|
||||
NvS32 NV_API_CALL os_imex_channel_count (void);
|
||||
|
||||
enum os_pci_req_atomics_type {
|
||||
OS_INTF_PCIE_REQ_ATOMICS_32BIT,
|
||||
@@ -219,6 +220,7 @@ extern NvU8 os_page_shift;
|
||||
extern NvBool os_cc_enabled;
|
||||
extern NvBool os_cc_tdx_enabled;
|
||||
extern NvBool os_dma_buf_enabled;
|
||||
extern NvBool os_imex_channel_is_supported;
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -167,25 +167,11 @@ static void RmCreateOsDescriptor(NVOS32_PARAMETERS *pApi, API_SECURITY_INFO secI
|
||||
}
|
||||
else if (rmStatus == NV_ERR_INVALID_ADDRESS)
|
||||
{
|
||||
rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount,
|
||||
&pPteArray, &pPageArray);
|
||||
rmStatus = os_lookup_user_io_memory(pDescriptor, pageCount, &pPteArray);
|
||||
if (rmStatus == NV_OK)
|
||||
{
|
||||
if (pPageArray != NULL)
|
||||
{
|
||||
pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPageArray;
|
||||
pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_PAGE_ARRAY;
|
||||
}
|
||||
else if (pPteArray != NULL)
|
||||
{
|
||||
pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray;
|
||||
pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY;
|
||||
}
|
||||
else
|
||||
{
|
||||
NV_ASSERT_FAILED("unknown memory import type");
|
||||
rmStatus = NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
pApi->data.AllocOsDesc.descriptor = (NvP64)(NvUPtr)pPteArray;
|
||||
pApi->data.AllocOsDesc.descriptorType = NVOS32_DESCRIPTOR_TYPE_OS_IO_MEMORY;
|
||||
}
|
||||
}
|
||||
if (rmStatus != NV_OK)
|
||||
|
||||
@@ -1165,6 +1165,11 @@ NV_STATUS osIsVfioPciCorePresent(void)
|
||||
return os_call_vgpu_vfio((void *) &vgpu_info, CMD_VFIO_PCI_CORE_PRESENT);
|
||||
}
|
||||
|
||||
NvU32 osGetGridCspSupport(void)
|
||||
{
|
||||
return os_get_grid_csp_support();
|
||||
}
|
||||
|
||||
void initVGXSpecificRegistry(OBJGPU *pGpu)
|
||||
{
|
||||
NvU32 data32;
|
||||
|
||||
@@ -4828,6 +4828,39 @@ osRmCapInitDescriptor
|
||||
*pCapDescriptor = NV_U64_MAX;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Checks if IMEX channel support is present.
|
||||
*/
|
||||
NvBool
|
||||
osImexChannelIsSupported(void)
|
||||
{
|
||||
return os_imex_channel_is_supported;
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Returns IMEX channel count.
|
||||
*/
|
||||
NvS32
|
||||
osImexChannelCount
|
||||
(
|
||||
void
|
||||
)
|
||||
{
|
||||
return os_imex_channel_count();
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Returns IMEX channel number.
|
||||
*
|
||||
* @param[in] descriptor OS specific descriptor to query channel number.
|
||||
*
|
||||
*/
|
||||
NvS32
|
||||
osImexChannelGet(NvU64 descriptor)
|
||||
{
|
||||
return os_imex_channel_get(descriptor);
|
||||
}
|
||||
|
||||
/*
|
||||
* @brief Generates random bytes which can be used as a universally unique
|
||||
* identifier.
|
||||
|
||||
@@ -2153,6 +2153,7 @@ static NV_STATUS RmCreateMmapContextLocked(
|
||||
RsClient *pClient = staticCast(pRmClient, RsClient);
|
||||
KernelMemorySystem *pKernelMemorySystem = NULL;
|
||||
NvBool bCoherentAtsCpuOffset = NV_FALSE;
|
||||
NvBool bSriovHostCoherentFbOffset = NV_FALSE;
|
||||
nv_state_t *pNv = NULL;
|
||||
NvU64 addr = (NvU64)address;
|
||||
NvU32 prot = 0;
|
||||
@@ -2200,6 +2201,8 @@ static NV_STATUS RmCreateMmapContextLocked(
|
||||
pNv = NV_GET_NV_STATE(pGpu);
|
||||
pKernelMemorySystem = GPU_GET_KERNEL_MEMORY_SYSTEM(pGpu);
|
||||
bCoherentAtsCpuOffset = IS_COHERENT_CPU_ATS_OFFSET(pKernelMemorySystem, addr, size);
|
||||
bSriovHostCoherentFbOffset = os_is_vgx_hyper() &&
|
||||
IS_COHERENT_FB_OFFSET(pKernelMemorySystem, addr, size);
|
||||
}
|
||||
|
||||
//
|
||||
@@ -2210,7 +2213,7 @@ static NV_STATUS RmCreateMmapContextLocked(
|
||||
if ((pNv == NULL) ||
|
||||
(!IS_REG_OFFSET(pNv, addr, size) &&
|
||||
!IS_FB_OFFSET(pNv, addr, size) &&
|
||||
!bCoherentAtsCpuOffset &&
|
||||
!(bCoherentAtsCpuOffset || bSriovHostCoherentFbOffset) &&
|
||||
!IS_IMEM_OFFSET(pNv, addr, size)))
|
||||
{
|
||||
pNv = nv_get_ctl_state();
|
||||
@@ -2240,6 +2243,38 @@ static NV_STATUS RmCreateMmapContextLocked(
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
else if (bSriovHostCoherentFbOffset)
|
||||
{
|
||||
status = RmGetMmapPteArray(pKernelMemorySystem, pClient, hMemory, nvuap);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
goto done;
|
||||
}
|
||||
|
||||
//
|
||||
// nvuap->page_array(allocated in RmGetMmapPteArray) is not assigned
|
||||
// to nvamc->page_array if onlining status is false(which is the case with
|
||||
// bSriovHostCoherentFbOffset) and so doesn't get freed if not done here.
|
||||
// The call to RmGetMmapPteArray is for getting the contig and num
|
||||
// pages of the allocation.
|
||||
//
|
||||
os_free_mem(nvuap->page_array);
|
||||
nvuap->page_array = NULL;
|
||||
|
||||
//
|
||||
// This path is taken in the case of self-hosted SRIOV host where
|
||||
// the coherent GPU memory is not onlined but the CPU mapping to
|
||||
// the coherent GPU memory is done via C2C(instead of BAR1) and so
|
||||
// only contig can be supported for now.
|
||||
//
|
||||
if (!nvuap->contig && (nvuap->num_pages > 1))
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Mapping of Non-contig allocation for "
|
||||
"not onlined coherent GPU memory not supported\n");
|
||||
status = NV_ERR_NOT_SUPPORTED;
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
|
||||
if (RmSetUserMapAccessRange(nvuap) != NV_OK)
|
||||
{
|
||||
@@ -5377,16 +5412,11 @@ NvBool rm_get_uefi_console_status(
|
||||
NvU64 fbBaseAddress = 0;
|
||||
NvBool bConsoleDevice = NV_FALSE;
|
||||
|
||||
// os_get_screen_info() will return dimensions and an address for
|
||||
// any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a
|
||||
// UEFI console check the fbBaseAddress: if it was set up by the EFI GOP
|
||||
// driver, it will point into BAR1 (FB); if it was set up by the VBIOS,
|
||||
// it will point to BAR2 + 16MB.
|
||||
os_get_screen_info(&fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
|
||||
fbSize = (NvU64)fbHeight * (NvU64)fbPitch;
|
||||
//
|
||||
// nv_get_screen_info() will return dimensions and an address for
|
||||
// any fbdev driver (e.g., efifb, vesafb, etc).
|
||||
//
|
||||
nv_get_screen_info(nv, &fbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize);
|
||||
|
||||
bConsoleDevice = (fbSize != 0);
|
||||
|
||||
@@ -5403,16 +5433,11 @@ NvU64 rm_get_uefi_console_size(
|
||||
|
||||
fbSize = fbWidth = fbHeight = fbDepth = fbPitch = 0;
|
||||
|
||||
// os_get_screen_info() will return dimensions and an address for
|
||||
// any fbdev driver (e.g., efifb, vesafb, etc). To find if this is a
|
||||
// UEFI console check the fbBaseAddress: if it was set up by the EFI GOP
|
||||
// driver, it will point into BAR1 (FB); if it was set up by the VBIOS,
|
||||
// it will point to BAR2 + 16MB.
|
||||
os_get_screen_info(pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
|
||||
fbSize = (NvU64)fbHeight * (NvU64)fbPitch;
|
||||
//
|
||||
// nv_get_screen_info() will return dimensions and an address for
|
||||
// any fbdev driver (e.g., efifb, vesafb, etc).
|
||||
//
|
||||
nv_get_screen_info(nv, pFbBaseAddress, &fbWidth, &fbHeight, &fbDepth, &fbPitch, &fbSize);
|
||||
|
||||
return fbSize;
|
||||
}
|
||||
|
||||
@@ -582,13 +582,14 @@ NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *sp,
|
||||
return rmStatus;
|
||||
}
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *sp,
|
||||
gpuDeviceHandle device)
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *sp,
|
||||
gpuFaultInfo *pFaultInfo,
|
||||
NvBool bCopyAndFlush)
|
||||
{
|
||||
NV_STATUS rmStatus;
|
||||
void *fp;
|
||||
NV_ENTER_RM_RUNTIME(sp,fp);
|
||||
rmStatus = nvGpuOpsFlushReplayableFaultBuffer(device);
|
||||
rmStatus = nvGpuOpsFlushReplayableFaultBuffer(pFaultInfo, bCopyAndFlush);
|
||||
NV_EXIT_RM_RUNTIME(sp,fp);
|
||||
return rmStatus;
|
||||
}
|
||||
|
||||
@@ -348,7 +348,7 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
|
||||
|
||||
if ((memmgrGetReservedConsoleMemDesc(pGpu, pMemoryManager) != NULL) && bContinue)
|
||||
{
|
||||
NvU64 baseAddr;
|
||||
NvU64 baseAddr, size;
|
||||
NvU32 width, height, depth, pitch;
|
||||
|
||||
// There should only be one.
|
||||
@@ -357,9 +357,8 @@ NV_STATUS deviceCtrlCmdOsUnixVTGetFBInfo_IMPL
|
||||
pParams->subDeviceInstance = gpumgrGetSubDeviceInstanceFromGpu(pGpu);
|
||||
|
||||
// Console is either mapped to BAR1 or BAR2 + 16 MB
|
||||
os_get_screen_info(&baseAddr, &width, &height, &depth, &pitch,
|
||||
nv->bars[NV_GPU_BAR_INDEX_FB].cpu_address,
|
||||
nv->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000);
|
||||
nv_get_screen_info(nv, &baseAddr, &width, &height, &depth,
|
||||
&pitch, &size);
|
||||
|
||||
pParams->width = (NvU16)width;
|
||||
pParams->height = (NvU16)height;
|
||||
|
||||
@@ -622,7 +622,7 @@ NV_STATUS NV_API_CALL rm_gpu_copy_mmu_faults(
|
||||
|
||||
// Copies all valid packets in RM's and client's shadow buffer
|
||||
status = kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, &threadState, faultsCopied,
|
||||
NON_REPLAYABLE_FAULT_BUFFER);
|
||||
NON_REPLAYABLE_FAULT_BUFFER, NV_FALSE);
|
||||
|
||||
threadStateFreeISRAndDeferredIntHandler(&threadState, pGpu, THREAD_STATE_FLAGS_IS_ISR);
|
||||
tlsIsrDestroy(pIsrAllocator);
|
||||
@@ -659,7 +659,7 @@ static NV_STATUS _rm_gpu_copy_mmu_faults_unlocked(
|
||||
|
||||
// Copies all valid packets in RM's and client's shadow buffer
|
||||
return kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, pThreadState, pFaultsCopied,
|
||||
NON_REPLAYABLE_FAULT_BUFFER);
|
||||
NON_REPLAYABLE_FAULT_BUFFER, NV_FALSE);
|
||||
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user