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570.211.01

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This commit is contained in:
Bernhard Stoeckner
2026-01-13 18:15:41 +01:00
parent a973de26cc
commit 498793d5e2
18 changed files with 194 additions and 61 deletions
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20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r570_00
#define NV_BUILD_BRANCH r573_96
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r570_00
#define NV_PUBLIC_BRANCH r573_96
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r570_00-658"
#define NV_BUILD_CHANGELIST_NUM (36886698)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r573_96-1"
#define NV_BUILD_CHANGELIST_NUM (36945344)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r570_00-658"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36886698)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r573_96-1"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36945344)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r570_00-640"
#define NV_BUILD_CHANGELIST_NUM (36886698)
#define NV_BUILD_BRANCH_VERSION "r573_96-648"
#define NV_BUILD_CHANGELIST_NUM (36918590)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "573.92"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36886698)
#define NV_BUILD_NAME "573.95"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36918590)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.207"
#define NV_VERSION_STRING "570.211.01"
#else

71
src/common/inc/swref/published/ada/ad102/dev_nv_pcfg_xve_regmap.h Normal file
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@@ -0,0 +1,71 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __dev_nv_pcfg_xve_regmap_h__
#define __dev_nv_pcfg_xve_regmap_h__
#define NV_PCFG_XVE_REGISTER_MAP_START_OFFSET 0x00088000
/*
* <prefix>_MAP has 1 bit set for each dword register.
* <prefix>_COUNT has total number of set bits in <prefix>_MAP.
*/
#define NV_PCFG_XVE_REGISTER_VALID_COUNT 474
#define NV_PCFG_XVE_REGISTER_VALID_MAP { \
/* 0x00088000 */ 0xFFF1FFFF, 0x101FFF9F, \
/* 0x00088100 */ 0x3FFA3C7F, 0x00000000, \
/* 0x00088200 */ 0x03F00000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x8007FFC0, 0x3F3F5807, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA1F, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0xFFEFDFD7, 0x1EDAFFFF, \
/* 0x00088900 */ 0xFFFFFFFF, 0x006FFFFF, \
/* 0x00088A00 */ 0xFF7FFFFF, 0x0007FFFF, \
/* 0x00088B00 */ 0x00000000, 0xFFFFF000, \
/* 0x00088C00 */ 0x0007BFE7, 0xFFC003FC, \
/* 0x00088D00 */ 0xFFFFFFFF, 0x7C1F3FFF, \
/* 0x00088E00 */ 0xFFFFFFFF, 0x00FFFFFF, \
/* 0x00088F00 */ 0x00000000, 0xFF000000 }
#define NV_PCFG_XVE_REGISTER_WR_COUNT 352
#define NV_PCFG_XVE_REGISTER_WR_MAP { \
/* 0x00088000 */ 0x3EF193FA, 0x1007C505, \
/* 0x00088100 */ 0x3FFA0828, 0x00000000, \
/* 0x00088200 */ 0x03200000, 0x00000000, \
/* 0x00088300 */ 0x00000000, 0x00000000, \
/* 0x00088400 */ 0x80007EC0, 0x3F075007, \
/* 0x00088500 */ 0x000000BF, 0x00000000, \
/* 0x00088600 */ 0x0140AA10, 0x00000000, \
/* 0x00088700 */ 0x00013FFF, 0x00000000, \
/* 0x00088800 */ 0x004C5FC3, 0x1C5AFFC0, \
/* 0x00088900 */ 0xFFFC7804, 0x006FFFFF, \
/* 0x00088A00 */ 0xFF7FFDFD, 0x00007FFF, \
/* 0x00088B00 */ 0x00000000, 0xF8A54000, \
/* 0x00088C00 */ 0x00003C01, 0x3FC003FC, \
/* 0x00088D00 */ 0xFFFFFFFC, 0x701B2C3F, \
/* 0x00088E00 */ 0xFFFFFFF8, 0x00FFBFFF, \
/* 0x00088F00 */ 0x00000000, 0xFF000000 }
#endif // {__dev_nv_pcfg_xve_regmap_h__}

4
src/nvidia/arch/nvalloc/unix/src/osapi.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -350,7 +350,7 @@ RmLogGpuCrash(OBJGPU *pGpu)
"NVRM: A GPU crash dump has been created. If possible, please run\n"
"NVRM: nvidia-bug-report.sh as root to collect this data before\n"
"NVRM: the NVIDIA kernel module is unloaded.\n");
if (hypervisorIsVgxHyper())
if (!IS_GSP_CLIENT(pGpu) && hypervisorIsVgxHyper())
{
nv_printf(NV_DBG_ERRORS, "NVRM: Dumping nvlogs buffers\n");
nvlogDumpToKernelLog(NV_FALSE);

8
src/nvidia/generated/g_kernel_bif_nvoc.c
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@@ -720,7 +720,7 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner *
pThis->__kbifDoFunctionLevelReset__ = &kbifDoFunctionLevelReset_GH100;
}
// kbifInitXveRegMap -- halified (3 hals) body
// kbifInitXveRegMap -- halified (4 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x00000400UL) )) /* ChipHal: GA100 */
{
pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_GA100;
@@ -729,6 +729,10 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner *
{
pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_TU102;
}
else if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f00000UL) )) /* ChipHal: AD102 | AD103 | AD104 | AD106 | AD107 */
{
pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_AD102;
}
else
{
pThis->__kbifInitXveRegMap__ = &kbifInitXveRegMap_GA102;
@@ -1120,7 +1124,7 @@ static void __nvoc_init_funcTable_KernelBif_1(KernelBif *pThis, RmHalspecOwner *
{
pThis->__kbifDoSecondaryBusHotReset__ = &kbifDoSecondaryBusHotReset_GH100;
}
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 160 basic block(s).
} // End __nvoc_init_funcTable_KernelBif_1 with approximately 161 basic block(s).
// Initialize vtable(s) for 75 virtual method(s).

4
src/nvidia/generated/g_kernel_bif_nvoc.h
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@@ -213,7 +213,7 @@ struct KernelBif {
void (*__kbifProbePcieCplAtomicCaps__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
void (*__kbifReadPcieCplCapsFromConfigSpace__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32 *); // halified (3 hals) body
NV_STATUS (*__kbifDoFunctionLevelReset__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (2 hals) body
NV_STATUS (*__kbifInitXveRegMap__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU8); // halified (3 hals) body
NV_STATUS (*__kbifInitXveRegMap__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU8); // halified (4 hals) body
NvU32 (*__kbifGetMSIXTableVectorControlSize__)(struct OBJGPU *, struct KernelBif * /*this*/); // halified (3 hals) body
NV_STATUS (*__kbifConfigAccessWait__)(struct OBJGPU *, struct KernelBif * /*this*/, RMTIMEOUT *); // halified (3 hals) body
NV_STATUS (*__kbifGetPciConfigSpacePriMirror__)(struct OBJGPU *, struct KernelBif * /*this*/, NvU32 *, NvU32 *); // halified (2 hals) body
@@ -1226,6 +1226,8 @@ NV_STATUS kbifInitXveRegMap_GA100(struct OBJGPU *pGpu, struct KernelBif *pKernel
NV_STATUS kbifInitXveRegMap_GA102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg3);
NV_STATUS kbifInitXveRegMap_AD102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif, NvU8 arg3);
NvU32 kbifGetMSIXTableVectorControlSize_TU102(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);
NvU32 kbifGetMSIXTableVectorControlSize_GH100(struct OBJGPU *pGpu, struct KernelBif *pKernelBif);

6
src/nvidia/interface/nvrm_registry.h
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@@ -2576,12 +2576,6 @@
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001
// Type DWORD
// Allows extending PMU FB Operationg Timeout (DMA / FBFlush) on certain profiles
// This currently takes effect on GB10X profile only
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US "RmPmuFBTimeoutUs"
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US_DEFAULT (0)
//
// Type: Dword
//

61
src/nvidia/src/kernel/gpu/bif/arch/ada/kernel_bif_ad102.c
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -27,9 +27,14 @@
#include "published/ada/ad102/dev_bus.h"
#include "published/ada/ad102/dev_bus_addendum.h"
#include "published/ada/ad102/dev_nv_pcfg_xve_regmap.h"
static NvBool _kbifPreOsCheckErotGrantAllowed_AD102(OBJGPU *pGpu, void *pVoid);
// XVE register map for PCIe config space
static const NvU32 xveRegMapValid[] = NV_PCFG_XVE_REGISTER_VALID_MAP;
static const NvU32 xveRegMapWrite[] = NV_PCFG_XVE_REGISTER_WR_MAP;
/*!
* Signals preOs to have eRoT hand over control of EEPROM to RM
*
@@ -85,3 +90,57 @@ _kbifPreOsCheckErotGrantAllowed_AD102
return FLD_TEST_DRF(_PBUS, _SW_GLOBAL_EROT_GRANT, _ALLOW, _YES, reg);
}
/*!
* This function setups the xve register map pointers
*
* @param[in] pGpu GPU object pointer
* @param[in] pKernelBif KernelBif object pointer
* @param[in] func PCIe function number
*
* @return 'NV_OK' if successful, an RM error code otherwise.
*
* Todo by rjindal: (Bug: 5020203) Create an IMPL for kbifInitXveRegMap
* and reduce the HALs for this function in a cleanup CL.
*/
NV_STATUS
kbifInitXveRegMap_AD102
(
OBJGPU *pGpu,
KernelBif *pKernelBif,
NvU8 func
)
{
extern NvU32 kbifInitXveRegMap_GM107(OBJGPU *pGpu, KernelBif *pKernelBif, NvU8 func);
NV_STATUS status = NV_OK;
NvU32 controlSize = 0;
if (func == 0)
{
pKernelBif->xveRegmapRef[0].nFunc = 0;
pKernelBif->xveRegmapRef[0].xveRegMapValid = xveRegMapValid;
pKernelBif->xveRegmapRef[0].xveRegMapWrite = xveRegMapWrite;
pKernelBif->xveRegmapRef[0].numXveRegMapValid = NV_ARRAY_ELEMENTS(xveRegMapValid);
pKernelBif->xveRegmapRef[0].numXveRegMapWrite = NV_ARRAY_ELEMENTS(xveRegMapWrite);
pKernelBif->xveRegmapRef[0].bufBootConfigSpace = pKernelBif->cacheData.gpuBootConfigSpace;
// Each MSIX table entry is 4 NvU32s
controlSize = kbifGetMSIXTableVectorControlSize_HAL(pGpu, pKernelBif);
if (pKernelBif->xveRegmapRef[0].bufMsixTable == NULL)
pKernelBif->xveRegmapRef[0].bufMsixTable = portMemAllocNonPaged(controlSize * 4 * sizeof(NvU32));
NV_ASSERT_OR_RETURN(pKernelBif->xveRegmapRef[0].bufMsixTable != NULL, NV_ERR_NO_MEMORY);
}
else if (func == 1)
{
// Init regmap for Fn1 using older HAL
status = kbifInitXveRegMap_GM107(pGpu, pKernelBif, 1);
}
else
{
NV_PRINTF(LEVEL_ERROR, "Invalid argument, func: %d.\n", func);
NV_ASSERT(0);
status = NV_ERR_INVALID_ARGUMENT;
}
return status;
}