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570.172.08

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This commit is contained in:
Bernhard Stoeckner
2025-07-17 17:17:18 +02:00
parent 4b30f4cde1
commit 4d6c416e7f
25 changed files with 213 additions and 182 deletions
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4
src/common/displayport/inc/dp_connectorimpl.h
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@@ -260,6 +260,8 @@ namespace DisplayPort
// Flag to check if the system is UEFI.
bool bIsUefiSystem;
bool bSkipResetLinkStateDuringPlug;
// Flag to check if LT should be skipped.
bool bSkipLt;
@@ -343,6 +345,8 @@ namespace DisplayPort
bool bEnableLowerBppCheckForDsc;
bool bSkipSettingLinkStateDuringUnplug;
//
// Dual SST Partner connector object pointer
ConnectorImpl *pCoupledConnector;

15
src/common/displayport/inc/dp_regkeydatabase.h
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@@ -90,21 +90,23 @@
//
// Bug 4388987 : This regkey will disable reading PCON caps for MST.
//
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
#define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED "DP_BUG_4388987_WAR"
#define NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION "DP_DISABLE_TUNNEL_BW_ALLOCATION"
// Bug 4793112 : On eDP panel, do not cache source OUI if it reads zero
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_DISABLE_FIX_FOR_5019537 "DP_DISABLE_5019537_FIX"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
#define NV_DP_REGKEY_DISABLE_FIX_FOR_5019537 "DP_DISABLE_5019537_FIX"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
// Bug 5041041 : Enable Lower BPP check for DSC
#define NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC "DP_ENABLE_LOWER_BPP_CHECK"
#define NV_DP_REGKEY_SKIP_SETTING_LINK_STATE_DURING_UNPLUG "DP_SKIP_SETTING_LINK_STATE_DURING_UNPLUG"
// Data Base used to store all the regkey values.
// The actual data base is declared statically in dp_evoadapter.cpp.
@@ -147,6 +149,7 @@ struct DP_REGKEY_DATABASE
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableLowerBppCheckForDsc;
bool bSkipSettingLinkStateDuringUnplug;
};
extern struct DP_REGKEY_DATABASE dpRegkeyDatabase;

42
src/common/displayport/src/dp_connectorimpl.cpp
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@@ -171,21 +171,22 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bKeepLinkAliveMST = dpRegkeyDatabase.bOptLinkKeptAliveMst;
this->bKeepLinkAliveSST = dpRegkeyDatabase.bOptLinkKeptAliveSst;
}
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
this->bReportDeviceLostBeforeNew = dpRegkeyDatabase.bReportDeviceLostBeforeNew;
this->bDisableSSC = dpRegkeyDatabase.bSscDisabled;
this->bEnableFastLT = dpRegkeyDatabase.bFastLinkTrainingEnabled;
this->bDscMstCapBug3143315 = dpRegkeyDatabase.bDscMstCapBug3143315;
this->bPowerDownPhyBeforeD3 = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
this->bReassessMaxLink = dpRegkeyDatabase.bReassessMaxLink;
if (dpRegkeyDatabase.applyMaxLinkRateOverrides)
{
this->maxLinkRateFromRegkey = hal->mapLinkBandiwdthToLinkrate(dpRegkeyDatabase.applyMaxLinkRateOverrides); // BW to linkrate
this->maxLinkRateFromRegkey = hal->mapLinkBandiwdthToLinkrate(dpRegkeyDatabase.applyMaxLinkRateOverrides); // BW to linkrate
}
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bDisable5019537Fix = dpRegkeyDatabase.bDisable5019537Fix;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableLowerBppCheckForDsc = dpRegkeyDatabase.bEnableLowerBppCheckForDsc;
this->bForceDisableTunnelBwAllocation = dpRegkeyDatabase.bForceDisableTunnelBwAllocation;
this->bSkipZeroOuiCache = dpRegkeyDatabase.bSkipZeroOuiCache;
this->bDisable5019537Fix = dpRegkeyDatabase.bDisable5019537Fix;
this->bForceHeadShutdownFromRegkey = dpRegkeyDatabase.bForceHeadShutdown;
this->bEnableLowerBppCheckForDsc = dpRegkeyDatabase.bEnableLowerBppCheckForDsc;
this->bSkipSettingLinkStateDuringUnplug = dpRegkeyDatabase.bSkipSettingLinkStateDuringUnplug;
}
void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -945,6 +946,7 @@ Group * ConnectorImpl::resume(bool firmwareLinkHandsOff,
activeGroups.insertBack((GroupImpl *)firmwareGroup);
result = firmwareGroup;
bSkipResetLinkStateDuringPlug = true;
}
hal->overrideMultiStreamCap(bAllowMST);
@@ -6781,6 +6783,15 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
// Tear down old message manager
DP_ASSERT( !hal->getSupportsMultistream() || (hal->isAtLeastVersion(1, 2) && " Device supports multistream but not DP 1.2 !?!? "));
if (this->bSkipSettingLinkStateDuringUnplug)
{
if (!bSkipResetLinkStateDuringPlug)
{
linkState = DP_TRANSPORT_MODE_INIT;
}
bSkipResetLinkStateDuringPlug = false;
}
// Check if we should be attempting a transition between MST<->SST
if (main->hasMultistream())
{
@@ -7101,7 +7112,12 @@ void ConnectorImpl::notifyLongPulseInternal(bool statusConnected)
bKeepOptLinkAlive = false;
bNoFallbackInPostLQA = false;
bDscCapBasedOnParent = false;
linkState = DP_TRANSPORT_MODE_INIT;
if (!this->bSkipSettingLinkStateDuringUnplug)
{
linkState = DP_TRANSPORT_MODE_INIT;
}
linkAwaitingTransition = false;
}

63
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -76,37 +76,38 @@ const struct
DP_REG_VAL_TYPE valueType;
} DP_REGKEY_TABLE [] =
{
{NV_DP_REGKEY_OVERRIDE_DPCD_REV, &dpRegkeyDatabase.dpcdRevOveride, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_SSC, &dpRegkeyDatabase.bSscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING, &dpRegkeyDatabase.bFastLinkTrainingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_MST, &dpRegkeyDatabase.bMstDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING, &dpRegkeyDatabase.bInbandStereoSignalingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_POWEROFF_EDP_IN_HEAD_DETACH, &dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_OCA_LOGGING, &dpRegkeyDatabase.bOcaLoggingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REPORT_DEVICE_LOST_BEFORE_NEW, &dpRegkeyDatabase.bReportDeviceLostBeforeNew, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_LINK_BW_OVERRIDE_WAR, &dpRegkeyDatabase.bLinkBwOverrideWarApplied, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES, &dpRegkeyDatabase.applyMaxLinkRateOverrides, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND, &dpRegkeyDatabase.bHdcpAuthOnlyOnDemand, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL}
{NV_DP_REGKEY_OVERRIDE_DPCD_REV, &dpRegkeyDatabase.dpcdRevOveride, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_SSC, &dpRegkeyDatabase.bSscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FAST_LINK_TRAINING, &dpRegkeyDatabase.bFastLinkTrainingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_MST, &dpRegkeyDatabase.bMstDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_INBAND_STEREO_SIGNALING, &dpRegkeyDatabase.bInbandStereoSignalingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_POWEROFF_EDP_IN_HEAD_DETACH, &dpRegkeyDatabase.bPoweroffEdpInHeadDetachSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_OCA_LOGGING, &dpRegkeyDatabase.bOcaLoggingEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REPORT_DEVICE_LOST_BEFORE_NEW, &dpRegkeyDatabase.bReportDeviceLostBeforeNew, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_LINK_BW_OVERRIDE_WAR, &dpRegkeyDatabase.bLinkBwOverrideWarApplied, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES, &dpRegkeyDatabase.applyMaxLinkRateOverrides, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND, &dpRegkeyDatabase.bHdcpAuthOnlyOnDemand, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_SST, &dpRegkeyDatabase.bOptLinkKeptAliveSst, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_EDP_ILR, &dpRegkeyDatabase.bBypassEDPRevCheck, DP_REG_VAL_BOOL},
{NV_DP_DSC_MST_CAP_BUG_3143315, &dpRegkeyDatabase.bDscMstCapBug3143315, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_POWER_DOWN_PHY, &dpRegkeyDatabase.bPowerDownPhyBeforeD3, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_REASSESS_MAX_LINK, &dpRegkeyDatabase.bReassessMaxLink, DP_REG_VAL_BOOL},
{NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT, &dpRegkeyDatabase.supportInternalUhbrOnFpga, DP_REG_VAL_U32},
{NV_DP2X_IGNORE_CABLE_ID_CAPS, &dpRegkeyDatabase.bIgnoreCableIdCaps, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED, &dpRegkeyDatabase.bMSTPCONCapsReadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_TUNNEL_BW_ALLOCATION, &dpRegkeyDatabase.bForceDisableTunnelBwAllocation, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_SETTING_LINK_STATE_DURING_UNPLUG, &dpRegkeyDatabase.bSkipSettingLinkStateDuringUnplug, DP_REG_VAL_BOOL}
};
EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

20
src/common/inc/nvBldVer.h
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@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r570_00
#define NV_BUILD_BRANCH r573_48
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r570_00
#define NV_PUBLIC_BRANCH r573_48
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r570_00-486"
#define NV_BUILD_CHANGELIST_NUM (36118394)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/r573_48-509"
#define NV_BUILD_CHANGELIST_NUM (36220323)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/r570_00-486"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36118394)
#define NV_BUILD_NAME "rel/gpu_drv/r570/r573_48-509"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36220323)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r570_00-483"
#define NV_BUILD_CHANGELIST_NUM (36118394)
#define NV_BUILD_BRANCH_VERSION "r573_48-4"
#define NV_BUILD_CHANGELIST_NUM (36212872)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "573.42"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36118394)
#define NV_BUILD_NAME "573.55"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36212872)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.169"
#define NV_VERSION_STRING "570.172.08"
#else

14
src/nvidia/arch/nvalloc/common/inc/nvpcie.h
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@@ -224,6 +224,20 @@
#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE 0x00503250
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0 0x000000D4
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_ID 7:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_NEXT 15:8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_LENGTH 23:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_0_SIG_LO 31:24
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1 0x000000D8
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_SIG_HI 15:0
#define NV_PCI_VIRTUAL_CONFIG_BITS_CAP_1_VALUE 31:16
#define NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE 0x00535442 //"BTS"
// Allocation of _VALUE bits
#define NV_PCI_VIRTUAL_CONFIG_BITS_PCI_EGRESS_POISON_ENABLE 0:0
// Chipset-specific definitions.
// Intel SantaRosa definitions
#define INTEL_2A00_CONFIG_SPACE_BASE 0x60

1
src/nvidia/generated/g_gpu_nvoc.h
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@@ -1218,6 +1218,7 @@ struct OBJGPU {
NvBool gspRmInitialized;
NV_PM_DEPTH powerManagementDepth;
_GPU_PCIE_PEER_CLIQUE pciePeerClique;
NvU16 virtualConfigBits;
NvBool bGspNocatEnabled;
NvU32 i2cPortForExtdev;
GPUIDINFO idInfo;

2
src/nvidia/generated/g_nv_name_released.h
View File

@@ -5451,8 +5451,10 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2D39, 0x0000, 0x0000, "NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU" },
{ 0x2D58, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Laptop GPU" },
{ 0x2D59, 0x0000, 0x0000, "NVIDIA GeForce RTX 5060 Laptop GPU" },
{ 0x2D98, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2DB8, 0x0000, 0x0000, "NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU" },
{ 0x2DB9, 0x0000, 0x0000, "NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU" },
{ 0x2DD8, 0x0000, 0x0000, "NVIDIA GeForce RTX 5050 Laptop GPU" },
{ 0x2F04, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070" },
{ 0x2F18, 0x0000, 0x0000, "NVIDIA GeForce RTX 5070 Ti Laptop GPU" },
{ 0x2F38, 0x0000, 0x0000, "NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU" },

1
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
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@@ -218,6 +218,7 @@ typedef struct GspSystemInfo
NvBool bRouteDispIntrsToCPU;
NvU64 hostPageSize;
NvBool bGspNocatEnabled;
NvU16 virtualConfigBits;
} GspSystemInfo;

3
src/nvidia/interface/gsp_abi_check.c
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@@ -369,6 +369,9 @@ ABI_CHECK_FIELD(GspSystemInfo, bFeatureStretchVblankCapable, 910, 1);
ABI_CHECK_FIELD(GspSystemInfo, bEnableDynamicGranularityPageArrays, 911, 1);
ABI_CHECK_FIELD(GspSystemInfo, bClockBoostSupported, 912, 1);
ABI_CHECK_FIELD(GspSystemInfo, bRouteDispIntrsToCPU, 913, 1);
ABI_CHECK_FIELD(GspSystemInfo, hostPageSize, 920, 8);
ABI_CHECK_FIELD(GspSystemInfo, bGspNocatEnabled, 928, 1);
ABI_CHECK_FIELD(GspSystemInfo, virtualConfigBits, 930, 2);
ABI_CHECK_SIZE_EQ(JT_METHOD_DATA, 12);

76
src/nvidia/src/kernel/gpu/external_device/arch/kepler/kern_gsync_p2060.c
View File

@@ -2441,14 +2441,6 @@ gsyncProgramMaster_P2060
"Failed to drive stereo output pin for bug3362661.\n");
}
//
// Set the RasterSync Decode Mode
// This may return an error if the FW and GPU combination is invalid
// In this case, the ServerGpu is the same Gpu
//
NV_CHECK_OK_OR_RETURN(LEVEL_WARNING,
pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pGpu, pGsync->pExtDev));
//
// GPU will now be TS - Mark sync source for GPU on derived index.
// This needs to be done first as only TS can write I_AM_MASTER bit.
@@ -2729,8 +2721,6 @@ gsyncProgramSlaves_P2060
NvBool bCoupled, bHouseSelect, bLocalMaster, bEnableSlaves = (0 != Slaves);
NV_STATUS rmStatus = NV_OK;
NvU32 numHeads = kdispGetNumHeads(pKernelDisplay);
OBJSYS *pSys = SYS_GET_INSTANCE();
OBJGSYNCMGR *pGsyncMgr = SYS_GET_GSYNCMGR(pSys);
// This utility fn returns display id's associated with each head.
extdevGetBoundHeadsAndDisplayIds(pGpu, DisplayIds);
@@ -2815,72 +2805,6 @@ gsyncProgramSlaves_P2060
}
}
//
// The RasterSyncDecodeMode of this Gsync board needs to get written if
// the server GPU is not on it. Find the server GPU and write based on that
// GPU's RasterSyncDecodeMode value.
//
if (bEnableSlaves && !bLocalMaster && pGsyncMgr->gsyncCount > 1)
{
OBJGPU *pServerGpu = NULL;
NvU32 otherGsyncIndex;
// Loops only need to go until we find pServerGpu
for (otherGsyncIndex = 0;
(otherGsyncIndex < pGsyncMgr->gsyncCount) && (pServerGpu == NULL);
otherGsyncIndex++)
{
DACP2060EXTERNALDEVICE *pOtherExtDev =
(DACP2060EXTERNALDEVICE *)pGsyncMgr->gsyncTable[otherGsyncIndex].pExtDev;
NvU32 otherIfaceIndex;
if (pOtherExtDev == pThis)
{
//
// If the server GPU is on this same GSync board, we don't need
// to write anything, so don't bother checking
//
continue;
}
for (otherIfaceIndex = 0;
(otherIfaceIndex < NV_P2060_MAX_IFACES_PER_GSYNC) && (pServerGpu == NULL);
otherIfaceIndex++)
{
NvU32 otherHeadIndex;
NvU32 serverBitmask = 0;
if (!pOtherExtDev->Iface[otherIfaceIndex].GpuInfo.connected)
{
continue;
}
for (otherHeadIndex = 0; otherHeadIndex < OBJ_MAX_HEADS; otherHeadIndex++)
{
serverBitmask |= pOtherExtDev->Iface[otherIfaceIndex].Sync.Master[otherHeadIndex];
}
if (serverBitmask == 0)
{
continue;
}
// This GPU is the server!
pServerGpu = gpumgrGetGpuFromId(pOtherExtDev->Iface[otherIfaceIndex].GpuInfo.gpuId);
}
}
if (pServerGpu != NULL)
{
//
// Set the RasterSync Decode Mode
// This may return an error if the FW and GPU combination is invalid
//
NV_CHECK_OK_OR_RETURN(LEVEL_WARNING,
pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pServerGpu, pGsync->pExtDev));
}
}
//
// With House sync enabled the crashlocking still need some investigations.
// So filter out Housesyced systems before doing local crashlocks.

14
src/nvidia/src/kernel/gpu/external_device/gsync.c
View File

@@ -395,7 +395,19 @@ gsyncAttachGpu(PDACEXTERNALDEVICE pExtDev, OBJGPU *pGpu,
pSys->setProperty(pSys, PDB_PROP_SYS_IS_GSYNC_ENABLED, NV_TRUE);
return gsyncStartupProvider(pGsync, externalDevice);
NV_ASSERT_OK_OR_RETURN(gsyncStartupProvider(pGsync, externalDevice));
if (pGsync->gpuCount == 1)
{
//
// Initialize the RasterSyncDecodeMode here.
// The timing source needs to agree with this, but all GPUs on the GSync
// should be the same, so we will use the type of the first GPU
//
NV_ASSERT_OK_OR_RETURN(pGsync->gsyncHal.gsyncSetRasterSyncDecodeMode(pGpu, pGpu, pGsync->pExtDev));
}
return NV_OK;
}
//

15
src/nvidia/src/kernel/gpu/fifo/arch/volta/kernel_channel_group_gv100.c
View File

@@ -92,12 +92,6 @@ kchangrpAllocFaultMethodBuffers_GV100
{
// Get the right aperture/attribute
faultBufApert = ADDR_SYSMEM;
if (bReUseInitMem)
{
faultBufApert = ADDR_FBMEM;
}
faultBufAttr = NV_MEMORY_CACHED;
memdescOverrideInstLoc(DRF_VAL(_REG_STR_RM, _INST_LOC_3, _FAULT_METHOD_BUFFER, pGpu->instLocOverrides3),
"fault method buffer", &faultBufApert, &faultBufAttr);
@@ -110,6 +104,7 @@ kchangrpAllocFaultMethodBuffers_GV100
{
pFaultMthdBuf = &(pKernelChannelGroup->pMthdBuffers[index]);
retryInFB:
// Allocate and initialize MEMDESC
status = memdescCreate(&(pFaultMthdBuf->pMemDesc), pGpu, bufSizeInBytes, 0,
NV_TRUE, faultBufApert, faultBufAttr, memDescFlags);
@@ -123,9 +118,15 @@ kchangrpAllocFaultMethodBuffers_GV100
pFaultMthdBuf->pMemDesc);
if (status != NV_OK)
{
DBG_BREAKPOINT();
memdescDestroy(pFaultMthdBuf->pMemDesc);
pFaultMthdBuf->pMemDesc = NULL;
if (bReUseInitMem && (faultBufApert == ADDR_SYSMEM))
{
faultBufApert = ADDR_FBMEM;
memDescFlags |= MEMDESC_FLAGS_OWNED_BY_CURRENT_DEVICE;
goto retryInFB;
}
DBG_BREAKPOINT();
goto fail;
}

10
src/nvidia/src/kernel/gpu/intr/intr.c
View File

@@ -1321,6 +1321,8 @@ void intrProcessDPCQueue_IMPL
DPCQUEUE *pDPCQueue = &pIntr->dpcQueue;
MC_ENGINE_BITVECTOR pendingEngines;
NvU16 nextEngine;
KernelGmmu *pKernelGmmu = GPU_GET_KERNEL_GMMU(pGpu);
NvU32 faultsCopied = 0;
do
{
@@ -1353,6 +1355,14 @@ void intrProcessDPCQueue_IMPL
if (!bitVectorTestAllCleared(&pendingEngines))
{
nextEngine = bitVectorCountTrailingZeros(&pendingEngines);
//
// Service Non-Replayable interrupt in bottom-half
// in case it is triggered while handling other software events like p-state in VGPU.
//
if (IS_VIRTUAL(pGpu) && (nextEngine == MC_ENGINE_IDX_NON_REPLAYABLE_FAULT))
{
kgmmuCopyMmuFaults_HAL(pGpu, pKernelGmmu, NULL, &faultsCopied, NON_REPLAYABLE_FAULT_BUFFER, NV_FALSE);
}
intrQueueInterruptBasedDpc(pGpu, pIntr, nextEngine);
bitVectorCopy(&pIntr->pmcIntrPending, &pendingEngines);
bitVectorClr(&pIntr->pmcIntrPending, nextEngine);

6
src/nvidia/src/kernel/gpu/mem_mgr/arch/maxwell/mem_mgr_gm107.c
View File

@@ -287,7 +287,11 @@ memmgrSetZbcReferenced
subDevInst = gpumgrGetSubDeviceInstanceFromGpu(pGpu);
NV_ASSERT_OR_RETURN_VOID(subdeviceGetByInstance(pClient, hDevice, subDevInst, &pSubdevice) == NV_OK);
if (subdeviceGetByInstance(pClient, hDevice, subDevInst, &pSubdevice) != NV_OK)
{
NV_PRINTF(LEVEL_INFO, "Found no subdevice for the ZBC surface\n");
return;
}
hSubdevice = RES_GET_HANDLE(pSubdevice);

55
src/nvidia/src/kernel/platform/chipset/chipset_pcie.c
View File

@@ -73,6 +73,7 @@ static void objClGpuMapEnhCfgSpace(OBJGPU *, OBJCL *);
static void objClGpuUnmapEnhCfgSpace(OBJGPU *);
static NV_STATUS objClGpuIs3DController(OBJGPU *);
static void objClLoadPcieVirtualP2PApproval(OBJGPU *);
static void objClLoadPcieVirtualConfigBits(OBJGPU *);
static void _objClAdjustTcVcMap(OBJGPU *, OBJCL *, PORTDATA *);
static void _objClGetDownstreamAtomicsEnabledMask(void *, NvU32, NvU32 *);
static void _objClGetUpstreamAtomicRoutingCap(void *, NvU32, NvBool *);
@@ -956,6 +957,9 @@ clUpdatePcieConfig_IMPL(OBJGPU *pGpu, OBJCL *pCl)
// Load PCI Express virtual P2P approval config
objClLoadPcieVirtualP2PApproval(pGpu);
// Load additional configuraiton bits from virtualized cfg space
objClLoadPcieVirtualConfigBits(pGpu);
//
// Disable NOSNOOP bit for Passthrough.
//
@@ -4336,6 +4340,57 @@ objClLoadPcieVirtualP2PApproval(OBJGPU *pGpu)
gpuGetInstance(pGpu), pGpu->pciePeerClique.id);
}
static void
objClLoadPcieVirtualConfigBits(OBJGPU *pGpu)
{
void *handle;
NvU32 data32;
NvU8 cap;
NvU8 bus = gpuGetBus(pGpu);
NvU8 device = gpuGetDevice(pGpu);
NvU32 domain = gpuGetDomain(pGpu);
NvU32 offset = 0;
NvU32 sig = 0;
if (!IS_PASSTHRU(pGpu))
{
NV_PRINTF(LEVEL_INFO,
"Skipping non-pass-through GPU%u\n", gpuGetInstance(pGpu));
return;
}
handle = osPciInitHandle(domain, bus, device, 0, NULL, NULL);
//
// Walk the list and find enable bits
//
cap = osPciReadByte(handle, PCI_CAPABILITY_LIST);
while ((cap != 0) && (sig != NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE))
{
offset = cap;
data32 = osPciReadDword(handle, offset);
cap = (NvU8)((data32 >> 8) & 0xFF);
if ((data32 & CAP_ID_MASK) != CAP_ID_VENDOR_SPECIFIC)
continue;
sig = DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_0, _SIG_LO, data32);
data32 = osPciReadDword(handle, offset + 4);
sig |= (DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _SIG_HI, data32) << 8);
}
if (sig == NV_PCI_VIRTUAL_CONFIG_BITS_SIGNATURE)
{
// data32 now contains the second dword of the capability structure.
pGpu->virtualConfigBits =
(NvU16) DRF_VAL(_PCI, _VIRTUAL_CONFIG_BITS_CAP_1, _VALUE, data32);
NV_PRINTF(LEVEL_INFO,
"Hypervisor has specified config bits %u for GPU%u\n",
pGpu->virtualConfigBits, gpuGetInstance(pGpu));
}
}
/*!
* @brief : Enable L0s and L1 support for GPU's upstream port
* Refer Section 7.8.7. Link Control Register of PCIE Spec 3.

1
src/nvidia/src/kernel/vgpu/rpc.c
View File

@@ -9559,6 +9559,7 @@ NV_STATUS rpcGspSetSystemInfo_v17_00
rpcInfo->upstreamAddressValid = pGpu->gpuClData.upstreamPort.addr.valid;
rpcInfo->hypervisorType = hypervisorGetHypervisorType(pHypervisor);
rpcInfo->virtualConfigBits = pGpu->virtualConfigBits;
rpcInfo->bIsPassthru = pGpu->bIsPassthru;
// Fill in VF related GPU flags