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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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570.123.07
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@@ -1,5 +1,5 @@
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/*******************************************************************************
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Copyright (c) 2021-2024 NVIDIA Corporation
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Copyright (c) 2021-2025 NVIDIA Corporation
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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@@ -532,7 +532,7 @@ NV_STATUS uvm_conf_computing_fault_decrypt(uvm_parent_gpu_t *parent_gpu,
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{
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NV_STATUS status;
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NvU32 fault_entry_size = parent_gpu->fault_buffer_hal->entry_size(parent_gpu);
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UvmCslContext *csl_context = &parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx;
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UvmCslContext *csl_context = &parent_gpu->fault_buffer.rm_info.replayable.cslCtx;
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// There is no dedicated lock for the CSL context associated with replayable
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// faults. The mutual exclusion required by the RM CSL API is enforced by
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@@ -571,7 +571,7 @@ void uvm_conf_computing_fault_increment_decrypt_iv(uvm_parent_gpu_t *parent_gpu)
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{
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NV_STATUS status;
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NvU32 fault_entry_size = parent_gpu->fault_buffer_hal->entry_size(parent_gpu);
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UvmCslContext *csl_context = &parent_gpu->fault_buffer_info.rm_info.replayable.cslCtx;
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UvmCslContext *csl_context = &parent_gpu->fault_buffer.rm_info.replayable.cslCtx;
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// See comment in uvm_conf_computing_fault_decrypt
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UVM_ASSERT(uvm_sem_is_locked(&parent_gpu->isr.replayable_faults.service_lock));
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