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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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580.94.10
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@@ -347,10 +347,23 @@ uvm_hal_blackwell_access_counter_query_clear_op_gb20x(uvm_parent_gpu_t *parent_g
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return UVM_ACCESS_COUNTER_CLEAR_OP_TARGETED;
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}
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// Host-specific L2 cache invalidate for non-coherent sysmem
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void uvm_hal_blackwell_host_l2_invalidate_noncoh_sysmem(uvm_push_t *push)
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void uvm_hal_blackwell_host_l2_invalidate(uvm_push_t *push, uvm_aperture_t aperture)
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{
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uvm_gpu_t *gpu = uvm_push_get_gpu(push);
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NvU32 aperture_value;
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if (!gpu->parent->is_integrated_gpu) {
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return uvm_hal_ampere_host_l2_invalidate(push, aperture);
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}
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switch (aperture) {
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case UVM_APERTURE_SYS:
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aperture_value = HWCONST(C96F, MEM_OP_D, OPERATION, L2_SYSMEM_NCOH_INVALIDATE);
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break;
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default:
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UVM_ASSERT_MSG(false, "Invalid aperture_type %d\n", aperture);
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return;
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}
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// First sysmembar
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uvm_hal_membar(gpu, push, UVM_MEMBAR_SYS);
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@@ -363,7 +376,7 @@ void uvm_hal_blackwell_host_l2_invalidate_noncoh_sysmem(uvm_push_t *push)
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NV_PUSH_4U(C96F, MEM_OP_A, 0,
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MEM_OP_B, 0,
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MEM_OP_C, 0,
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MEM_OP_D, HWCONST(C96F, MEM_OP_D, OPERATION, L2_SYSMEM_NCOH_INVALIDATE));
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MEM_OP_D, aperture_value);
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// Final sysmembar
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uvm_hal_membar(gpu, push, UVM_MEMBAR_SYS);
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}
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