mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-10 07:39:49 +00:00
570.86.15
This commit is contained in:
Bernhard Stoeckner
@@ -1,19 +1,19 @@
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/*******************************************************************************
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Copyright (c) 1993-2004 NVIDIA Corporation
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Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to
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deal in the Software without restriction, including without limitation the
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rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
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sell copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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Permission is hereby granted, free of charge, to any person obtaining a
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copy of this software and associated documentation files (the "Software"),
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to deal in the Software without restriction, including without limitation
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the rights to use, copy, modify, merge, publish, distribute, sublicense,
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and/or sell copies of the Software, and to permit persons to whom the
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Software is furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be
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included in all copies or substantial portions of the Software.
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The above copyright notice and this permission notice shall be included in
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all copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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@@ -21,8 +21,6 @@
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*******************************************************************************/
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#include "nvtypes.h"
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#ifndef _clc7b5_h_
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@@ -34,69 +32,6 @@ extern "C" {
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#define AMPERE_DMA_COPY_B (0x0000C7B5)
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typedef volatile struct _clc7b5_tag0 {
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NvV32 Reserved00[0x40];
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NvV32 Nop; // 0x00000100 - 0x00000103
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NvV32 Reserved01[0xF];
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NvV32 PmTrigger; // 0x00000140 - 0x00000143
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NvV32 Reserved02[0x36];
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NvV32 SetMonitoredFenceType; // 0x0000021C - 0x0000021F
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NvV32 SetMonitoredFenceSignalAddrBaseUpper; // 0x00000220 - 0x00000223
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NvV32 SetMonitoredFenceSignalAddrBaseLower; // 0x00000224 - 0x00000227
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NvV32 Reserved03[0x6];
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NvV32 SetSemaphoreA; // 0x00000240 - 0x00000243
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NvV32 SetSemaphoreB; // 0x00000244 - 0x00000247
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NvV32 SetSemaphorePayload; // 0x00000248 - 0x0000024B
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NvV32 SetSemaphorePayloadUpper; // 0x0000024C - 0x0000024F
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NvV32 Reserved04[0x1];
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NvV32 SetRenderEnableA; // 0x00000254 - 0x00000257
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NvV32 SetRenderEnableB; // 0x00000258 - 0x0000025B
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NvV32 SetRenderEnableC; // 0x0000025C - 0x0000025F
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NvV32 SetSrcPhysMode; // 0x00000260 - 0x00000263
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NvV32 SetDstPhysMode; // 0x00000264 - 0x00000267
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NvV32 Reserved05[0x6];
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NvV32 SetGlobalCounterUpper; // 0x00000280 - 0x00000283
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NvV32 SetGlobalCounterLower; // 0x00000284 - 0x00000287
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NvV32 SetPageoutStartPAUpper; // 0x00000288 - 0x0000028B
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NvV32 SetPageoutStartPALower; // 0x0000028C - 0x0000028F
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NvV32 Reserved06[0x1C];
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NvV32 LaunchDma; // 0x00000300 - 0x00000303
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NvV32 Reserved07[0x3F];
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NvV32 OffsetInUpper; // 0x00000400 - 0x00000403
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NvV32 OffsetInLower; // 0x00000404 - 0x00000407
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NvV32 OffsetOutUpper; // 0x00000408 - 0x0000040B
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NvV32 OffsetOutLower; // 0x0000040C - 0x0000040F
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NvV32 PitchIn; // 0x00000410 - 0x00000413
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NvV32 PitchOut; // 0x00000414 - 0x00000417
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NvV32 LineLengthIn; // 0x00000418 - 0x0000041B
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NvV32 LineCount; // 0x0000041C - 0x0000041F
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NvV32 Reserved08[0xB8];
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NvV32 SetRemapConstA; // 0x00000700 - 0x00000703
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NvV32 SetRemapConstB; // 0x00000704 - 0x00000707
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NvV32 SetRemapComponents; // 0x00000708 - 0x0000070B
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NvV32 SetDstBlockSize; // 0x0000070C - 0x0000070F
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NvV32 SetDstWidth; // 0x00000710 - 0x00000713
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NvV32 SetDstHeight; // 0x00000714 - 0x00000717
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NvV32 SetDstDepth; // 0x00000718 - 0x0000071B
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NvV32 SetDstLayer; // 0x0000071C - 0x0000071F
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NvV32 SetDstOrigin; // 0x00000720 - 0x00000723
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NvV32 Reserved09[0x1];
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NvV32 SetSrcBlockSize; // 0x00000728 - 0x0000072B
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NvV32 SetSrcWidth; // 0x0000072C - 0x0000072F
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NvV32 SetSrcHeight; // 0x00000730 - 0x00000733
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NvV32 SetSrcDepth; // 0x00000734 - 0x00000737
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NvV32 SetSrcLayer; // 0x00000738 - 0x0000073B
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NvV32 SetSrcOrigin; // 0x0000073C - 0x0000073F
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NvV32 Reserved10[0x1];
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NvV32 SrcOriginX; // 0x00000744 - 0x00000747
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NvV32 SrcOriginY; // 0x00000748 - 0x0000074B
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NvV32 DstOriginX; // 0x0000074C - 0x0000074F
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NvV32 DstOriginY; // 0x00000750 - 0x00000753
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NvV32 Reserved11[0x270];
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NvV32 PmTriggerEnd; // 0x00001114 - 0x00001117
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NvV32 Reserved12[0x3BA];
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} ampere_dma_copy_bControlPio;
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#define NVC7B5_NOP (0x00000100)
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#define NVC7B5_NOP_PARAMETER 31:0
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#define NVC7B5_PM_TRIGGER (0x00000140)
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@@ -146,14 +81,6 @@ typedef volatile struct _clc7b5_tag0 {
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#define NVC7B5_SET_DST_PHYS_MODE_BASIC_KIND 5:2
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#define NVC7B5_SET_DST_PHYS_MODE_PEER_ID 8:6
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#define NVC7B5_SET_DST_PHYS_MODE_FLA 9:9
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#define NVC7B5_SET_GLOBAL_COUNTER_UPPER (0x00000280)
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#define NVC7B5_SET_GLOBAL_COUNTER_UPPER_V 31:0
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#define NVC7B5_SET_GLOBAL_COUNTER_LOWER (0x00000284)
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#define NVC7B5_SET_GLOBAL_COUNTER_LOWER_V 31:0
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#define NVC7B5_SET_PAGEOUT_START_PAUPPER (0x00000288)
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#define NVC7B5_SET_PAGEOUT_START_PAUPPER_V 4:0
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#define NVC7B5_SET_PAGEOUT_START_PALOWER (0x0000028C)
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#define NVC7B5_SET_PAGEOUT_START_PALOWER_V 31:0
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#define NVC7B5_LAUNCH_DMA (0x00000300)
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#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE 1:0
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#define NVC7B5_LAUNCH_DMA_DATA_TRANSFER_TYPE_NONE (0x00000000)
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@@ -223,8 +150,6 @@ typedef volatile struct _clc7b5_tag0 {
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#define NVC7B5_LAUNCH_DMA_VPRMODE 23:22
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#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_NONE (0x00000000)
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#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2VID (0x00000001)
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#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_VID2SYS (0x00000002)
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#define NVC7B5_LAUNCH_DMA_VPRMODE_VPR_SYS2VID (0x00000003)
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#define NVC7B5_LAUNCH_DMA_RESERVED_START_OF_COPY 24:24
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#define NVC7B5_LAUNCH_DMA_DISABLE_PLC 26:26
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#define NVC7B5_LAUNCH_DMA_DISABLE_PLC_FALSE (0x00000000)
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