mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-09 17:50:00 +00:00
570.86.15
This commit is contained in:
@@ -31,6 +31,12 @@
|
||||
void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
|
||||
{
|
||||
NvU32 sem_lo;
|
||||
|
||||
UVM_ASSERT_MSG(uvm_push_get_gpu(push)->parent->host_hal->semaphore_target_is_valid(push, gpu_va),
|
||||
"Semaphore target validation failed in channel %s, GPU %s.\n",
|
||||
push->channel ? push->channel->name : "fake",
|
||||
uvm_gpu_name(uvm_push_get_gpu(push)));
|
||||
|
||||
UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET)));
|
||||
sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET);
|
||||
|
||||
@@ -49,6 +55,12 @@ void uvm_hal_hopper_host_semaphore_release(uvm_push_t *push, NvU64 gpu_va, NvU32
|
||||
void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32 payload)
|
||||
{
|
||||
NvU32 sem_lo;
|
||||
|
||||
UVM_ASSERT_MSG(uvm_push_get_gpu(push)->parent->host_hal->semaphore_target_is_valid(push, gpu_va),
|
||||
"Semaphore target validation failed in channel %s, GPU %s.\n",
|
||||
push->channel ? push->channel->name : "fake",
|
||||
uvm_gpu_name(uvm_push_get_gpu(push)));
|
||||
|
||||
UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET)));
|
||||
sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET);
|
||||
NV_PUSH_5U(C86F, SEM_ADDR_LO, HWVALUE(C86F, SEM_ADDR_LO, OFFSET, sem_lo),
|
||||
@@ -63,6 +75,12 @@ void uvm_hal_hopper_host_semaphore_acquire(uvm_push_t *push, NvU64 gpu_va, NvU32
|
||||
void uvm_hal_hopper_host_semaphore_timestamp(uvm_push_t *push, NvU64 gpu_va)
|
||||
{
|
||||
NvU32 sem_lo;
|
||||
|
||||
UVM_ASSERT_MSG(uvm_push_get_gpu(push)->parent->host_hal->semaphore_target_is_valid(push, gpu_va),
|
||||
"Semaphore target validation failed in channel %s, GPU %s.\n",
|
||||
push->channel ? push->channel->name : "fake",
|
||||
uvm_gpu_name(uvm_push_get_gpu(push)));
|
||||
|
||||
UVM_ASSERT(!(NvOffset_LO32(gpu_va) & ~HWSHIFTMASK(C86F, SEM_ADDR_LO, OFFSET)));
|
||||
sem_lo = READ_HWVALUE(NvOffset_LO32(gpu_va), C86F, SEM_ADDR_LO, OFFSET);
|
||||
|
||||
|
||||
Reference in New Issue
Block a user