mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-03-02 03:39:50 +00:00
570.86.15
This commit is contained in:
Bernhard Stoeckner
@@ -129,6 +129,7 @@ typedef enum
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linkBW_8_10Gbps = 0x1E,
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linkBW_Supported
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} DP_LINK_BANDWIDTH;
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// TODO-@vduraisamy - below enum needs to be moved back to displayport2x.h
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typedef enum
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{
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// enum value unit = 10M
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@@ -140,7 +141,12 @@ typedef enum
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dp2LinkRate_3_24Gbps = 0x0144, // 324
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dp2LinkRate_4_32Gbps = 0x01B0, // 432
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dp2LinkRate_5_40Gbps = 0x021C, // 540
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dp2LinkRate_6_75Gbps = 0x02A3, // 675
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dp2LinkRate_8_10Gbps = 0x032A, // 810
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dp2LinkRate_5_00Gbps = 0x01F4, // 500
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dp2LinkRate_10_0Gbps = 0x03E8, // 1000
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dp2LinkRate_13_5Gbps = 0x0546, // 1350
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dp2LinkRate_20_0Gbps = 0x07D0, // 2000
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dp2LinkRate_Supported
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} DP2X_LINKRATE_10M;
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@@ -159,14 +165,34 @@ typedef enum
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dataRate_8_10Gbps = 810000000
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} DP_LINK_8B_10B_DATA_RATES;
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#define IS_8B_10B_CODING(dataRate) (((NvU64)(val)== dataRate_1_62Gbps) || \
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((NvU64)(val)== dataRate_2_16Gbps) || \
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((NvU64)(val)== dataRate_2_43Gbps) || \
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((NvU64)(val)== dataRate_2_70Gbps) || \
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((NvU64)(val)== dataRate_3_24Gbps) || \
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((NvU64)(val)== dataRate_4_32Gbps) || \
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((NvU64)(val)== dataRate_5_40Gbps) || \
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((NvU64)(val)== dataRate_8_10Gbps))
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#define IS_8B_10B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_1_62Gbps) || \
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((NvU64)(dataRate)== dataRate_2_16Gbps) || \
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((NvU64)(dataRate)== dataRate_2_43Gbps) || \
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((NvU64)(dataRate)== dataRate_2_70Gbps) || \
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((NvU64)(dataRate)== dataRate_3_24Gbps) || \
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((NvU64)(dataRate)== dataRate_4_32Gbps) || \
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((NvU64)(dataRate)== dataRate_5_40Gbps) || \
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((NvU64)(dataRate)== dataRate_8_10Gbps))
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typedef enum
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{
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// Uses 128b/132b channel encoding
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// Link Data Rate = link rate * (128 / 132) / 8
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// = link rate * 4 / 33
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dataRate_UHBR_2_50Gbps = 303030303,
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dataRate_UHBR_2_70Gbps = 327272727,
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dataRate_UHBR_5_00Gbps = 606060606,
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dataRate_UHBR_10_00Gbps = 1212121212,
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dataRate_UHBR_13_50Gbps = 1636363636,
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dataRate_UHBR_20_10Gbps = 2424242424U
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} DP_LINK_128B_132B_DATA_RATES;
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#define IS_128B_132B_CODING(dataRate) (((NvU64)(dataRate)== dataRate_UHBR_2_50Gbps) || \
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((NvU64)(dataRate)== dataRate_UHBR_2_70Gbps) || \
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((NvU64)(dataRate)== dataRate_UHBR_5_00Gbps) || \
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((NvU64)(dataRate)== dataRate_UHBR_10_00Gbps) || \
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((NvU64)(dataRate)== dataRate_UHBR_13_50Gbps) || \
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((NvU64)(dataRate)== dataRate_UHBR_20_10Gbps))
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typedef enum
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{
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@@ -212,9 +238,18 @@ typedef enum
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{
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trainingPattern_Disabled = 0x0,
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trainingPattern_1 = 0x1,
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// trainingPattern_128B132B_TPS1 = 0x1, (use trainingPattern_1 enum as both are same)
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trainingPattern_2 = 0x2,
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trainingPattern_3 = 0x3,
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trainingPattern_4 = 0xB
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trainingPattern_4 = 0xB,
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trainingPattern_128B132B_TPS2 = 0xD,
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trainingPattern_PRBS_9 = 0xE,
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trainingPattern_PRBS_11 = 0xF,
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trainingPattern_PRBS_15 = 0x10,
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trainingPattern_PRBS_23 = 0x11,
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trainingPattern_PRBS_31 = 0x12,
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trainingPattern_SqNum = 0x13,
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trainingPattern_CSTM_264 = 0x14
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} DP_TRAININGPATTERN;
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typedef enum
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@@ -228,8 +263,9 @@ typedef enum
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{
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dpColorFormat_RGB = 0,
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dpColorFormat_YCbCr444 = 0x1,
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dpColorFormat_YCbCr422 = 0x2,
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dpColorFormat_YCbCr422 = 0x2, // this is for simple 422
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dpColorFormat_YCbCr420 = 0x3,
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dpColorFormat_YCbCr422_Native = 0x4,
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dpColorFormat_Unknown = 0xF
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} DP_COLORFORMAT;
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@@ -509,10 +545,87 @@ typedef struct VesaPsrSinkCaps
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} vesaPsrSinkCaps;
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#pragma pack()
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typedef struct
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{
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//
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// If True, then DSC CRC of multiple SU regions supported irrespective
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// of byte counts.
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// If False, then DSC CRC of multiple SU regions supported only when
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// the byte count is multiple of 6.
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//
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NvBool bDscCrcOfMultipleSuSupported;
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//
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// If True, then SU coordinates need to adhere granularity specified in
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// 000B2h, 000B3h, 000B4h.
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// If False, then SU coordinates does not need to adhere any granularity.
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//
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NvBool bSelUpdateGranularityNeeded;
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//
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// If True, then source will use Y granularity specified in 000B5h, 000B6h
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// for PR.
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// If False, sink does not support Y granularity extended cap.
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// Value in 000B4h shall be used for PR.
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//
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NvBool bSuYGranularityExtendedCap;
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//
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// Applicable to PR SU operation. Sets the grid pattern granularity in X axis.
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// If non zero, X coordinate shall be even divisible by 000B2h, 000B3h
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// If zero, no X coordinate granularity requirement exists.
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//
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NvU8 selUpdateXGranularityCap; // This represents 00B2h register
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NvU8 selUpdateXGranularityCap1; // This represents 00B3h register
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//
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// Applicable to PR SU operation. Sets the grid pattern granularity in Y axis.
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// If value is 00h or 01h, No restrictions to SU region Y coordinate.
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// If value is 02h or higher, Y coordinate shall be evenly by divisible by 000B4h
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//
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NvU8 selUpdateYGranularityCap;
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//
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// Applicable to PR SU operation. when image compression is performed locally
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// in sink device, this sets additional granularity in Y axis.
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//
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NvU8 selUpdateYGranularityExtCap;
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NvU8 selUpdateYGranularityExtCap1;
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} SelectiveUpdateCaps;
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typedef struct PanelReplayCaps
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{
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// Indicates if Panel replay is supported or not
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NvBool bPanelReplaySupported;
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// Indicates if selective updates is supported or not
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NvBool bSelUpdateSupported;
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// Indicates if Early region transport is supported or not
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NvBool bEarlyRegionTpSupported;
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// Tells whether sink supports DSC decode functionality in PR.
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NvBool bDscDecodeNotSupportedInPr;
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//
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// If true, it indicates that sink device does not support Asynchronous
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// Video Timing while in a PR Active state. Source device shall keep
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// transmitting Adaptive-Sync SDPs during a PR Active state.
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//
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NvBool bAdaptiveSyncSdpNotSupportedInPr;
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//
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// Applicable to PR function operation using AUX-less ALPM when both
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// an Adaptive-Sync SDP v2 (HB2[4:0] = 02h) and a selective update –or–
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// full frame update occurred during a video frame.
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// 0 = Main-Link shall remain turned ON following the Adaptive-Sync
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// SDP transmission and until after the first selective update region –or–
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// full frame update transmission is complete.
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// 1 = Source device may optionally turn OFF the Main-Link after the
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// Adaptive-Sync SDP transmission and then turn the Main-Link back ON
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// in time for the selective update –or– full frame update.
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//
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NvBool bLinkOffSupportAfterAsSdpSent;
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SelectiveUpdateCaps suCaps;
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} panelReplayCaps;
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typedef struct PanelReplayConfig
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@@ -540,6 +653,62 @@ typedef struct PanelReplayConfig
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// CRC mismatch.
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//
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NvBool bHpdOnRfbActiveFrameCrcError;
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// Configure selective update feature on sink.
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NvBool bEnableSelectiveUpdate;
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// Configure Early region transport on sink.
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NvBool bSuRegionEarlyTpEnable;
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//
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// Applicable only during a PR Active state with AUX-less ALPM enabled.
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// Sink device ignores the setting when while receiving an Adaptive-Sync
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// SDP with HB2[4:0] = 02h and DB0[2] = 0. After receiving an
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// Adaptive-Sync SDP with HB2[4:0] = 02h and DB0[2] = 1, the bit value
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// determines the Sink device’s refresh timing.
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// 0 = Sink device shall use the coasting VTotal value in the last
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// Adaptive-Sync SDP received.
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// 1 = Sink device evice governs the display refresh rate and ignores the
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// coasting VTotal value
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//
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NvBool bSinkRrUnlockGranted;
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//
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// Applicable only to PR SU operation.
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// 0 = Source device shall use the Y granularity value declared by the
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// PANEL REPLAY SELECTIVE UPDATE Y GRANULARITY
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// CAPABILITY register (DPCD 000B4h).
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// 1 = Source device shall use a supported value listed in the
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// SU Y GRANULARITY EXTENDED CAPABILITY register
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// (DPCD 000B5h and 000B6h). The selected value shall be indicated
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// by way of DPCD 001B1h[6:3].
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//
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NvBool bSelUpdateYExtValEnable;
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//
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// Applicable only to the PR function.
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// 0 = Sink device shall capture the SU region, starting with the active
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// video image scan line immediately following the first BE control link
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// symbol sequence after the VSC SDP.
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// 1 = Sink device shall capture the SU region, starting with the active
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// video image scan line immediately following the second BE control link
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// symbol sequence after the VSC SDP.
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//
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NvBool bSuRegionScanLineIndicate;
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//
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// Applicable only to PR SU operation.
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// Used by the Source device to indicate which supported Y granularity
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// extended capability value shall be used. Only a value declared to be
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// supported by DPCD 000B5h and 000B6h may be chosen. Enabled
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// when DPCD 001B1h[2] = 1, and may be used only when the SU Y
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// Granularity Extended Capability Supported bit in the PANEL REPLAY
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// CAPABILITY register is set (DPCD 000B1h[6] = 1).
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//
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NvU8 selUpdateYExtVal : 4;
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//Adaptive-Sync SDP Setup Time Configuration during PR_State.
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NvU8 asSdpSetUpTimePrActive: 2;
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} panelReplayConfig;
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// PR state
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@@ -571,6 +740,68 @@ typedef struct
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PanelReplayState prState;
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} PanelReplayStatus;
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typedef struct
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{
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//
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// 0 = PM_State 2a (FW_STANDBY) is not supported.
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// 1 = PM_State 2a (FW_STANDBY) is supported.
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//
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NvBool bFwStandbySupported;
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//
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// If Sink device reports this as TRUE then it supports AUX-less ALPM.
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// PM_State 3b (ALW_SLEEP) is supported by default.
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//
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NvBool bAuxLessAlpmSupported;
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//
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// Indicates whether the Sink device supports the
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// AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED debug bit in the
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// RECEIVER_ALPM_ARP_STATUS register (DPCD 0200Bh[3]).
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//
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NvBool bAuxLessAlpmPhySleepSupported;
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} AlpmCaps;
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typedef struct
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{
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// Source will use this to configure ALPM on sink side
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NvBool bEnableAlpm;
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//
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// when this field is enabled Sink will trigger HPD to notify source
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// the event of an AUX-less ALPM lock timeout error
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//
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NvBool bHpdOnAlpmLockError;
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// This field needs to be set to True to enable Aux less ALPM
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NvBool bSelectedAlpmMode;
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//
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// This is duration of ACDS phase.
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// The Aux less exit sequence is composed of LFPS, followed by a
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// PHY Establishment period and then the AUX-less ALPM Clock and
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// Data Switch(ACDS) period.
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//
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NvBool bAcdsPeriodDuration;
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} AlpmConfig;
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typedef struct
|
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{
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//
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// Set by the Sink device if it does not achieve LANEx_CR_DONE,
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// LANEx_CHANNEL_EQ_DONE, LANEx_SYMBOL_LOCKED, and
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// INTERLANE_ALIGN_DONE, within the specified time period, after
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// receiving the wake sequence signal (LFPS and Silence)
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//
|
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NvBool bAuxlessAlpmLockTimeout;
|
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|
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//
|
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// Used for debug purposes. Set by the Sink device when
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// two consecutive ML_PHY_SLEEP sequences are detected.
|
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//
|
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NvBool bAuxlessAlpmPhySleepDetected;
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} AlpmStatus;
|
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|
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// Multiplier constant to get link frequency in KHZ
|
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// Maximum link rate of Main Link lanes = Value x 270M.
|
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// To get it to KHz unit, we need to multiply 270K.
|
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@@ -588,6 +819,7 @@ typedef struct
|
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// a * 1000(KHz) / 10 * 1000 * 1000(10Mhz)
|
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//
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#define LINK_RATE_KHZ_TO_10MHZ(a) ((a) / 10000)
|
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#define LINK_RATE_10MHZ_TO_KHZ(a) ((a) * 10000)
|
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#define LINK_RATE_270MHZ_TO_10MHZ(a) ((a) * 27)
|
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#define LINK_RATE_10MHZ_TO_270MHZ(a) ((a) / 27)
|
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|
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@@ -599,7 +831,10 @@ typedef struct
|
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#define DP_LINK_BW_FREQ_MULTI_MBPS 27000000
|
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|
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// Convert link rate in 10M to its value in bps
|
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#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
|
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#define DP_LINK_RATE_10M_TO_BPS(linkRate) (linkRate * 10000000)
|
||||
|
||||
// Convert link rate in 270M to its value in bps
|
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#define DP_LINK_RATE_270M_TO_BPS(linkRate) (linkRate * 270000000)
|
||||
|
||||
// Convert link rate from bps to Bps
|
||||
#define DP_LINK_RATE_BITSPS_TO_BYTESPS(linkRate) (linkRate / 8)
|
||||
|
||||
190
src/common/inc/displayport/displayport2x.h
Normal file
190
src/common/inc/displayport/displayport2x.h
Normal file
@@ -0,0 +1,190 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2023-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _DISPLAYPORT2X_H_
|
||||
#define _DISPLAYPORT2X_H_
|
||||
|
||||
#include "nvmisc.h"
|
||||
#include "dpcd.h"
|
||||
#include "dpcd14.h"
|
||||
#include "dpcd20.h"
|
||||
#include "displayport.h"
|
||||
|
||||
/**************** Resource Manager Defines and Structures ******************\
|
||||
* *
|
||||
* Module: DISPLAYPORT2x.H *
|
||||
* Defines DISPLAYPORT V2.x *
|
||||
* *
|
||||
\***************************************************************************/
|
||||
|
||||
//
|
||||
// 4 Legacy Link Rates: RBR, HBR, HBR2, HBR3
|
||||
// 5 ILRs: 2.16G, 2.43G, 3.24G, 4.32G, 6.75G
|
||||
// 3 UHBRs: 10G, 13.5G, 20G
|
||||
// 2 Internal Test: 2.5G, 5G Do NOT use in any other use cases.
|
||||
//
|
||||
#define NV_SUPPORTED_DP2X_LINK_RATES__SIZE 14
|
||||
//
|
||||
// For 128b/132b link rate to data rate, linkRate * 128/132 * 1/8 * 10M -> ((linkRate * 4 * 1000000) / 33)
|
||||
// For 128b/132b data rate to link rate, dataRate * 132/128 * 8 * 1/10M -> ((dataRate * 33) / (4 * 10000000))
|
||||
// Data rates used here are in Bytes per second.
|
||||
//
|
||||
#define LINK_RATE_TO_DATA_RATE_128B_132B(linkRate) ((linkRate * 4 * 10000000UL) / 33)
|
||||
#define DATA_RATE_128B_132B_TO_LINK_RATE(dataRate) (NV_UNSIGNED_DIV_CEIL((dataRate * 33ULL), (4 * 10000000ULL)))
|
||||
|
||||
// To calculate the effective link rate with channel encoding accounted
|
||||
#define OVERHEAD_128B_132B(linkRate) ((linkRate * 128) / 132)
|
||||
|
||||
//
|
||||
// 128b/132b precise Data Bandwidth Efficiency.
|
||||
// Per Spec 3.5.2.18, effective BW with 128b/132b channel coding is linkRate * 0.9671.
|
||||
// This covers Phy logial layer efficiency 52/1584 and link layer efficiency of 4/65540 as well.
|
||||
// Also add SSC margin of 0.5%.
|
||||
// Additionally add another 0.1% for source to be slightly more conservative for DSC environments
|
||||
// and provide maximum compatibility for LTTPR CDS LT sequence.
|
||||
//
|
||||
// (1 - 52/1584) * (1 - 4/65540) * 0.994 = 0.9612
|
||||
//
|
||||
#define DATA_BW_EFF_128B_132B(linkRate) ((linkRate * 9612) / 10000)
|
||||
|
||||
// For channel equalization, max loop count is 20 when waiting CHANNEL_EQ_DONE set.
|
||||
#define NV_DP2X_MAX_LOOP_COUNT_POLL_CHNL_EQ_DONE (20U)
|
||||
|
||||
typedef enum
|
||||
{
|
||||
linkBW_6_75Gbps = 0x19
|
||||
} DP2X_LINK_BANDWIDTH_270M;
|
||||
|
||||
// The definition here is to match HW register defines for link speed.
|
||||
typedef enum
|
||||
{
|
||||
dp2LinkSpeedId_1_62Gbps = 0x00,
|
||||
dp2LinkSpeedId_2_70Gbps = 0x01,
|
||||
dp2LinkSpeedId_5_40Gbps = 0x02,
|
||||
dp2LinkSpeedId_8_10Gbps = 0x03,
|
||||
dp2LinkSpeedId_2_16Gbps = 0x04,
|
||||
dp2LinkSpeedId_2_43Gbps = 0x05,
|
||||
dp2LinkSpeedId_3_24Gbps = 0x06,
|
||||
dp2LinkSpeedId_4_32Gbps = 0x07,
|
||||
dp2LinkSpeedId_6_75Gbps = 0x08,
|
||||
dp2LinkSpeedId_10_0Gbps = 0x12,
|
||||
dp2LinkSpeedId_13_5Gbps = 0x13,
|
||||
dp2LinkSpeedId_20_0Gbps = 0x14,
|
||||
dp2LinkSpeedId_UHBR_1_62Gbps = 0x1C,
|
||||
dp2LinkSpeedId_UHBR_5_00Gbps = 0x1D,
|
||||
dp2LinkSpeedId_UHBR_2_70Gbps = 0x1E,
|
||||
dp2LinkSpeedId_UHBR_2_50Gbps = 0x1F,
|
||||
dp2LinkSpeedId_Supported
|
||||
} DP2X_LINK_SPEED_INDEX;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
dp2xTxFFEPresetId_0 = 0,
|
||||
dp2xTxFFEPresetId_1 = 1,
|
||||
dp2xTxFFEPresetId_2 = 2,
|
||||
dp2xTxFFEPresetId_3 = 3,
|
||||
dp2xTxFFEPresetId_4 = 4,
|
||||
dp2xTxFFEPresetId_5 = 5,
|
||||
dp2xTxFFEPresetId_6 = 6,
|
||||
dp2xTxFFEPresetId_7 = 7,
|
||||
dp2xTxFFEPresetId_8 = 8,
|
||||
dp2xTxFFEPresetId_9 = 9,
|
||||
dp2xTxFFEPresetId_10 = 10,
|
||||
dp2xTxFFEPresetId_11 = 11,
|
||||
dp2xTxFFEPresetId_12 = 12,
|
||||
dp2xTxFFEPresetId_13 = 13,
|
||||
dp2xTxFFEPresetId_14 = 14,
|
||||
dp2xTxFFEPresetId_15 = 15,
|
||||
dp2xTxFFEPresetId_Supported
|
||||
} DP2X_TXFFE_PRESET_INDEX;
|
||||
|
||||
// Link Training stages for 128b/132b channel coding.
|
||||
typedef enum
|
||||
{
|
||||
DP2X_LT_Set_ResetLink = 0,
|
||||
DP2X_LT_Poll_ResetLink = 1,
|
||||
DP2X_LT_Set_PreLT = 2,
|
||||
DP2X_LT_Set_ChnlEq = 3,
|
||||
DP2X_LT_Poll_ChnlEq_Done = 4,
|
||||
DP2X_LT_Poll_ChnlEq_InterlaneAlign = 5,
|
||||
DP2X_LT_Set_CDS = 6,
|
||||
DP2X_LT_Poll_CDS = 7,
|
||||
DP2X_LT_Set_PostLT = 8,
|
||||
DP2X_LT_StageSupported
|
||||
} DP2X_LT_STAGES;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DP2X_ResetLinkForPreLT,
|
||||
DP2X_ResetLinkForFallback,
|
||||
DP2X_ResetLinkForChannelCoding
|
||||
} DP2X_RESET_LINK_REASON;
|
||||
|
||||
//
|
||||
// Multiplier constant to get link frequency (multiplier of 10MHz) in MBps with 128b/132b channel coding.
|
||||
// a * 10 * 1000 * 1000(10Mhz) * (128 / 132)(128b/132b) / 8(Byte)
|
||||
//
|
||||
#define DP_LINK_BW_FREQ_MULTI_10M_TO_MBPS (10 * 1000 * 1000 * 128 / (132 * 8))
|
||||
|
||||
//
|
||||
// Multiplier constant to get DP2X link frequency in KHZ
|
||||
// Maximum link rate of Main Link lanes = Value x 10M.
|
||||
// To get it to KHz unit, we need to multiply 10K.
|
||||
//
|
||||
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_KHZ (10*1000)
|
||||
|
||||
//
|
||||
// Multiplier constant to get link frequency (multiplier of 270MHz) in MBps
|
||||
// a * 10 * 1000 * 1000(10Mhz) * (8 / 10)(8b/10b) / 8(Byte)
|
||||
// = a * 1000000
|
||||
//
|
||||
#define DP_LINK_BW_FREQUENCY_MULTIPLIER_10MHZ_TO_10HZ (1000*1000)
|
||||
|
||||
#define IS_STANDARD_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_1_62Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_2_70Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_5_40Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_8_10Gbps))
|
||||
|
||||
#define IS_INTERMEDIATE_DP2_X_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_16Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_2_43Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_3_24Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_4_32Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_6_75Gbps))
|
||||
|
||||
#define IS_DP2_X_UHBR_LINKBW(val) (((NvU32)(val)==dp2LinkRate_2_50Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_5_00Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_10_0Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_13_5Gbps) || \
|
||||
((NvU32)(val)==dp2LinkRate_20_0Gbps))
|
||||
|
||||
#define IS_VALID_DP2_X_LINKBW(val) (IS_STANDARD_DP2_X_LINKBW(val) || \
|
||||
IS_INTERMEDIATE_DP2_X_LINKBW(val) || \
|
||||
IS_DP2_X_UHBR_LINKBW(val))
|
||||
|
||||
#define IS_LEGACY_INTERMEDIATE_LINKBW(val) (((NvU32)(val)==linkBW_2_16Gbps) || \
|
||||
((NvU32)(val)==linkBW_2_43Gbps) || \
|
||||
((NvU32)(val)==linkBW_3_24Gbps) || \
|
||||
((NvU32)(val)==linkBW_4_32Gbps) || \
|
||||
((NvU32)(val)==linkBW_6_75Gbps))
|
||||
|
||||
#endif // #ifndef _DISPLAYPORT2X_H_
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -447,6 +447,9 @@ number of Downstream ports will be limited to 32.
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4 /* RWXUF */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NONE (0x00000000) /* RWXUV */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_LESS_THAN_0_5 (0x00000001) /* RWXUV */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE 6:6 /* RWXUF */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_NO (0x00000000) /* RWXUV */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_FIXED_VTOTAL_AS_SDP_EN_IN_PR_ACTIVE_YES (0x00000001) /* RWXUV */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED 7:7 /* RWXUF */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_FALSE (0x00000000) /* RWXUV */
|
||||
#define NV_DPCD_DOWNSPREAD_CTRL_MSA_TIMING_PAR_IGNORED_TRUE (0x00000001) /* RWXUV */
|
||||
@@ -915,16 +918,20 @@ number of Downstream ports will be limited to 32.
|
||||
|
||||
// 00283h - 002BFh: RESERVED. Read all 0s.
|
||||
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS (0x000002C0) /* R-XUR */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED 0:0 /* R-XUF */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_UPDATED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1 /* R-XUF */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_VC_PAYLOAD_ID_SLOT0_5_0 7:2 /* R-XUF */
|
||||
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1 (0x000002C1) /* R-XUR */
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT1_VC_PAYLOAD_ID_SLOT0_6 7:7 /* R-XUF */
|
||||
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT(i) (0x000002C1+(i)) /* R--1A */
|
||||
#define NV_DPCD_VC_PAYLOAD_ID_SLOT__SIZE 63 /* R---S */
|
||||
|
||||
// Source Device-Specific Field, Burst write for 00300h-0030Bh
|
||||
// 6 hex digits: 0x300~0x302.
|
||||
|
||||
@@ -48,6 +48,12 @@
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_SEL_UPDATE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION (0x000001B0) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_PR_MODE 0:0 /* R-XUF */
|
||||
@@ -68,6 +74,12 @@
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR 5:5 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_HPD_RFB_ACTIVE_FRAME_CRC_ERROR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE 6:6 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SELECTIVE_UPDATE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT 7:7 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION_ENABLE_SU_REGION_EARLY_TRANSPORT_YES (0x00000001) /* R-XUV */
|
||||
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_ERROR_STATUS (0x00002020) /* R-XUR */
|
||||
@@ -110,6 +122,321 @@
|
||||
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_DEBUG_LAST_VSC_SDP_CARRYING_PR_INFO_SU_COORDINATE_VALID_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_LINK_BANDWIDTH_SET (0x00000100) /* RWXUR */
|
||||
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL 7:0 /* RWXUF */
|
||||
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_10_0 (0x00000001) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_20_0 (0x00000002) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_BANDWIDTH_SET_VAL_UHBR_13_5 (0x00000004) /* RWXUV */
|
||||
|
||||
// UHBR-128B/132B specific
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN (0x00000102) /* RWXUR */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT 3:0 /* RWXUF */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_NONE (0x00000000) /* RWXUV */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS1 (0x00000001) /* RWXUV */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2 (0x00000002) /* RWXUV */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_SELECT_TPS2_CDS (0x00000003) /* RWXUV */
|
||||
// Bit 7:4 are reserved for 128b/132b. Driver should keep them 0
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED 7:4 /* RWXUF */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_PATTERN_RESERVED_ZERO (0x00000000) /* RWXUV */
|
||||
|
||||
#define NV_DPCD20_TRAINING_LANE_SET(i) (0x00000103+(i)) /* RW-1A */
|
||||
#define NV_DPCD20_TRAINING_LANE_SET__SIZE 4 /* RW--S */
|
||||
#define NV_DPCD20_TRAINING_LANE_SET_TX_FFE_PRESET_VALUE 3:0 /* RWXUF */
|
||||
#define NV_DPCD20_TRAINING_LANE0_SET (0x00000103) /* RWXUR */
|
||||
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET(i) (0x0000010B+(i)) /* RW-1A */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET__SIZE 4 /* RW--S */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS 6:0 /* RWXUF */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS1 (0x00000008) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_128B132B_TPS2 (0x00000010) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS9 (0x00000018) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS11 (0x00000020) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS15 (0x00000028) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS23 (0x00000030) /* RWXUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_PRBS31 (0x00000038) /* R-XUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_264_BIT_CUSTOM (0x00000040) /* R-XUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
|
||||
#define NV_DPCD20_LINK_QUAL_LANE_SET_LQS_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_LINK_SQUARE_PATTERN_NUM_PLUS_1 (0x0000010F) /* RWXUR */
|
||||
|
||||
#define NV_DPCD20_SDP_ERR_DETECTION_CONF (0x00000121) /* RWXUR */
|
||||
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED 0:0 /* RWXUF */
|
||||
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUV */
|
||||
#define NV_DPCD20_SDP_ERR_DETECTION_CONF_CRC16_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUV */
|
||||
|
||||
// Field definition only used only with 128b/132b for DP2.0+
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED (0x00000204) /* R-XUR */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED 4:4 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_SINK_STATUS (0x00000205) /* R-XUR */
|
||||
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_SINK_STATUS_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
|
||||
|
||||
// Field definition only used only with 128b/132b for DP2.0+
|
||||
#define NV_DPCD20_TEST_REQUEST (0x00000218) /* R-XUR */
|
||||
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING 4:4 /* R-XUF */
|
||||
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_8B10B (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_REQUEST_PHY_TEST_CHANNEL_CODING_128B132B (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ 5:5 /* R-XUF */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_PATTERN_REQ_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO 6:6 /* R-XUF */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_REQUEST_TEST_AUDIO_DISABLED_VIDEO_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_TEST_LINK_RATE (0x00000219) /* R-XUR */
|
||||
#define NV_DPCD20_TEST_LINK_RATE_TYPE 7:0 /* R-XUF */
|
||||
#define NV_DPCD20_TEST_LINK_RATE_TYPE_10_0G (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_LINK_RATE_TYPE_20_0G (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G (0x00000004) /* R-XUV */
|
||||
// Bug 4953977: Unigraf UCD323 uses the wrong value to request test link training.
|
||||
// WAR to add off-spec value
|
||||
#define NV_DPCD20_TEST_LINK_RATE_TYPE_13_5G_2 (0x00000003) /* R-XUV */
|
||||
|
||||
// Field definition only used only with 128b/132b for DP2.0+
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN (0x00000248) /* R-XUR */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_DP20 6:0 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS1 (0x00000008) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_128B132B_TPS2 (0x00000010) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS9 (0x00000018) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS11 (0x00000020) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS15 (0x00000028) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS23 (0x00000030) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_PRBS31 (0x00000038) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_264_BIT_CUSTOM (0x00000040) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_ON (0x00000048) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_ON (0x00000049) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_ON_DE_EMPHASIS_OFF (0x0000004A) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_SQUARE_SEQ_WITH_PRESHOOT_OFF_DE_EMPHASIS_OFF (0x0000004B) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_TEST_PATTERN_SEL_LTTPR_CLOCK_SWITCH 7:7 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PHY_SQUARE_PATTERN_NUM_PLUS_1 (0x00000249) /* R-XUR */
|
||||
|
||||
// 0x2230 - 0x2250 = 33 bytes
|
||||
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN(i) (0x00002230+(i)) /* R--1A */
|
||||
#define NV_DPCD20_TEST_264BIT_CUSTOM_PATTERN__SIZE 33 /* R---S */
|
||||
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX (0x00002251) /* R-XUR */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_NOT_SUPPORTED (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CAP_SUPPORTED (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL (0x00002252) /* R-XUR */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_ENABLE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION 2:1 /* R-XUF */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_15 (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_30 (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_60 (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_CONTINUOUS_264BIT_FROM_DPRX_AUX_CTRL_DURATION_120 (0x00000003) /* R-XUV */
|
||||
|
||||
// Field definition for 0x0206/0x0207h (ADJUST_REQUEST_LANEX), only used only with 128b/132b for DP2.0+
|
||||
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEX_TX_FFE_PRESET_VALUE 3:0 /* R-XUF */
|
||||
#define NV_DPCD20_LANEX_XPLUS1_ADJUST_REQ_LANEXPLUS1_TX_FFE_PRESET_VALUE 7:4 /* R-XUF */
|
||||
|
||||
// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled.
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_CDS_INTERLANE_ALIGN_DONE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED 4:4 /* R-XUF */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_LT_FAILED_YES (0x00000001) /* R-XUV */
|
||||
|
||||
// Field definition for 0x0200F (SINK_STATUS_ESI), used only when DP2.0+ 128b/132b is enabled.
|
||||
#define NV_DPCD20_SINK_STATUS_ESI (0x0000200F) /* R-XUR */
|
||||
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_DPRX (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_SINK_STATUS_ESI_INTRA_HOP_AUX_REPLY_LTTPR (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING (0x00002206) /* R-XUR */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_8B_10B_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_EXTENDED_MAIN_LINK_CHANNEL_CODING_ANSI_128B_132B_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES (0x00002215) /* R-XUR */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR10_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR20_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_SUPPORTED_LINK_RATES_UHBR13_5_YES (0x00000001) /* R-XUV */
|
||||
|
||||
//
|
||||
// The interval is (128b/132b_TRAINING_AUX_RD_INTERVAL value + 1) * INTERVAL_UNIT.
|
||||
// The maximum is 256 ms.
|
||||
//
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL (0x00002216) /* R-XUR */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_VAL 6:0 /* R-XUF */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT 7:7 /* R-XUF */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_2MS (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_UNIT_1MS (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_128B_132B_TRAINING_AUX_RD_INTERVAL_MAX_MS 256
|
||||
|
||||
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING (0x000F0006) /* RWXUR */
|
||||
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_NO (0x00000000) /* RWXUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_MAIN_LINK_CHANNEL_CODING_128B_132B_SUPPORTED_YES (0x00000001) /* RWXUF */
|
||||
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES (0x000F0007) /* R-XUR */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_NO (0x00000000) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_10G_SUPPORTED_YES (0x00000001) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_NO (0x00000000) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_20G_SUPPORTED_YES (0x00000001) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_NO (0x00000000) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_128B_132B_RATES_13_5G_SUPPORTED_YES (0x00000001) /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE (0x000F0008) /* R-XUR */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR(i) (i):(i) /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_0_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_1_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_2_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_3_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4 4:4 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_4_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5 5:5 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_5_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6 6:6 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_6_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7 7:7 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_EQ_DONE_LTTPR_7_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS (0x000F0009) /* R-XUR */
|
||||
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_NOT_SUPPORTED (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PHY_REPEATER_ALPM_CAPS_AUX_LESS_SUPPORTED (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT (0x000F000A) /* RWXUR */
|
||||
#define NV_DPCD20_PHY_REPEATER_TOTAL_LTTPR_CNT_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD (0x000000B1) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_DECODE_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_ASYNC_VIDEOTIMING_NOT_SUPPORTED_IN_PR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED 4:4 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_DSC_CRC_MULTIPLE_SUS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED 5:5 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_PR_SEL_UPDATE_GRANULARITY_NEEDED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED 6:6 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_SU_Y_GRANULARITY_EXT_CAP_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP 7:7 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CAPABILITY_ADD_LINK_OFF_SUPPORTED_IN_PR_AFTER_ADAPT_SYNC_SDP_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY (0x000000B2) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1 (0x000000B3) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_X_GRANULARITY_CAPABILITY1_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY (0x000000B4) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_CAPABILITY_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY (0x000000B5) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1 (0x000000B6) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_SU_Y_GRANULARITY_EXTENDED_CAPABILITY1_VAL 7:0 /* R-XUF */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2 (0x000001B1) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SINK_RR_UNLOCK_GRANTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_Y_GRANULARITY_EXTENDED_VALUE_SELECTION 6:3 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION 7:7 /* R-XUF */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION2_SU_REGION_SCANLINE_CAPTURE_INDICATION_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3 (0x0000011A) /* R-XUR */
|
||||
#define NV_DPCD20_PANEL_REPLAY_CONFIGURATION3_AS_SDP_SETUP_CONFIG_PR_ACTIVE_TIME 7:6 /* R-XUF */
|
||||
|
||||
//
|
||||
// Adding DPCD registers for EDP ALPM.
|
||||
//
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES (0x0000002E) /* R-XUR */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_FW_STANDBY_SUPPORT_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_CAP_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CAPABILITIES_AUX_LESS_ALPM_ML_PHY_SLEEP_SUPPORT_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION (0x00000116) /* R-XUR */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ENABLE_ALPM_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_IRQ_HPD_ON_ALPM_LOCK_ERROR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_WAKE_ALPM (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ALPM_SELECTED_MODE_AUX_LESS_ALPM (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_CONFIGURATION_ACDS_PERIOD_DURATION_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS (0x0000200B) /* R-XUR */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_WAKE_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_LOCK_TIMEOUT_ERR_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED 3:3 /* R-XUF */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_RECEIVER_ALPM_STATUS_AUX_LESS_ALPM_ML_PHY_SLEEP_DETECTED_YES (0x00000001) /* R-XUV */
|
||||
|
||||
|
||||
//
|
||||
// Adding DPCD registers for DP Tunneling feature.
|
||||
@@ -179,6 +506,22 @@
|
||||
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_TWO (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_MAX_LANE_COUNT_LANE_FOUR (0x00000004) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_DP_TUNNELING_MAIN_LINK_CHANNEL_CODING (0x000E002B) /* R-XUR */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_DP_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES (0x000E002C) /* R-XUR */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED 0:0 /* R-XUF */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_10_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED 1:1 /* R-XUF */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_20_0_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_DP_TUNNELING_128B132B_LINK_RATES_13_5_GPBS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_DPTX_BW_ALLOCATION_MODE_CONTROL (0x000E0030) /* R-XUR */
|
||||
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ 6:6 /* R-XUF */
|
||||
#define NV_DPCD20_DPTX_UNMASK_BW_ALLOCATION_IRQ_NO (0x00000000) /* R-XUV */
|
||||
@@ -187,4 +530,33 @@
|
||||
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_DPTX_DISPLAY_DRIVER_BW_ALLOCATION_MODE_ENABLE_YES (0x00000001) /* R-XUV */
|
||||
|
||||
// DPCD Registers for Cable ID
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX (0x00000110) /* R-XUR */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE 5:3 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPTX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
|
||||
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX (0x00002217) /* R-XUR */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY 1:0 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_UHBR_NOT_CAPABLE (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_0_GBPS_SUPPORTED (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_UHBR20_10_CAPABILITY_10_AND_20_GBPS_SUPPORTED (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED 2:2 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_NO (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_13_5_GBPS_SUPPORTED_YES (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE 5:3 /* R-XUF */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_CABLE_TYPE_UNKNOWN (0x00000000) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_PASSIVE (0x00000001) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_LRD (0x00000002) /* R-XUV */
|
||||
#define NV_DPCD20_CABLE_ATTRIBUTES_UPDATED_BY_DPRX_CABLE_TYPE_ACTIVE_RETIMER (0x00000003) /* R-XUV */
|
||||
|
||||
#endif // #ifndef _DISPLAYPORT20_H_
|
||||
|
||||
Reference in New Issue
Block a user