mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-23 16:34:00 +00:00
570.86.15
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@@ -4625,11 +4625,11 @@ nvswitch_eng_wr_ls10
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if (nvswitch_is_tnvl_mode_enabled(device))
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{
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nvswitch_tnvl_reg_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
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nvswitch_tnvl_eng_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
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}
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else
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{
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nvswitch_reg_write_32(device, base_addr + offset, data);
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nvswitch_reg_write_32(device, base_addr + offset, data);
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}
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#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
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@@ -4647,6 +4647,33 @@ nvswitch_eng_wr_ls10
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#endif //defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
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}
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void
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nvswitch_reg_write_32_ls10
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(
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nvswitch_device *device,
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NvU32 offset,
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NvU32 data
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)
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{
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if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: register write failed at offset 0x%x\n",
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__FUNCTION__, offset);
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return;
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}
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if (nvswitch_is_tnvl_mode_enabled(device))
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{
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nvswitch_tnvl_reg_wr_32_ls10(device, offset, data);
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}
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else
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{
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// Write the register
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nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
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}
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}
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NvU32
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nvswitch_get_link_eng_inst_ls10
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(
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@@ -5756,7 +5783,8 @@ nvswitch_send_inband_nack_ls10
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msghdr->status = NV_ERR_FABRIC_MANAGER_NOT_PRESENT;
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switch (msghdr->type)
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{
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case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ:
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case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ_V2:
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case NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_REQ:
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msghdr->type = NVLINK_INBAND_MSG_TYPE_MC_TEAM_SETUP_RSP;
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break;
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default:
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