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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-28 10:53:59 +00:00
570.86.15
This commit is contained in:
@@ -666,6 +666,87 @@ nvswitch_soe_issue_ingress_stop_ls10
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Perform register writes in SOE during TNVL
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*
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* @param[in] device
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* @param[in] eng_id
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* @param[in] eng_instance
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* @param[in] reg
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* @param[in] data
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*/
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NvlStatus
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nvswitch_soe_update_intr_report_en_ls10
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(
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nvswitch_device *device,
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RM_SOE_CORE_ENGINE_ID eng_id,
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NvU32 eng_instance,
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RM_SOE_CORE_NPORT_REPORT_EN_REGISTER reg,
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NvU32 data
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)
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{
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FLCN *pFlcn;
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NvU32 cmdSeqDesc = 0;
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NV_STATUS status;
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RM_FLCN_CMD_SOE cmd;
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NVSWITCH_TIMEOUT timeout;
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RM_SOE_CORE_CMD_ERROR_REPORT_EN *pErrorReportEnable;
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NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
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if (!nvswitch_is_soe_supported(device))
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{
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NVSWITCH_PRINT(device, INFO,
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"%s: SOE is not supported\n",
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__FUNCTION__);
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return -NVL_ERR_NOT_SUPPORTED;
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}
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status = device->hal.nvswitch_ctrl_get_bios_info(device, ¶ms);
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if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
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SOE_VBIOS_REVLOCK_REPORT_EN))
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{
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NVSWITCH_PRINT(device, INFO,
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"%s: Unable to update REPORT_EN register and disabiling NVLW interrupt. Update firmware "
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"from .%02x to .%02x\n",
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__FUNCTION__, (NvU32)((params.version & SOE_VBIOS_VERSION_MASK) >> 16),
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SOE_VBIOS_REVLOCK_REPORT_EN);
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return -NVL_ERR_NOT_SUPPORTED;
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}
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pFlcn = device->pSoe->pFlcn;
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nvswitch_os_memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unitId = RM_SOE_UNIT_CORE;
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cmd.hdr.size = RM_SOE_CMD_SIZE(CORE, ERROR_REPORT_EN);
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pErrorReportEnable = &cmd.cmd.core.enableErrorReport;
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pErrorReportEnable->cmdType = RM_SOE_CORE_CMD_UPDATE_INTR_REPORT_EN;
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pErrorReportEnable->engId = RM_SOE_CORE_ENGINE_ID_NPORT;
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pErrorReportEnable->engInstance = eng_instance;
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pErrorReportEnable->reg = reg;
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pErrorReportEnable->data = data;
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nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
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status = flcnQueueCmdPostBlocking(device, pFlcn,
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(PRM_FLCN_CMD)&cmd,
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NULL, // pMsg
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NULL, // pPayload
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SOE_RM_CMDQ_LOG_ID,
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&cmdSeqDesc,
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&timeout);
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if (status != NV_OK)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: Failed to update [0x%x] REPORT_EN register through SOE, status 0x%x\n",
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__FUNCTION__, reg, status);
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return -NVL_ERR_GENERIC;
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}
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Perform register writes in SOE during TNVL
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*
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@@ -697,11 +778,19 @@ nvswitch_soe_reg_wr_32_ls10
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return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
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}
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if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: register write failed at offset 0x%x\n",
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__FUNCTION__, offset);
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return -NVL_IO_ERROR;
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}
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status = device->hal.nvswitch_ctrl_get_bios_info(device, ¶ms);
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if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
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SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE))
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SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS))
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{
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nvswitch_reg_write_32(device, offset, data);
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nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
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return NVL_SUCCESS;
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}
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@@ -736,6 +825,96 @@ nvswitch_soe_reg_wr_32_ls10
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Perform engine writes in SOE during TNVL
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*
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* @param[in] device
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* @param[in] eng_id NVSWITCH_ENGINE_ID*
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* @param[in] eng_bcast NVSWITCH_GET_ENG_DESC_TYPE*
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* @param[in] eng_instance
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* @param[in] base_addr
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* @param[in] offset
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* @param[in] data
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*/
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NvlStatus
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nvswitch_soe_eng_wr_32_ls10
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(
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nvswitch_device *device,
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NVSWITCH_ENGINE_ID eng_id,
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NvU32 eng_bcast,
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NvU32 eng_instance,
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NvU32 base_addr,
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NvU32 offset,
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NvU32 data
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)
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{
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FLCN *pFlcn;
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NvU32 cmdSeqDesc = 0;
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NV_STATUS status;
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RM_FLCN_CMD_SOE cmd;
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NVSWITCH_TIMEOUT timeout;
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RM_SOE_TNVL_CMD_ENGINE_WRITE *pEngineWrite;
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NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
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if (!nvswitch_is_soe_supported(device))
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{
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NVSWITCH_PRINT(device, INFO,
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"%s: SOE is not supported\n",
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__FUNCTION__);
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return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
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}
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if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: register write failed at offset 0x%x\n",
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__FUNCTION__, offset);
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return -NVL_IO_ERROR;
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}
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status = device->hal.nvswitch_ctrl_get_bios_info(device, ¶ms);
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if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
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SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS))
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{
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nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
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return NVL_SUCCESS;
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}
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pFlcn = device->pSoe->pFlcn;
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nvswitch_os_memset(&cmd, 0, sizeof(cmd));
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cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
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cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, ENGINE_WRITE);
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pEngineWrite = &cmd.cmd.tnvl.engineWrite;
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pEngineWrite->cmdType = RM_SOE_TNVL_CMD_ISSUE_ENGINE_WRITE;
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pEngineWrite->eng_id = eng_id;
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pEngineWrite->eng_bcast = eng_bcast;
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pEngineWrite->eng_instance = eng_instance;
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pEngineWrite->base = base_addr;
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pEngineWrite->offset = offset;
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pEngineWrite->data = data;
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nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
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status = flcnQueueCmdPostBlocking(device, pFlcn,
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(PRM_FLCN_CMD)&cmd,
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NULL, // pMsg
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NULL, // pPayload
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SOE_RM_CMDQ_LOG_ID,
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&cmdSeqDesc,
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&timeout);
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if (status != NV_OK)
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{
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NVSWITCH_PRINT(device, ERROR,
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"%s: Failed to send ENGINE_WRITE command to SOE, offset = 0x%x, data = 0x%x\n",
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__FUNCTION__, offset, data);
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return -NVL_ERR_GENERIC;
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}
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return NVL_SUCCESS;
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}
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/*
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* @Brief : Init sequence for SOE FSP RISCV image
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*
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@@ -1009,7 +1188,6 @@ _soeService_LS10
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)
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{
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NvBool bRecheckMsgQ = NV_FALSE;
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NvBool bRecheckPrintQ = NV_FALSE;
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NvU32 clearBits = 0;
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NvU32 intrStatus;
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PFLCN pFlcn = ENG_GET_FLCN(pSoe);
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@@ -1075,8 +1253,6 @@ _soeService_LS10
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NVSWITCH_PRINT(device, INFO,
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"%s: Received a SWGEN1 interrupt\n",
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__FUNCTION__);
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flcnDebugBufferDisplay_HAL(device, pFlcn);
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bRecheckPrintQ = NV_TRUE;
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}
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// Clear any sources that were serviced and get the new status.
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@@ -1112,22 +1288,6 @@ _soeService_LS10
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}
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}
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//
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// If we just processed a SWGEN1 interrupt (Debug Buffer interrupt), peek
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// into the Debug Buffer and see if any text was missed the last time
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// the buffer was displayed (above). If it is not empty, re-generate SWGEN1
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// (since it is now cleared) and exit. As long as an interrupt is pending,
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// this function will be re-entered and the message(s) will be processed.
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//
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if (bRecheckPrintQ)
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{
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if (!flcnDebugBufferIsEmpty_HAL(device, pFlcn))
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{
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flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET,
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DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN1, _SET));
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}
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}
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flcnIntrRetrigger_HAL(device, pFlcn);
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return intrStatus;
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