mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-20 06:53:58 +00:00
570.86.15
This commit is contained in:
Bernhard Stoeckner
@@ -30,7 +30,6 @@
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// Source file: ctrl/ctrl0073/ctrl0073system.finn
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//
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#include "nvlimits.h"
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#include "ctrl/ctrl0073/ctrl0073base.h"
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/* NV04_DISPLAY_COMMON system-level control commands and parameters */
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@@ -1841,165 +1840,6 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS {
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NvHandle hMemory;
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} NV0073_CTRL_CMD_SYSTEM_VRR_SET_RGLINE_ACTIVE_PARAMS;
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/*
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL
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*
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* The VBlank Semaphore Control API ("VBlank Sem Control") allows clients to
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* register for a semaphore release to be performed on the specified memory.
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*
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* One or more clients may register a memory allocation + offset by describing a
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* video memory object with _PARAMS::hMemory and an offset within that memory
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* object (_PARAMS::memoryOffset). Until the hMemory + memoryOffset combination
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* is disabled, during each vblank on the specified heads, RM will interpret the
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* specified memory location as an
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA data structure. Each enabled
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* head will inspect the corresponding
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD at
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA::head[head].
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*
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* _PARAMS::memoryOffset must be a multiple of 8, so that GPU semaphore releases
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* and GSP can write to 8-byte fields within
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD with natural alignment.
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*
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* During vblank, the _CONTROL_DATA_ONE_HEAD::requestCounter field will be read,
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* and the following pseudocode will be performed:
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*
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* swapInterval = DRF_VAL(data->flags)
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* useMinimumGpuTime = DRV_VAL(data->flags)
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*
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* if (data->requestCounter == prevRequestCounter)
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* return
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*
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* if (currentVblankCount < (prevVBlankCount + swapInterval))
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* return
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*
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* if (useMinimumGpuTime && (data->minimumGpuTime < currentGpuTime))
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* return
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*
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* data->vblankCount = currentVblankCount
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* data->releaseGpuTime = currentGpuTime
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* data->semaphore = data->requestCounter
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*
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* prevRequestCounter = data->requestCounter
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* previousVblankCount = currentVblankCount
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*
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* I.e., if the client-described conditions are met, the RM will write
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* _CONTROL_DATA_ONE_HEAD::semaphore to the client-requested 'requestCounter'
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* along with several informational fields (vblankCount, releaseGpuTime).
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*
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* The intent is for clients to use semaphore releases to write:
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*
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* _CONTROL_DATA_ONE_HEAD::minimumGpuTime (if desired)
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* _CONTROL_DATA_ONE_HEAD::swapInterval
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* _CONTROL_DATA_ONE_HEAD::requestCounter
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*
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* and then perform a semaphore acquire on _CONTROL_DATA_ONE_HEAD::semaphore >=
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* requestCounter (using the ACQ_GEQ semaphore operation). This will block any
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* following methods in the client's channel (e.g., a blit) until the requested
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* conditions are met. Note the ::requestCounter should be written last,
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* because the change in value of ::requestCounter is what causes RM, during a
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* vblank callback, to inspect the other fields.
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*
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* Additionally, clients should use the CPU (not semaphore releases in their
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* channel) to write the field _CONTROL_DATA_ONE_HEAD::requestCounterAccel at
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* the same time that they enqueue the semaphore release to write to
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* _CONTROL_DATA_ONE_HEAD::requestCounter. ::requestCounterAccel will be used
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* by resman to "accelerate" the vblank sem control by copying the value from
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* ::requestCounterAccel to ::semaphore. This will be done when the vblank sem
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* control is disabled, and when a client calls
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* NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS. It is important for resman
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* to have access to the value in ::requestCounterAccel, and not just
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* ::requestCounter. The latter is only the last value released so far by the
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* client's channel (further releases to ::requestCounter may still be inflight,
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* perhaps blocked on pending semaphore acquires). The former should be the
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* most recent value enqueued in the channel. This is also why it is important
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* for clients to acquire with ACQ_GEQ (greater-than-or-equal-to), rather than
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* just ACQUIRE.
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*
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* The same hMemory (with difference memoryOffsets) may be used by multiple
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* VBlank Sem Controls.
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*
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* Lastly, the bUseHeadIndexMap field in the enable params is used to tell
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* resman to honor the headIndexMap[] table in the enable params. Normally, the
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* N-th bit in the enable params headMask corresponds to element N in the
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* _CONTROL_DATA::head[] array. But, headIndexMap[] allows the N-th bit in
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* headMask to be remapped to a different index in the head[] array. E.g.,
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*
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA *pData = ...;
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*
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* FOR_EACH_INDEX_IN_MASK(32, head, pParams->headMask)
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* {
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* NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD *pDataOneHead;
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* NvU32 headIndex = pParams->bUseHeadIndexMap ?
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* pParams->headIndexMap[head] : head;
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* pDataOneHead = &pData->head[headIndex];
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* ...
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* }
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* FOR_EACH_INDEX_IN_MASK_END;
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*
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* This remapping is important for nvkms' use of the RMAPI. To support
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* 2head1or, nvkms may remap head indices between the headMask passed to RM and
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* the array indices in _CONTROL_DATA::head[] as used by OpenGL.
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*/
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/* Fields within NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD::flags */
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_USE_MINIMUM_GPU_TIME 16:16
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typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD {
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NvU32 requestCounterAccel;
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NvU32 requestCounter;
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NvU32 flags;
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NV_DECLARE_ALIGNED(NvU64 minimumGpuTime, 8);
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NvU32 semaphore;
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NV_DECLARE_ALIGNED(NvU64 vblankCount, 8);
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NV_DECLARE_ALIGNED(NvU64 releaseGpuTime, 8);
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} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD;
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typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA {
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NV_DECLARE_ALIGNED(NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA_ONE_HEAD head[NV_MAX_HEADS], 8);
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} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DATA;
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE (0x73014eU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS_MESSAGE_ID (0x4EU)
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typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 headMask;
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NvU8 headIndexMap[NV_MAX_HEADS];
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NvHandle hMemory;
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NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
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NvBool bUseHeadIndexMap;
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} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_ENABLE_PARAMS;
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE (0x73014fU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS_MESSAGE_ID (0x4FU)
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typedef struct NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS {
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NvU32 subDeviceInstance;
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NvHandle hMemory;
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NV_DECLARE_ALIGNED(NvU64 memoryOffset, 8);
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} NV0073_CTRL_CMD_SYSTEM_VBLANK_SEM_CONTROL_DISABLE_PARAMS;
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/*
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* Accelerate all VBlank Sem Controls on the specified heads.
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*
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* For all enabled vblank sem controls on the specified heads, immediate set
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* their pending ::semaphore fields to the value in their ::requestCounterAccel
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* field.
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*/
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#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS (0x730150U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS_MESSAGE_ID (0x50U)
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typedef struct NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 headMask;
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} NV0073_CTRL_CMD_SYSTEM_ACCEL_VBLANK_SEM_CONTROLS_PARAMS;
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/*
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* Maps the memory allocated in Kernel RM into Physical RM using the
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* memory descriptor information provided.
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@@ -2037,8 +1877,8 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
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* This parameter specifies the subdevice instance within the
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* NV04_DISPLAY_COMMON parent device to which the operation should be
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* directed.
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* displayId
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* DisplayId of the panel for which we are going to read loadv info
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* head
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* headId of the panel for which we are going to read loadv info
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* Possible status values returned are:
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* counterValue
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* Counts number of frames that have been procesed or synchronized with display
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@@ -2053,7 +1893,7 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_MAP_SHARED_DATA_PARAMS {
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typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 displayId;
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NvU32 head;
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NvU32 counterValue;
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} NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS;
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@@ -2068,6 +1908,9 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_RISCV0CLK 0x0003
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_DISPCLK 0x0004
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_SWITCH_POSTRG_CLKS 0x0005
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_HUBCLK 0x0006
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_DISPCLK 0x0007
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#define NV0073_CTRL_DISP_LPWR_FEATURE_ID_CLK_GATING_POSTRG_CLKS 0x0008
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// Parameter/characteristics of Display ALPM
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_ALPM_INVALID 0x0000
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@@ -2160,6 +2003,34 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_LOADV_COUNTER_INFO_PARAMS {
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_SWITCH_STATUS (0x0010)
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/*!
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* @brief Parameter/characteristics of hubclk, dispclk and Post-RG clock Gating
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*
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* Following are the Parameter/characteristics for of hubclk, dispclk and Post-RG
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* Clock Gating
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_INVALID (0x0000)
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/*!
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* Property specifies if Clock Gating is supported
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* or not. This property is applicable for hubclk, dispclk and Post-RG clk.
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_SUPPORT (0x0001)
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/*!
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* Property specifies if Clock Gating is enabled or not.
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* This property is applicable for hubclk, dispclk and Post-RG clk.
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* (This property allows Get and Set operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_ENABLED (0x0002)
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/*!
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* Property specifies the time(us) for which the specified clock was gated.
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* This property is applicable for hubclk, dispclk and Post-RG clk
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* (This property allows Get operation)
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*/
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#define NV0073_CTRL_DISP_LPWR_PARAMETER_ID_CLK_GATING_GATE_TIME_US (0x0003)
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/*!
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* @brief Structure to identify display low power feature
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*
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@@ -2234,6 +2105,16 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER {
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* Commands returns SUCCESS only when it successfully retrieves value all
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* parameter in the list.
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*
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*
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* subDeviceInstance
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* This parameter specifies the subdevice instance within the
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* NV04_DISPLAY_COMMON parent device to which the operation should be
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* directed.
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*
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* displayId
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* DisplayId of the panel for which we are going to low power features data
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* Possible status values returned are:
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*
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* listSize
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* Number of valid entries in list.
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*
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@@ -2252,6 +2133,7 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER {
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typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 displayId;
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NvU32 listSize;
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NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
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} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS;
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@@ -2285,6 +2167,7 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_GET_PARAMS {
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typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 displayId;
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NvU32 listSize;
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NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER list[NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_LIST_MAX_SIZE];
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} NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS;
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@@ -2310,9 +2193,9 @@ typedef struct NV0073_CTRL_DISP_LPWR_FEATURE_PARAMETER_SET_PARAMS {
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* NV_ERR_INVALID_ARGUMENT
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* NV_ERR_NOT_SUPPORTED
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*/
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#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730158U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR (0x730159U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x58U)
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#define NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS_MESSAGE_ID (0x59U)
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typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
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NvU32 subDeviceInstance;
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@@ -2320,6 +2203,34 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS {
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NvBool bEnableDrr;
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} NV0073_CTRL_CMD_SYSTEM_NOTIFY_DRR_MSCG_WAR_PARAMS;
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/*
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* NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO
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*
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* Fetches the Crash Lock Counter information from corresponding register.
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*
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* subDeviceInstance
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* This parameter specifies the subdevice instance within the
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* NV04_DISPLAY_COMMON parent device to which the operation should be
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* directed.
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* head
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* HeadId of the panel for which we are going to read crash lock counter info
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* Possible status values returned are:
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* counterValueV
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* Counts number of vertical crashlock events that have occured with this display
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* NV_OK
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* NV_ERR_INVALID_PARAM_STRUCT
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* NV_ERR_INVALID_ARGUMENT
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*/
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#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO (0x730160U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID" */
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#define NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS_MESSAGE_ID (0x60U)
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typedef struct NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS {
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NvU32 subDeviceInstance;
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NvU32 head;
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NvU32 counterValueV;
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} NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS;
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/* _ctrl0073system_h_ */
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