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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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10
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080bios.h
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@@ -443,6 +443,13 @@ typedef struct NV2080_CTRL_CMD_BIOS_GET_POST_TIME_PARAMS {
* This value indicates that UEFI is not running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE
* This value indicates that UEFI is running.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT
* This field indicates the EFI running value. Legal values for
* this parameter include:
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE
* This value indicates that display is in vbios mode.
* NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE
* This value indicates that display is in EFI mode.
*
* Possible status values returned are:
* NV_OK
@@ -468,6 +475,9 @@ typedef struct NV2080_CTRL_BIOS_GET_UEFI_SUPPORT_PARAMS {
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING 2:2
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_RUNNING_TRUE (0x00000001)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT 3:3
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_FALSE (0x00000000)
#define NV2080_CTRL_BIOS_UEFI_SUPPORT_FLAGS_IS_EFI_INIT_TRUE (0x00000001)

27
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080dmabuf.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -35,7 +35,7 @@
/*
* NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD
*
* Exports RM vidmem handles to a dma-buf fd.
* Exports RM vidmem and sysmem handles to a dma-buf fd.
*
* The objects in the 'handles' array are exported to the fd as range:
* [index, index + numObjects).
@@ -63,12 +63,25 @@
* This size includes the memory that will be exported in future export calls
* for this dma-buf.
*
* mappingType
* The type of mapping that must be used for this dma-buf.
* See NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_* for all possible values.
*
* With type DEFAULT, the driver shall decide the type based on platform coherency:
* C2C for coherent
* PCIe BAR1 for non-coherent
* Type FORCE_PCIE field is a workaround for platforms with Grace (PCIe Gen4/Gen5 RPs) paired with
* Gen6 parts like Blackwell GPUs and CX8 NICs, requiring a separate Gen6 PCIe link to maximize RDMA
* bandwidth. This type allows dma-buf to be mapped over this Gen6 PCIe link.
*
* This call shall return NV_ERR_NOT_SUPPORTED if FORCE_PCIE type is used on non-Grace platforms.
*
* handles
* An array of {handle, offset, size} that describes the dma-buf.
* The offsets and sizes must be OS page-size aligned.
*
* Limitations:
* 1. This call only supports vidmem objects for now.
* 1. This call supports vidmem and sysmem objects.
* 2. All memory handles should belong to the same GPU or the same GPU MIG instance.
*
* Possible status values returned are:
@@ -81,9 +94,12 @@
* NV_ERR_INVALID_OBJECT
* NV_ERR_INVALID_OBJECT_PARENT
*/
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_DMABUF_EXPORT_OBJECTS_TO_FD (0x20803a01) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_DMABUF_INTERFACE_ID << 8) | NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
#define NV2080_CTRL_DMABUF_MAX_HANDLES 128
#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT (0x00000000U)
#define NV2080_CTRL_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE (0x00000001U)
typedef struct NV2080_CTRL_DMABUF_MEM_HANDLE_INFO {
NvHandle hMemory;
@@ -99,6 +115,7 @@ typedef struct NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS {
NvU32 numObjects;
NvU32 index;
NV_DECLARE_ALIGNED(NvU64 totalSize, 8);
NvU8 mappingType;
NV_DECLARE_ALIGNED(NV2080_CTRL_DMABUF_MEM_HANDLE_INFO handles[NV2080_CTRL_DMABUF_MAX_HANDLES], 8);
} NV2080_CTRL_DMABUF_EXPORT_MEM_PARAMS;

166
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
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@@ -389,6 +389,8 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_RAM_TYPE_LPDDR5 (0x00000013U) /* LPDDR (Low Power SDDR) used on T23x and later.*/
#define NV2080_CTRL_FB_INFO_RAM_TYPE_HBM3 (0x00000014U) /* HBM3 (High Bandwidth Memory) v3 */
#define NV2080_CTRL_FB_INFO_RAM_TYPE_GDDR7 (0x00000015U) /* GDDR7 */
/* valid RAM LOCATION types */
@@ -2669,6 +2671,9 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
* @params [OUT] NvBool bStaticBar1Enabled:
* This field indicates the static BAR1 mode is enabled. All the following fields are valid
* only if static BAR1 mode is enabled.
* @params [OUT] NvU64 staticBar1StartOffset:
* Static BAR1 may start at nonzero BAR1 address.
* This field indicates the start offset of the static BAR1.
* @params [OUT] NvU64 staticBar1Size:
* This field indicates the size of the static BAR1.
*
@@ -2684,7 +2689,168 @@ typedef struct NV2080_CTRL_CMD_FB_STATS_GET_PARAMS {
typedef struct NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS {
NvBool bStaticBar1Enabled;
NV_DECLARE_ALIGNED(NvU64 staticBar1StartOffset, 8);
NV_DECLARE_ALIGNED(NvU64 staticBar1Size, 8);
} NV2080_CTRL_FB_GET_STATIC_BAR1_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION
*
* This command returns the current DRAM encryption configuration
* setting for a GPU given its subdevice handle. The value returned
* is the current DRAM encryption setting for the GPU stored in non-volatile
* memory on the board.
*
* currentConfiguration
* The current DRAM encryption configuration setting.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION (0x20801355U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_DISABLED (0x00000000U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS_MESSAGE_ID (0x55U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS {
NvU32 currentConfiguration;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_PENDING_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION
*
* This command changes the DRAM encryption configuration setting for
* a GPU given its subdevice handle. The value specified is stored
* in non-volatile memory on the board and will take effect with the
* next GPU reset.
*
* newConfiguration
* The new configuration setting to take effect with
* the next GPU reset.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_SET_DRAM_ENCRYPTION_CONFIGURATION (0x20801356U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_DISABLE (0x00000000U)
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_ENABLE (0x00000001U)
#define NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS {
NvU32 newConfiguration;
} NV2080_CTRL_FB_SET_DRAM_ENCRYPTION_CONFIGURATION_PARAMS;
/*
* NV2080_CTRL_CMD_FB_GET_STATUS
*
* This control command is used by clients to get the FB availabilty status,
* i.e whether the GPU Memory is ready for use or not for MIG and non-MIG cases
*
* fbStatus[OUT]
* This parameter returns the various values of FB availability status.
* Valid values include:
* NV2080_CTRL_FB_STATUS_FAILED
* On Non Self hosted (Non NUMA) systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - this status indicates that either
* the memory onlining has failed or fabric probe response has failed.
* GPU reset maybe required in such a case.
* NV2080_CTRL_FB_STATUS_READY
* On Non Self hosted systems - this status is always returned as memory is ready
* after GPU initialization is complete.
* On Self hosted systems - this status indicates that the FB memory has been onlined
* successfully and is available for client/user allocations.
* NV2080_CTRL_FB_STATUS_PENDING
* On Non Self hosted systems - this status is not expected
* On Direct connected Self hosted systems - this status is not expected since
* FB memory is available as part of GPU initialization itself.
* On Nvswitch connected Self hosted systems - This status indicates memory is yet to
* be onlined or is in progress since we are either still waiting for a fabric
* probe response or a fabric probe request hasn't been sent yet.
* NV2080_CTRL_FB_STATUS_NOT_APPLICABLE
* This status indicates that this is a system with no FB memory.
*
*
* @returns Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_STATE
* NV_ERR_NOT_SUPPORTED
* NV_ERR_NOT_READY
* NV_ERR_INVALID_LOCK_STATE
*/
#define NV2080_CTRL_CMD_FB_GET_STATUS (0x20801357U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID" */
// NUMA Memory Onlining Status
#define NV2080_CTRL_FB_STATUS_FAILED (0x00000000U)
#define NV2080_CTRL_FB_STATUS_READY (0x00000001U)
#define NV2080_CTRL_FB_STATUS_PENDING (0x00000002U)
#define NV2080_CTRL_FB_STATUS_NOT_APPLICABLE (0x00000003U)
#define NV2080_CTRL_FB_GET_STATUS_PARAMS_MESSAGE_ID (0x57U)
typedef struct NV2080_CTRL_FB_GET_STATUS_PARAMS {
NvU32 fbStatus;
} NV2080_CTRL_FB_GET_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT
*
* This command returns whether or not DRAM encryption config object is supported via the InfoROM.
*
* isSupported [OUT]
* This parameter returns whether the DRAM Encryption inforom object is present in the inforom.
* The various values of isSupported is:
* 1. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED
* 2. NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT (0x20801358U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_INFOROM_SUPPORT_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS_MESSAGE_ID (0x58U)
typedef struct NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS {
NvU32 isSupported;
} NV2080_CTRL_FB_DRAM_ENCRYPTION_INFOROM_SUPPORT_PARAMS;
/*
* NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS
*
* This command returns the current DRAM encryption status.
*
* currentStatus
* The current DRAM encryption status.
*
* Possible status return values are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
* NV_ERR_INVALID_STATE
*/
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS (0x20801359U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FB_INTERFACE_ID << 8) | NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_DISABLED (0x00000000U)
#define NV2080_CTRL_CMD_FB_QUERY_DRAM_ENCRYPTION_STATUS_ENABLED (0x00000001U)
#define NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS_MESSAGE_ID (0x59U)
typedef struct NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS {
NvU32 currentStatus;
} NV2080_CTRL_FB_QUERY_DRAM_ENCRYPTION_STATUS_PARAMS;
/* _ctrl2080fb_h_ */

81
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fifo.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2006-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -212,6 +212,10 @@ typedef struct NV2080_CTRL_FIFO_GET_PHYSICAL_CHANNEL_COUNT_PARAMS {
* This index can be used to get max channel groups supported per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE
* This index can be used too get channel groups currently in use per engine/runlist.
* NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
* This index can be used to query the maximum "lower" subcontext index
* allocated under NV_CTXSHARE_ALLOCATION_FLAGS_SUBCONTEXT_ASYNC_PREFER_LOWER.
* Note: Includes subcontext ID 0, which will be allocated last in ASYNC allocation mode.
*
*/
typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
@@ -227,10 +231,11 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FIFO_INFO;
#define NV2080_CTRL_FIFO_INFO_INDEX_IS_PER_RUNLIST_CHANNEL_RAM_SUPPORTED (0x000000007)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_CHANNEL_GROUPS_PER_ENGINE (0x000000008)
#define NV2080_CTRL_FIFO_INFO_INDEX_CHANNEL_GROUPS_IN_USE_PER_ENGINE (0x000000009)
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT (0x00000000a)
/* set INDEX_MAX to greatest possible index value */
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_DEFAULT_CHANNEL_TIMESLICE
#define NV2080_CTRL_FIFO_INFO_INDEX_MAX NV2080_CTRL_FIFO_INFO_INDEX_MAX_LOWER_SUBCONTEXT
#define NV2080_CTRL_FIFO_GET_INFO_USERD_OFFSET_SHIFT (12)
@@ -989,7 +994,7 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_STATE_PARAMS {
* This field sets the runlist scheduling policy. It specifies the
* NV2080_CTRL_CMD_VGPU_SCHEDULER_POLICY_* scheduling policy.
*
* enableArr
* enableArr
* This field sets the Adaptive round robin scheduler
* is enabled/disabled.
*
@@ -1085,4 +1090,74 @@ typedef struct NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS {
NvU32 minAvgFactorForARR;
} NV2080_CTRL_FIFO_OBJSCHED_GET_CAPS_PARAMS;
// Max channels per group is limited by NV_RAMRL_ENTRY_TSG_LENGTH_MAX for the arch.
#define NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG 128
/*
* NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO
* hClient
* Input parameter
* This parameter specifies the client handle associated input channel/TSG
* hChannelOrTsg
* Input parameter.
* This parameter specifies the handle of input channel handle (or channel
* group)
* tsgId
* Output parameter.
* This field return the Unique of TSG object if user specified a channel group handle
* with hChannelOrTsg.
* numChannels
* Output parameter.
* This field return the number of channels under TSG if user specify a
* channel group handle or return 1 if user specify a channel handle.
* channelUniqueID
* Output parameter.
* This array field returns unique Channel ID for each channel.
* vasUniqueID
* Output parameter.
* This array field returns unique IDs of VA Space objects of channels under TSG or channel.
* veid
* Output parameter.
* This array field returns VEID for channels under TSG or channel.
*/
#define NV2080_CTRL_CMD_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO (0x20801123) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS_MESSAGE_ID (0x23U)
typedef struct NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS {
NvHandle hClient;
NvHandle hChannelOrTsg;
NvU32 tsgId;
NvU32 numChannels;
NvU32 channelUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 vasUniqueID[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 veid[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
} NV2080_CTRL_FIFO_GET_CHANNEL_GROUP_UNIQUE_ID_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID
* This command is used query the CID (channel ID) in batch
* hClients
* Input parameter
* Array of Client handles
* hChannels
* Input parameter
* Array of Channel handles
* numChannels
* Indicates the number of input client, channel handle pairs.
* channelUniqueIDs
* Output parameter.
* This parameter returns an array of unique Channel IDs for each input pair.
* channel handles.
*/
#define NV2080_CTRL_CMD_FIFO_QUERY_CHANNEL_UNIQUE_ID (0x20801124) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_FIFO_INTERFACE_ID << 8) | NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS {
NvHandle hClients[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvHandle hChannels[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
NvU32 numChannels;
NvU32 channelUniqueIDs[NV2080_CTRL_CMD_FIFO_MAX_CHANNELS_PER_TSG];
} NV2080_CTRL_FIFO_QUERY_CHANNEL_UNIQUE_ID_PARAMS;
/* _ctrl2080fifo_h_ */

209
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -42,7 +42,7 @@
#define NV_GRID_LICENSE_FEATURE_VAPPS_EDITION "GRID-Virtual-Apps,3.0"
#define NV_GRID_LICENSE_FEATURE_VIRTUAL_WORKSTATION_EDITION "Quadro-Virtual-DWS,5.0;GRID-Virtual-WS,2.0;GRID-Virtual-WS-Ext,2.0"
#define NV_GRID_LICENSE_FEATURE_GAMING_EDITION "GRID-vGaming,8.0"
#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0;Quadro-Virtual-DWS,5.0"
#define NV_GRID_LICENSE_FEATURE_COMPUTE_EDITION "NVIDIA-vComputeServer,9.0"
#define NV_GRID_LICENSED_PRODUCT_VWS "NVIDIA RTX Virtual Workstation"
#define NV_GRID_LICENSED_PRODUCT_GAMING "NVIDIA Cloud Gaming"
@@ -81,7 +81,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE (0x00000025U)
#define NV2080_CTRL_GPU_INFO_INDEX_IBMNPU_RELAXED_ORDERING (0x00000026U)
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED (0x00000027U)
#define NV2080_CTRL_GPU_INFO_INDEX_NVSWITCH_PROXY_DETECTED (0x00000028U)
#define NV2080_CTRL_GPU_INFO_INDEX_GPU_SR_SUPPORT (0x00000029U)
@@ -139,11 +138,6 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_GPU_INFO;
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_SURPRISE_REMOVAL_POSSIBLE_YES (0x00000001U)
/* valid relaxed ordering values */
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_DISABLED (0x00000000U)
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_ENABLED (0x00000001U)
#define NV2080_CTRL_GPU_INFO_IBMNPU_RELAXED_ORDERING_UNSUPPORTED (0xFFFFFFFFU)
/* valid poison fuse capability values */
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_NO (0x00000000U)
#define NV2080_CTRL_GPU_INFO_INDEX_GLOBAL_POISON_FUSE_ENABLED_YES (0x00000001U)
@@ -2523,6 +2517,26 @@ typedef struct NV2080_CTRL_GPU_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_GPU_PARTITION_SPAN;
/*
* NV2080_CTRL_EXEC_PARTITION_SPAN
*
* This struct represents the span of a compute partition, which represents the
* slices a given partition occupies (or may occupy) within a fixed range which
* is defined memory partition. A partition containing more resources will cover
* more GPU instance slices and therefore cover a larger span.
*
* lo
* - The starting unit of this span, inclusive
*
* hi
* - The ending unit of this span, inclusive
*
*/
typedef struct NV2080_CTRL_EXEC_PARTITION_SPAN {
NV_DECLARE_ALIGNED(NvU64 lo, 8);
NV_DECLARE_ALIGNED(NvU64 hi, 8);
} NV2080_CTRL_EXEC_PARTITION_SPAN;
#define NV_GI_UUID_LEN 16U
/*
@@ -2607,6 +2621,18 @@ typedef struct NV2080_CTRL_GPU_SET_PARTITION_INFO {
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE_RESERVED_INTERNAL_07 0x00000007U
#define NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE 7:5
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_FULL 0x00000001U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_HALF 0x00000002U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_MINI_HALF 0x00000003U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_QUARTER 0x00000004U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_EIGHTH 0x00000005U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_06 0x00000006U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_RESERVED_INTERNAL_07 0x00000007U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE 0x00000000U
#define NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE__SIZE 8U
#define NV2080_CTRL_GPU_PARTITION_MAX_TYPES 40U
#define NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA 30:30
@@ -2896,10 +2922,13 @@ typedef NV2080_CTRL_GPU_EXEC_REG_OPS_PARAMS NV2080_CTRL_GPU_EXEC_REG_OPS_VGPU_PA
typedef struct NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS {
NvU32 engineList[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
NvU32 runlistPriBase[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
NvU32 runlistId[NV2080_GPU_MAX_ENGINES_LIST_SIZE];
} NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_PARAMS;
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_NULL (0xFFFFFFFFU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_PRI_BASE_ERROR (0xFFFFFFFBU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_GPU_GET_ENGINE_RUNLIST_ERROR (0xFFFFFFFBU)
/*
* NV2080_CTRL_CMD_GPU_GET_HW_ENGINE_ID
@@ -3055,6 +3084,26 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
#define NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO (0x2080017cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX
*
* This command returns the first async ce index
*
* CE Index
* Output parameter.
* Returns the first async ce index
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID (0xe6U)
typedef struct NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS {
NvU32 firstAsyncCEIdx;
} NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS;
#define NV2080_CTRL_CMD_GPU_GET_FIRST_ASYNC_CE_IDX (0x208001e6U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIRST_ASYNC_CE_IDX_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE
@@ -3069,7 +3118,7 @@ typedef struct NV2080_CTRL_GPU_GET_NVFBC_SW_SESSION_INFO_PARAMS {
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GPU_GET_VMMU_SEGMENT_SIZE (0x2080017eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_VMMU_SEGMENT_SIZE_PARAMS_MESSAGE_ID (0x7EU)
@@ -4029,6 +4078,10 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
*
* This structure specifies resources in an execution partition
*
* partitionFlag[IN]
* - GPU instance profile flags for which to query compute profiles
* Ignored, if subdevice is subscribed to a GPU instance
*
* profileCount[OUT]
* - Total Number of profiles filled
*
@@ -4038,6 +4091,7 @@ typedef struct NV2080_CTRL_GPU_COMPUTE_PROFILE {
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS_MESSAGE_ID (0xA2U)
typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
NvU32 partitionFlag;
NvU32 profileCount;
NV2080_CTRL_GPU_COMPUTE_PROFILE profiles[NV2080_CTRL_GPU_PARTITION_FLAG_COMPUTE_SIZE__SIZE];
} NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS;
@@ -4057,10 +4111,25 @@ typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILES_PARAMS {
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW 1:0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_DEGRADED_BW_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE 3:2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ROUTE_UPDATE_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY 5:4
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_CONNECTION_UNHEALTHY_FALSE 2
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY 7:6
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_NOT_SUPPORTED 0
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_TRUE 1
#define NV2080_CTRL_GPU_FABRIC_HEALTH_MASK_ACCESS_TIMEOUT_RECOVERY_FALSE 2
/*!
* NV2080_CTRL_CMD_GET_GPU_FABRIC_PROBE_INFO_PARAMS
@@ -4376,6 +4445,7 @@ typedef enum NV2080_CTRL_GPU_RECOVERY_ACTION {
NV2080_CTRL_GPU_RECOVERY_ACTION_GPU_RESET = 1,
NV2080_CTRL_GPU_RECOVERY_ACTION_NODE_REBOOT = 2,
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_P2P = 3,
NV2080_CTRL_GPU_RECOVERY_ACTION_DRAIN_AND_RESET = 4,
} NV2080_CTRL_GPU_RECOVERY_ACTION;
#define NV2080_CTRL_GPU_GET_RECOVERY_ACTION_PARAMS_MESSAGE_ID (0xB2U)
@@ -4400,5 +4470,120 @@ typedef struct NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS {
} NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS;
#define NV2080_CTRL_GPU_GET_FIPS_STATUS (0x208001e4) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_FIPS_STATUS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_GPU_GET_RAFTS_FS_MASK
*
* @brief Get floorsweeping mask for given skyline configuration.
*
* tpcCountMatrix [IN]
* TPC per GPC distribution for which user require floorsweeping mask.
*
* gfxGpcCount [IN]
* Number of GFX capable GPC required.
*
* gfxTpcCount [IN]
* Number of GFX capable TPC required.
*
* floorSweepConfig [OUT]
* MODS floorsweeping mask.
*
* bValid [OUT]
* If entries in floorSweepConfig are valid or not.
*
* @return NV_OK : on success
* @return NV_ERR_INVALID_PARAMETER : Parameters in pParams are incompatible with each other
* @return NV_ERR_NOT_SUPPORTED : Requested skyline not supported by current chip but can be supported by a chip
* with fewer defects
*/
typedef enum NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE {
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_INVALID = 0,
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_TPC = 1,
NV2080_RAFTS_FLOORSWEEP_UNIT_TYPE_GPC = 2,
} NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE;
typedef struct NV2080_RAFTS_FLOORSWEEP_INFO {
NV2080_RAFTS_FLOORSWEEP_UNIT_MASK_TYPE unitType;
NvU32 parentId;
NvU32 mask;
} NV2080_RAFTS_FLOORSWEEP_INFO;
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU 0x2
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU 0xC
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC (0x18) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU * NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU" */
#define NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT (0x1a) /* finn: Evaluated from "NV2080_CTRL_GPU_RAFTS_NUM_MAX_NUM_GPC + 2" */
#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID (0xB3U)
typedef struct NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS {
NvU8 tpcCountMatrix[NV2080_CTRL_GPU_RAFTS_NUM_MAX_UGPU][NV2080_CTRL_GPU_RAFTS_NUM_MAX_GPC_PER_UGPU];
NvBool bValid;
NV2080_RAFTS_FLOORSWEEP_INFO floorSweepConfig[NV2080_CTRL_GPU_RAFTS_NUM_MAX_FS_UNIT];
NvU8 gfxGpcCount;
NvU8 gfxTpcPerGpcCount;
NvU8 maxUgpuTpcDiff;
} NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS;
#define NV2080_CTRL_GPU_GET_RAFTS_FS_MASK (0x208001b3) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_RAFTS_FS_MASK_PARAMS_MESSAGE_ID" */
/*!
* NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS
*
* This structure specifies resources in an execution partition
*
* partitionFlag[IN]
* - If GPU instance profile flag for which to query specified
* compute profile
*
* computeSize[IN]
* - Size specifying compute profile whose info to query
*
* totalProfileCount[OUT]
* - Total Number of profiles possible to create in instance of specified GPU
* profile
*
* totalSpans[OUT]
* - List of spans which can possibly be occupied by partitions of the
* given type.
*
* totalSpansCount[OUT]
* - Number of entries filled in totalSpans
*
*/
#define NV2080_CTRL_CMD_GPU_GET_COMPUTE_PROFILE_CAPACITY (0x208001e5U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS_MESSAGE_ID (0xe5U)
typedef struct NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS {
NvU32 partitionFlag;
NvU32 computeSize;
NvU32 totalProfileCount;
NV_DECLARE_ALIGNED(NV2080_CTRL_EXEC_PARTITION_SPAN totalSpans[NV2080_CTRL_GPU_MAX_PARTITIONS], 8);
NvU32 totalSpansCount;
} NV2080_CTRL_GPU_GET_COMPUTE_PROFILE_CAPACITY_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK
*
* This command returns the TPC reconfig mask for a specific GPC
*
* gpc[IN]
* The GPC for which the TPC reconfig mask needs to be queried.
* The GPC should be specified as a logical index.
*
* tpcReconfigMask[OUT]
* Mask of reconfigurable TPCs in the specified GPC
*
* Possible status values returned are:
* NV_OK
* NV_ERR_NOT_SUPPORTED
*/
#define NV2080_CTRL_CMD_GPU_GET_TPC_RECONFIG_MASK (0x208001e7U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GPU_INTERFACE_ID << 8) | NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0xe7U)
typedef struct NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 gpc;
NvU32 tpcReconfigMask;
} NV2080_CTRL_GPU_GET_TPC_RECONFIG_MASK_PARAMS;
/* _ctrl2080gpu_h_ */

285
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gr.h
View File

@@ -157,23 +157,23 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* Valid GR info index values
* These indices are offset from supporting the 0080 version of this call
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
#define NV2080_CTRL_GR_INFO_INDEX_MAXCLIPS NV0080_CTRL_GR_INFO_INDEX_MAXCLIPS
#define NV2080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894 NV0080_CTRL_GR_INFO_INDEX_MIN_ATTRS_BUG_261894
#define NV2080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK NV0080_CTRL_GR_INFO_XBUF_MAX_PSETS_PER_BANK
/**
* This index is used to request the surface buffer alignment (in bytes)
* required by the associated subdevice. The return value is GPU
* implementation-dependent.
*/
#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
#define NV2080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_BUFFER_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT NV0080_CTRL_GR_INFO_INDEX_SWIZZLE_ALIGNMENT
#define NV2080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE NV0080_CTRL_GR_INFO_INDEX_VERTEX_CACHE_SIZE
/**
* This index is used to request the number of VPE units supported by the
* associated subdevice. The return value is GPU implementation-dependent.
* A return value of 0 indicates the GPU does not contain VPE units.
*/
#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_VPE_COUNT NV0080_CTRL_GR_INFO_INDEX_VPE_COUNT
/**
* This index is used to request the number of shader pipes supported by
* the associated subdevice. The return value is GPU
@@ -181,13 +181,13 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* not contain dedicated shader units.
* For tesla: this value is the number of enabled TPCs
*/
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_COUNT
/**
* This index is used to request the scaling factor for thread stack
* memory.
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
#define NV2080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR NV0080_CTRL_GR_INFO_INDEX_THREAD_STACK_SCALING_FACTOR
/**
* This index is used to request the number of sub units per
* shader pipes supported by the associated subdevice. The return
@@ -195,157 +195,167 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* the GPU does not contain dedicated shader units.
* For tesla: this value is the number of enabled SMs (per TPC)
*/
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT NV0080_CTRL_GR_INFO_INDEX_SHADER_PIPE_SUB_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT NV0080_CTRL_GR_INFO_INDEX_SM_REG_BANK_REG_COUNT
/**
* This index is used to determine the SM version.
* A value of 0 indicates the GPU does not support this function.
* Otherwise one of NV2080_CTRL_GR_INFO_SM_VERSION_*.
*/
#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
#define NV2080_CTRL_GR_INFO_INDEX_SM_VERSION NV0080_CTRL_GR_INFO_INDEX_SM_VERSION
/**
* This index is used to determine the maximum number of warps
* (thread groups) per SM.
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_WARPS_PER_SM
/**
* This index is used to determine the maximum number of threads
* in each warp (thread group).
* A value of 0 indicates the GPU does not support this function.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP NV0080_CTRL_GR_INFO_INDEX_MAX_THREADS_PER_WARP
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_GS_OBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES NV0080_CTRL_GR_INFO_INDEX_GEOM_XBUF_ENTRIES
#define NV2080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_FB_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY NV0080_CTRL_GR_INFO_INDEX_HOST_MEMORY_REQUEST_GRANULARITY
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM NV0080_CTRL_GR_INFO_INDEX_MAX_SP_PER_SM
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ZCULL_BANKS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MIN_FBPS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_FBP_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED NV0080_CTRL_GR_INFO_INDEX_TIMESLICE_ENABLED
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPAS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_PES_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_GPU_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_TPCS_PER_PES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_MXBAR_HUB_PORTS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SM_PER_TPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_HSHUB_FBP_PORTS
/**
* This index is used to return the number of "Ray Tracing Cores"
* supported by the graphics pipeline
*/
#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_RT_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT NV0080_CTRL_GR_INFO_INDEX_TENSOR_CORE_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GRS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_SLICES
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCMMU_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_LTC_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_ROP_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC NV0080_CTRL_GR_INFO_INDEX_FAMILY_MAX_TPC_PER_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_FBPA_PER_FBP
#define NV2080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_LEGACY_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT NV0080_CTRL_GR_INFO_INDEX_MAX_PER_ENGINE_SUBCONTEXT_COUNT
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SINGLETON_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_TPCS_PER_GFXC_GPC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_SLICES_PER_LTC
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GFXC_SMC_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
#define NV2080_CTRL_GR_INFO_INDEX_DUMMY NV0080_CTRL_GR_INFO_INDEX_DUMMY
#define NV2080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES NV0080_CTRL_GR_INFO_INDEX_GFX_CAPABILITIES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES NV0080_CTRL_GR_INFO_INDEX_MAX_MIG_ENGINES
#define NV2080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS NV0080_CTRL_GR_INFO_INDEX_MAX_PARTITIONABLE_GPCS
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG NV0080_CTRL_GR_INFO_INDEX_LITTER_MIN_SUBCTX_PER_SMC_ENG
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_NUM_GPCS_PER_DIELET
#define NV2080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET NV0080_CTRL_GR_INFO_INDEX_LITTER_MAX_NUM_SMC_ENGINES_PER_DIELET
/* When adding a new INDEX, please update INDEX_MAX and MAX_SIZE accordingly
* NOTE: 0080 functionality is merged with 2080 functionality, so this max size
* reflects that.
*/
#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX
#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE
#define NV2080_CTRL_GR_INFO_INDEX_MAX NV0080_CTRL_GR_INFO_INDEX_MAX
#define NV2080_CTRL_GR_INFO_MAX_SIZE NV0080_CTRL_GR_INFO_MAX_SIZE
/* valid SM version return values */
#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_NONE (0x00000000U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_05 (0x00000105U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_1 (0x00000110U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_2 (0x00000120U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_3 (0x00000130U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_4 (0x00000140U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_1_5 (0x00000150U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_0 (0x00000200U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_1 (0x00000210U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_2_2 (0x00000220U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_0 (0x00000300U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_1 (0x00000310U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_2 (0x00000320U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_3 (0x00000330U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_5 (0x00000350U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_6 (0x00000360U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_8 (0x00000380U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_3_9 (0x00000390U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_4_0 (0x00000400U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_0 (0x00000500U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_02 (0x00000502U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_03 (0x00000503U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_0 (0x00000600U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_01 (0x00000601U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_02 (0x00000602U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_0 (0x00000700U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_01 (0x00000701U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_02 (0x00000702U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_03 (0x00000703U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_05 (0x00000705U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_02 (0x00000802U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_06 (0x00000806U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_07 (0x00000807U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_08 (0x00000808U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_09 (0x00000809U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_00 (0x00000900U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_00 (0x00000A00U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_01 (0x00000A01U)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_04 (0x00000A04U)
/* compatibility SM versions to match the official names in the ISA (e.g., SM5.2) */
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_2 (NV2080_CTRL_GR_INFO_SM_VERSION_5_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_5_3 (NV2080_CTRL_GR_INFO_SM_VERSION_5_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_1 (NV2080_CTRL_GR_INFO_SM_VERSION_6_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_6_2 (NV2080_CTRL_GR_INFO_SM_VERSION_6_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_1 (NV2080_CTRL_GR_INFO_SM_VERSION_7_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_2 (NV2080_CTRL_GR_INFO_SM_VERSION_7_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_3 (NV2080_CTRL_GR_INFO_SM_VERSION_7_03)
#define NV2080_CTRL_GR_INFO_SM_VERSION_7_5 (NV2080_CTRL_GR_INFO_SM_VERSION_7_05)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_2 (NV2080_CTRL_GR_INFO_SM_VERSION_8_02)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_6 (NV2080_CTRL_GR_INFO_SM_VERSION_8_06)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_7 (NV2080_CTRL_GR_INFO_SM_VERSION_8_07)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_8 (NV2080_CTRL_GR_INFO_SM_VERSION_8_08)
#define NV2080_CTRL_GR_INFO_SM_VERSION_8_9 (NV2080_CTRL_GR_INFO_SM_VERSION_8_09)
#define NV2080_CTRL_GR_INFO_SM_VERSION_9_0 (NV2080_CTRL_GR_INFO_SM_VERSION_9_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_0 (NV2080_CTRL_GR_INFO_SM_VERSION_10_00)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_1 (NV2080_CTRL_GR_INFO_SM_VERSION_10_01)
#define NV2080_CTRL_GR_INFO_SM_VERSION_10_4 (NV2080_CTRL_GR_INFO_SM_VERSION_10_04)
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D 0:0
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_2D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D 1:1
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_3D_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE 2:2
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_COMPUTE_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M 3:3
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_FALSE 0x0U
#define NV2080_CTRL_GR_INFO_GFX_CAPABILITIES_I2M_TRUE 0x1U
/**
* NV2080_CTRL_CMD_GR_GET_INFO
@@ -367,7 +377,7 @@ typedef NV0080_CTRL_GR_INFO NV2080_CTRL_GR_INFO;
* disambiguate the target GR engine. When MIG is enabled, this
* is a mandatory parameter.
*/
#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GR_GET_INFO (0x20801201U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GR_GET_INFO_PARAMS_MESSAGE_ID (0x1U)
@@ -1909,26 +1919,29 @@ typedef struct NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS {
} NV2080_CTRL_GR_GET_GFX_GPC_AND_TPC_INFO_PARAMS;
/*
* NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION
* NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK
*
* This command grabs information on GFX capable GPC's and TPC's for a specifc GR engine
* This command returns the TPC reconfig mask for a specific GPC
*
* promoType[IN]
* This parameter specifies what kind of sector promotion to perform
* gpc[IN]
* The GPC for which the TPC reconfig mask needs to be queried.
* The GPC should be specified as a logical index.
*
* tpcReconfigMask[OUT]
* Mask of reconfigurable TPCs in the specified GPC
*
* grRouteInfo[IN]
* This parameter specifies the routing information used to
* disambiguate the target GR engine.
*/
#define NV2080_CTRL_CMD_GR_SET_LG_SECTOR_PROMOTION (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GR_GET_TPC_RECONFIG_MASK (0x2080123bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GR_INTERFACE_ID << 8) | NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_NONE = 0,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_64B = 1,
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_128B = 2,
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE;
#define NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS_MESSAGE_ID (0x3bU)
#define NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS_MESSAGE_ID (0x3BU)
typedef struct NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS {
NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_TYPE promoType;
} NV2080_CTRL_GR_SET_LG_SECTOR_PROMOTION_PARAMS;
typedef struct NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS {
NvU32 gpc;
NvU32 tpcReconfigMask;
NV_DECLARE_ALIGNED(NV2080_CTRL_GR_ROUTE_INFO grRouteInfo, 8);
} NV2080_CTRL_GR_GET_TPC_RECONFIG_MASK_PARAMS;
/* _ctrl2080gr_h_ */

55
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gsp.h
View File

@@ -131,8 +131,63 @@ typedef struct NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT {
typedef struct NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS {
NvU32 gfid;
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT current, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_RM_HEAP_STATS_SNAPSHOT peak, 8);
} NV2080_CTRL_GSP_GET_RM_HEAP_STATS_PARAMS;
/*
* NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS
*
* This command reports the current partition's VGPU-GSP plugin's heap usage statistics.
*
* managedSize
* The total size in bytes of the underlying heap. Note that not all memory
* will be allocatable, due to fragmentation and memory allocator/tracking
* overhead.
* allocatedSize
* Allocated memory size, in bytes. This value does not include overhead used
* by the underlying allocator for padding/metadata.
* allocationCount
* The number of active allocations. This count reflects the current number of
* memory blocks that have been allocated but not yet freed.
* peakAllocatedSize
* The highest recorded allocated memory size, in bytes. This value represents the
* maximum amount of memory that has been allocated at any point in time. When a new
* highest allocated size is recorded, the peakAllocatedSize is updated.
* peakAllocationCount
* The number of active allocations corresponding to the highest recorded peakAllocatedSize.
*/
#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS (0x20803603) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS_MESSAGE_ID (0x3U)
typedef struct NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NvU64 allocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 peakAllocatedSize, 8);
NV_DECLARE_ALIGNED(NvU64 managedSize, 8);
NvU32 allocationCount;
NvU32 peakAllocationCount;
NV_DECLARE_ALIGNED(NvU64 largestFreeChunkSize, 8);
} NV2080_CTRL_CMD_GSP_GET_VGPU_HEAP_STATS_PARAMS;
#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS (0x20803604) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_GSP_INTERFACE_ID << 8) | NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX 64
typedef struct NV2080_CTRL_GSP_LIBOS_POOL_STATS {
NvU32 allocations;
NvU32 peakAllocations;
NV_DECLARE_ALIGNED(NvU64 objectSize, 8);
} NV2080_CTRL_GSP_LIBOS_POOL_STATS;
#define NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS_MESSAGE_ID (0x4U)
typedef struct NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_GSP_LIBOS_POOL_STATS poolStats[NV2080_CTRL_GSP_LIBOS_POOL_COUNT_MAX], 8);
NV_DECLARE_ALIGNED(NvU64 totalHeapSize, 8);
NvU8 poolCount;
} NV2080_CTRL_CMD_GSP_GET_LIBOS_HEAP_STATS_PARAMS;
// _ctrl2080gsp_h_

626
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h
View File

@@ -79,6 +79,7 @@ typedef struct NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS {
NvU32 embeddedDisplayPortMask;
NvBool bExternalMuxSupported;
NvBool bInternalMuxSupported;
NvU32 numDispChannels;
} NV2080_CTRL_INTERNAL_DISPLAY_GET_STATIC_INFO_PARAMS;
@@ -2195,7 +2196,6 @@ typedef struct NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS {
NvBool bIsC2CLinkUp;
NvBool bIsDeviceMultiFunction;
NvBool bGcxPmuCfgSpaceRestore;
NV_DECLARE_ALIGNED(NvU64 dmaWindowStartAddress, 8);
} NV2080_CTRL_INTERNAL_BIF_GET_STATIC_INFO_PARAMS;
/*!
@@ -2227,33 +2227,6 @@ typedef struct NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS {
NvU32 programPciePeerMask;
} NV2080_CTRL_INTERNAL_HSHUB_PEER_CONN_CONFIG_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID
*
* Given a mask of link ids, find the first with a valid peerId.
*
* linkMask[IN]
* Mask of linkIds to check.
*
* peerId[OUT]
* The peerId for the lowest-index link with a valid peerId, if any.
* If none found, NV2080_CTRLINTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER (return value will still be NV_OK).
*
* Possible status values returned are:
* NV_OK
*
*/
#define NV2080_CTRL_CMD_INTERNAL_HSHUB_FIRST_LINK_PEER_ID (0x20800a89) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_INVALID_PEER 0xffffffff
#define NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS {
NvU32 linkMask;
NvU32 peerId;
} NV2080_CTRL_INTERNAL_HSHUB_FIRST_LINK_PEER_ID_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_HSHUB_GET_HSHUB_ID_FOR_LINKS
*
@@ -2806,7 +2779,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_ATTACH_AND_INIT_PARAMS {
#define NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS_MESSAGE_ID (0xBFU)
typedef struct NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS {
NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters;
NV_DECLARE_ALIGNED(NV30F1_CTRL_GSYNC_GET_OPTIMIZED_TIMING_PARAMS timingParameters, 8);
} NV2080_CTRL_INTERNAL_GSYNC_OPTIMIZE_TIMING_PARAMETERS_PARAMS;
/*!
@@ -2952,6 +2925,7 @@ typedef struct NV2080_CTRL_INTERNAL_GSYNC_SET_OR_RESTORE_RASTER_SYNC_PARAMS {
* Handle to SYSMEM memlist object
* [in] bEnteringGcoffState
* Value of PDB_PROP_GPU_GCOFF_STATE_ENTERING
* [in] sysmemAddrOfSuspendResumeData
*
* Possible status values returned are:
* NV_OK
@@ -2967,6 +2941,7 @@ typedef struct NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS {
NvHandle hClient;
NvHandle hSysMem;
NvBool bEnteringGcoffState;
NV_DECLARE_ALIGNED(NvU64 sysmemAddrOfSuspendResumeData, 8);
} NV2080_CTRL_INTERNAL_FBSR_INIT_PARAMS;
/*!
@@ -3822,6 +3797,23 @@ typedef struct NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS
} NV2080_CTRL_CMD_INTERNAL_CONF_COMPUTE_SET_SECURITY_POLICY_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID
*
* This command is an internal command sent from Kernel RM to Physical RM
* to update the logical Uproc Id for the configuration.
*
* logicalUprocId [OUT]
*/
#define NV2080_CTRL_CMD_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID (0x20800aef) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS_MESSAGE_ID (0xEFU)
typedef struct NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS {
NvU8 logicalUprocId;
} NV2080_CTRL_INTERNAL_FIFO_GET_LOGICAL_UPROC_ID_PARAMS;
/*
* NV2080_CTRL_CMD_INTERNAL_MEMMGR_MEMORY_TRANSFER_WITH_GSP
@@ -4021,6 +4013,7 @@ typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
* @brief Set mask of data to be polled on physical for RUSD
*
* @param[in] polledDataMask Bitmask of data requested, defined in cl00de
* @param[in] pollFrequencyMs Requested polling interval, in ms
*
* @return NV_OK on success
* @return NV_ERR_ otherwise
@@ -4029,6 +4022,7 @@ typedef struct NV2080_CTRL_INTERNAL_INIT_USER_SHARED_DATA_PARAMS {
typedef struct NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS {
NV_DECLARE_ALIGNED(NvU64 polledDataMask, 8);
NvU32 pollFrequencyMs;
} NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL (0x20800aff) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_USER_SHARED_DATA_SET_DATA_POLL_PARAMS_MESSAGE_ID" */
@@ -4128,8 +4122,17 @@ typedef struct NV2080_CTRL_INTERNAL_GPU_CLIENT_LOW_POWER_MODE_ENTER_PARAMS {
* This command is used to perform recovery actions after the fabric has been
* idled due to a fatal nvlink error.
* This command accepts no parameters.
*
* bSuccessful
* NV_TRUE if recovery was successful, NV_FALSE otherwise
*/
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | 0xEA" */
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY (0x20800aea) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS_MESSAGE_ID (0xEAU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS {
NvBool bSuccessful;
} NV2080_CTRL_INTERNAL_NVLINK_POST_FATAL_ERROR_RECOVERY_PARAMS;
/*!
* NV2080_CTRL_CMD_INTERNAL_GPU_GET_GSP_RM_FREE_HEAP
@@ -4686,4 +4689,567 @@ typedef struct NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS {
} NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER (0x20800a50U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_POST_SETUP_NVLINK_PEER_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID
*
* Log an XID message to OOB.
*
* xid [in]
* The XID number of the message.
*
* message [in]
* The text message, including the NULL terminator.
*
* len [in]
* The length, in bytes, of the text message, excluding the NULL terminator.
*
* Possible status return values are:
* NV_OK
* NV_ERR_INVALID_ARGUMENT
*/
#define NV2080_CTRL_CMD_INTERNAL_LOG_OOB_XID (0x20800a56U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID" */
#define NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE (81U)
#define NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS_MESSAGE_ID (0x56U)
typedef struct NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS {
NvU32 xid;
NvU8 message[NV2080_INTERNAL_OOB_XID_MESSAGE_BUFFER_SIZE];
NvU32 len;
} NV2080_CTRL_INTERNAL_LOG_OOB_XID_PARAMS;
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING
*
* Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
*
* [In] mapTypeMask
* Remove NVLink mapping for the given map types (sysmem or peer or both)
* [In] peerMask
* Mask of Peer IDs which needs to be removed on NVLink
* Only parsed if mapTypeMask accounts peer
* [In] bL2Entry
* Is the peer removal happening because links are entering L2 low power state?
* Only parsed if mapTypeMask accounts peer
*/
#define NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x5FU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
NvU32 mapTypeMask;
NvU32 peerMask;
NvBool bL2Entry;
} NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING (0x20800a5fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE
*
* Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
*
* [In] bSave
* Whether this is a save/restore operation
* [In] linkMask
* Mask of links for which HSHUB config registers need to be saved/restored
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x62U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
NvBool bSave;
NvU32 linkMask;
} NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20800a62U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000)
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001)
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002)
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY
*
* Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
*
* [In] flags
* Whether to set, save or restore bufferready
* [In] bSysmem
* Whether to perform the operation for sysmem links or peer links
* [In] peerLinkMask
* Mask of peer links for which bufferready state need to be set/saved/restored
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x64U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_BUFFERREADY (0x20800a64U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG
*
* Performs all the necessary actions required to update the current Nvlink configuration
*
* [out] bNvlinkSysmemEnabled
* Whether sysmem nvlink support was enabled
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x78U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
NvBool bNvlinkSysmemEnabled;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG (0x20800a78U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK
*
* Synchronizes the peerLinkMask between CPU-RM and GSP-RM
*
* [In] gpuInst
* Gpu instance
* [In] peerLinkMask
* Mask of links to the given peer GPU
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x7DU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK (0x20800a7dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION
*
* Updates the remote connection information for a link
*
* [In] linkId
* Id of the link to be used
* [In] bConnected
* Boolean that tracks whether the link is connected
* [In] remoteDeviceType
* Tracks whether the remote device is switch/gpu/ibmnpu/tegra
* [In] remoteLinkNumber
* Tracks the link number for the connected remote device
*/
#define NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x82U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
NvU32 linkId;
NvU32 laneRxdetStatusMask;
NvU32 remoteLinkNumber;
NvU32 remotePciDeviceId;
NvU32 remoteDomain;
NvU8 remoteBus;
NvU8 remoteDevice;
NvU8 remoteFunction;
NvBool bConnected;
} NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION (0x20800a82U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
*
* Enable links post topology via GSP
*
* [In] linkMask
* Mask of links to enable
* [Out] initializedLinks
* Mask of links that were initialized
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x83U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
NvU32 linkMask;
NvU32 initializedLinks;
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20800a83U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x84U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI (0x20800a84U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE 64
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET
*
* Get link mask post Rx detection
*
* [Out] postRxDetLinkMask
* Mask of links discovered
* [Out] laneRxdetStatusMask
* RXDET per-lane status mask
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x85U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
NV_DECLARE_ALIGNED(NvU64 postRxDetLinkMask, 8);
NvU32 laneRxdetStatusMask[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET (0x20800a85U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x86U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_LINK_TRAIN_ALI (0x20800a86U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES {
NvBool bValid;
NvU8 linkId;
NvU32 ioctrlId;
NvU8 pllMasterLinkId;
NvU8 pllSlaveLinkId;
NvU32 ipVerDlPl;
} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO
*
* [Out] ioctrlMask
* Mask of IOCTRLs discovered from PTOP device info table
* [Out] ioctrlNumEntries
* Number of IOCTRL entries in the PTOP device info table
* [Out] ioctrlSize
* Maximum number of entries in the PTOP device info table
* [Out] discoveredLinks
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x87U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlMask;
NvU8 ioctrlNumEntries;
NvU32 ioctrlSize;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 ipVerNvlink;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO (0x20800a87U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES {
NvU32 ipVerIoctrl;
NvU32 ipVerMinion;
} NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO
*
* [In] ioctrlIdx
* IOCTRL index
* [Out] PublicId
* PublicId of the IOCTRL discovered
* [Out] localDiscoveredLinks
* Mask of discovered links local to the IOCTRL
* [Out] localGlobalLinkOffset
* Global link offsets for the locally discovered links
* [Out] ioctrlDiscoverySize
* IOCTRL table size
* [Out] numDevices
* Number of devices discovered from the IOCTRL
* [Out] deviceIpRevisions
* IP revisions for the devices discovered in the IOCTRL
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
NvU32 ioctrlIdx;
NvU32 PublicId;
NvU32 localDiscoveredLinks;
NvU32 localGlobalLinkOffset;
NvU32 ioctrlDiscoverySize;
NvU8 numDevices;
NV2080_CTRL_INTERNAL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
} NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO (0x20800a8eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED
*
* Program NVLink Speed from OS/VBIOS
*
* [In] bPlatformLinerateDefined
* Whether line rate is defined in the platform
* [In] platformLineRate
* Platform defined line rate
* [Out] nvlinkLinkSpeed
* The line rate that was programmed for the links
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
NvBool bPlatformLinerateDefined;
NvU32 platformLineRate;
NvU32 nvlinkLinkSpeed;
} NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROGRAM_LINK_SPEED (0x20800a8fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED
*
* [In] linkMask
* Mask of links whose state will be checked
* [In] bActiveOnly
* The input boolean to check for Link Active state
* [Out] bIsLinkActive
* Boolean array to track if the link is trained
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x90U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
NvU32 linkMask;
NvBool bActiveOnly;
NvBool bIsLinkActive[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ARE_LINKS_TRAINED (0x20800a90U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_ASSERT (0x00000000)
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001)
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002)
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS
*
* [In] linkMask
* Mask of links which need to be reset
* [In] flags
* Whether to assert, de-assert or toggle the Nvlink reset
*/
#define NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x91U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS {
NvU32 linkMask;
NvU32 flags;
} NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_RESET_LINKS (0x20800a91U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS
*
* [In] linkMask
* Mask of links for which DL interrrupts need to be disabled
*/
#define NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x92U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
NvU32 linkMask;
} NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS (0x20800a92U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
/*
* Structure to store the GET_LINK_AND_CLOCK__INFO params
*
* [Out] bLinkConnectedToSystem
* Boolean indicating sysmem connection of a link
* [Out] bLinkConnectedToPeer
* Boolean indicating peer connection of a link
* [Out] bLinkReset
* Whether the link is in reset
* [Out] subLinkWidth
* Number of lanes per sublink
* [Out] linkState
* Mode of the link
* [Out] txSublinkState
* Tx sublink state
* [Out] rxSublinkState
* Rx sublink state
* [Out] bLaneReversal
* Boolean indicating if a link's lanes are reversed
* [Out] nvlinkLinkClockKHz
* Link clock value in KHz
* [Out] nvlinkLineRateMbps
* Link line rate in Mbps
* [Out] nvlinkLinkClockMhz
* Link clock in MHz
* [Out] nvlinkLinkDataRateKiBps
* Link Data rate in KiBps
* [Out] nvlinkRefClkType
* Current Nvlink refclk source
* [Out] nvlinkReqLinkClockMhz
* Requested link clock value
* [Out] nvlinkMinL1Threshold
* Requested link Min L1 Threshold
* [Out] nvlinkMaxL1Threshold
* Requested link Max L1 Threshold
* [Out] nvlinkL1ThresholdUnits
* Requested link L1 Threshold Units
*/
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvBool bLinkConnectedToSystem;
NvBool bLinkConnectedToPeer;
NvBool bLinkReset;
NvU8 subLinkWidth;
NvU32 linkState;
NvU32 txSublinkState;
NvU32 rxSublinkState;
NvBool bLaneReversal;
NvU32 nvlinkLinkClockKHz;
NvU32 nvlinkLineRateMbps;
NvU32 nvlinkLinkClockMhz;
NvU32 nvlinkLinkDataRateKiBps;
NvU8 nvlinkRefClkType;
NvU32 nvlinkReqLinkClockMhz;
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO
*
* [In] linkMask
* Mask of enabled links to loop over
* [Out] nvlinkRefClkSpeedKHz
* Ref clock value n KHz
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x93U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20800a93U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM
*
* Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
*
* [In] sysmemLinkMask
* Mask of discovered sysmem NVLinks
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x94U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM (0x20800a94U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS
*
* Process NVLink forced configurations which includes setting of HSHUB and memory system
*
* [In] bLegacyForcedConfig
* Tracks whether the forced config is legacy forced config or chiplib config
* [Out] bOverrideComputePeerMode
* Whether compute peer mode was enabled
* [In] phase
* Only applicable when bLegacyForcedConfig is true
* Tracks the set of registers to program from the NVLink table
* [In] linkConnection
* Array of chiplib configurations
*/
#define NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x95U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
NvBool bLegacyForcedConfig;
NvBool bOverrideComputePeerMode;
NvU32 phase;
NvU32 linkConnection[NV2080_CTRL_INTERNAL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS (0x20800a95U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
*
* Sync the NVLink lane shutdown properties with GSP-RM
*
* [In] bLaneShutdownOnUnload
* Whether nvlink shutdown should be triggered on driver unload
*/
#define NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x96U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
NvBool bLaneShutdownOnUnload;
} NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20800a96U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
*
* Enable ATS functionality related to NVLink sysmem if hardware support is available
*
* [In] notUsed
*/
#define NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x97U)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
NvU32 notUsed;
} NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20800a97U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
*
* Get the mask of Nvlink links connected to system
*
* [Out] sysmemLinkMask
* Mask of Nvlink links connected to system
*/
#define NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0xABU)
typedef struct NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20800aabU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/* ctrl2080internal_h */

12
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080mc.h
View File

@@ -81,6 +81,8 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_AD100 (0x00000190)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB100 (0x000001A0)
#define NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_GB200 (0x000001B0)
/* valid ARCHITECTURE_T23X implementation values */
@@ -132,6 +134,16 @@ typedef struct NV2080_CTRL_MC_GET_ARCH_INFO_PARAMS {
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB102 (0x00000002)
/* valid ARCHITECTURE_GB20x implementation values */
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB200 (0x00000000)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB202 (0x00000002)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB203 (0x00000003)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB204 (0x00000004)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB205 (0x00000005)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB206 (0x00000006)
#define NV2080_CTRL_MC_ARCH_INFO_IMPLEMENTATION_GB207 (0x00000007)
/* Valid Chip sub revisions */
#define NV2080_CTRL_MC_ARCH_INFO_SUBREVISION_NO_SUBREVISION (0x00000000)

726
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -50,9 +50,13 @@
* This field specifies the lowest supported NCI version for this subdevice.
* highestNciVersion
* This field specifies the highest supported NCI version for this subdevice.
* discoveredLinkMask
* discoveredLinkMask // deprecated use discovered links
* This field provides a bitfield mask of NVLink links discovered on this subdevice.
* enabledLinkMask
* enabledLinkMask // deprecated use enabled Links
* This field provides a bitfield mask of NVLink links enabled on this subdevice.
* discoveredLinks
* This field provides a bitfield mask of NVLink links discovered on this subdevice.
* enabledLinks
* This field provides a bitfield mask of NVLink links enabled on this subdevice.
*
*/
@@ -68,6 +72,9 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
NvU32 discoveredLinkMask;
NvU32 enabledLinkMask;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NV_DECLARE_ALIGNED(NvU64 enabledLinks, 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS;
/* extract cap bit setting from tbl */
@@ -175,6 +182,8 @@ typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_CAPS_PARAMS {
* See NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_* for possible values
* deviceUUID
* This field specifies the device UUID of the device. Useful for identifying the device (or version)
* fabricRecoveryStatusMask
* This field contains flags which advertise the current GPU-centric health status of the NVLINKs
*/
typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
// ID Flags
@@ -192,21 +201,31 @@ typedef struct NV2080_CTRL_NVLINK_DEVICE_INFO {
// Device UUID
NvU8 deviceUUID[16];
// GPU-centric fabric health
NvU32 fabricRecoveryStatusMask;
} NV2080_CTRL_NVLINK_DEVICE_INFO;
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS 31:0
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_NONE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_PCI (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_ID_FLAGS_UUID (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_EBRIDGE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NPU (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_GPU (0x00000002U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_SWITCH (0x00000003U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_TEGRA (0x00000004U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_TYPE_NONE (0x000000FFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_DEVICE_UUID_INVALID (0xFFFFFFFFU)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED 0:0
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_FALSE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_GPU_DEGRADED_TRUE (0x00000001U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY 1:1
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_INACTIVE (0x00000000U)
#define NV2080_CTRL_NVLINK_DEVICE_INFO_FABRIC_RECOVERY_STATUS_MASK_UNCONTAINED_ERROR_RECOVERY_ACTIVE (0x00000001U)
/*
* NV2080_CTRL_NVLINK_NVLINK_LINK_STATUS_INFO
@@ -409,6 +428,7 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
} NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT;
#define NV2080_CTRL_NVLINK_MAX_LINKS 32
#define NV2080_CTRL_NVLINK_MAX_ARR_SIZE 64
// NVLink REFCLK types
#define NV2080_CTRL_NVLINK_REFCLK_TYPE_INVALID (0x00U)
@@ -420,7 +440,7 @@ typedef enum NV2080_CTRL_NVLINK_STATUS_L1_THRESHOLD_UNIT {
typedef struct NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS {
NvU32 enabledLinkMask;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_LINK_STATUS_INFO linkInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_CMD_NVLINK_GET_NVLINK_STATUS_PARAMS;
/*
@@ -691,7 +711,7 @@ typedef struct NV2080_CTRL_NVLINK_COMMON_ERR_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_ERR_INFO_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_ERR_INFO linkErrInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
NvU32 ioctrlMask;
NV2080_CTRL_NVLINK_COMMON_ERR_INFO commonErrInfo[NV2080_CTRL_NVLINK_MAX_IOCTRLS];
NvU8 ErrInfoFlags;
@@ -799,7 +819,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS {
NvU32 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_GET_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS (0x20803004U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -1008,7 +1028,7 @@ typedef struct NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES {
typedef struct NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NvU64 counterMask[NV2080_CTRL_NVLINK_COUNTER_MAX_GROUPS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_LINKS][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_COUNTERS_V2_VALUES counter[NV2080_CTRL_NVLINK_MAX_ARR_SIZE][NV2080_CTRL_NVLINK_COUNTER_MAX_COUNTERS_PER_LINK_IN_REQ], 8);
} NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_COUNTERS_V2 (0x20803050U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | NV2080_CTRL_NVLINK_GET_COUNTERS_V2_PARAMS_MESSAGE_ID)" */
@@ -1138,7 +1158,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG {
typedef struct NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_HW_ERROR_INJECT_CFG errCfg[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SET_HW_ERROR_INJECT (0x20803081U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
@@ -1189,7 +1209,7 @@ typedef struct NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO {
typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_HW_ERROR_INJECT_INFO errInfo[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_HW_ERROR_INJECT (0x20803082U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS_MESSAGE_ID" */
@@ -1209,7 +1229,7 @@ typedef struct NV2080_CTRL_NVLINK_GET_HW_ERROR_INJECT_PARAMS {
typedef struct NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS {
NvU32 linkMask;
NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_LINKS];
NvU32 numRecoveries[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_CMD_NVLINK_GET_ERROR_RECOVERIES_PARAMS;
/*
@@ -1891,7 +1911,7 @@ typedef struct NV2080_CTRL_NVLINK_LINK_ECC_ERROR {
typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_LINKS];
NV2080_CTRL_NVLINK_LINK_ECC_ERROR errorLink[NV2080_CTRL_NVLINK_MAX_ARR_SIZE];
} NV2080_CTRL_NVLINK_GET_NVLINK_ECC_ERRORS_PARAMS;
@@ -1960,7 +1980,7 @@ typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES {
typedef struct NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS {
NvU16 counterMask;
NV_DECLARE_ALIGNED(NvU64 linkMask, 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_LINKS], 8);
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_READ_TP_COUNTERS_VALUES counters[NV2080_CTRL_NVLINK_MAX_ARR_SIZE], 8);
} NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_READ_TP_COUNTERS (0x20803015U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_READ_TP_COUNTERS_PARAMS_MESSAGE_ID" */
@@ -2028,93 +2048,10 @@ typedef struct NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS {
NvU32 counterValues[NV2080_CTRL_NVLINK_GET_LP_COUNTERS_MAX_COUNTERS];
} NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_GET_LP_COUNTERS (0x20803018U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LP_COUNTERS_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
#define NV2080_CTRL_CMD_NVLINK_CLEAR_LP_COUNTERS (0x20803052U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8 | 0x52)" */
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_SYSMEM 0x1U
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_TYPE_PEER 0x2U
/*
* NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING
*
* Performs all the necessary actions required to remove NVLink mapping (sysmem or peer or both)
*
* [In] mapTypeMask
* Remove NVLink mapping for the given map types (sysmem or peer or both)
* [In] peerMask
* Mask of Peer IDs which needs to be removed on NVLink
* Only parsed if mapTypeMask accounts peer
* [In] bL2Entry
* Is the peer removal happening because links are entering L2 low power state?
* Only parsed if mapTypeMask accounts peer
*/
#define NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID (0x1fU)
typedef struct NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS {
NvU32 mapTypeMask;
NvU32 peerMask;
NvBool bL2Entry;
} NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_REMOVE_NVLINK_MAPPING (0x2080301fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_REMOVE_NVLINK_MAPPING_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE
*
* Performs all the necessary actions required to save/restore HSHUB state during NVLink L2 entry/exit
*
* [In] bSave
* Whether this is a save/restore operation
* [In] linkMask
* Mask of links for which HSHUB config registers need to be saved/restored
*/
#define NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID (0x20U)
typedef struct NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS {
NvBool bSave;
NvU32 linkMask;
} NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SAVE_RESTORE_HSHUB_STATE (0x20803020U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SAVE_RESTORE_HSHUB_STATE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SET (0x00000000)
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_SAVE (0x00000001)
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_FLAGS_RESTORE (0x00000002)
/*
* NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY
*
* Performs all the necessary actions required to save/restore bufferready state during NVLink L2 entry/exit
*
* [In] flags
* Whether to set, save or restore bufferready
* [In] bSysmem
* Whether to perform the operation for sysmem links or peer links
* [In] peerLinkMask
* Mask of peer links for which bufferready state need to be set/saved/restored
*/
#define NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID (0x21U)
typedef struct NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS {
NvU32 flags;
NvBool bSysmem;
NvU32 peerLinkMask;
} NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROGRAM_BUFFERREADY (0x20803021U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_BUFFERREADY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG
*
* Performs all the necessary actions required to update the current Nvlink configuration
*
* [out] bNvlinkSysmemEnabled
* Whether sysmem nvlink support was enabled
*/
#define NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID (0x22U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS {
NvBool bNvlinkSysmemEnabled;
} NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_CURRENT_CONFIG (0x20803022U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_CURRENT_CONFIG_PARAMS_MESSAGE_ID" */
//
// Set the near end loopback mode using the following
@@ -2149,93 +2086,6 @@ typedef struct NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_SET_LOOPBACK_MODE (0x20803023U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SET_LOOPBACK_MODE_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK
*
* Synchronizes the peerLinkMask between CPU-RM and GSP-RM
*
* [In] gpuInst
* Gpu instance
* [In] peerLinkMask
* Mask of links to the given peer GPU
*/
#define NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID (0x24U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS {
NvU32 gpuInst;
NvU32 peerLinkMask;
} NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_PEER_LINK_MASK (0x20803024U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_PEER_LINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION
*
* Updates the remote connection information for a link
*
* [In] linkId
* Id of the link to be used
* [In] bConnected
* Boolean that tracks whether the link is connected
* [In] remoteDeviceType
* Tracks whether the remote device is switch/gpu/ibmnpu/tegra
* [In] remoteLinkNumber
* Tracks the link number for the connected remote device
*/
#define NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID (0x25U)
typedef struct NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS {
NV_DECLARE_ALIGNED(NvU64 remoteDeviceType, 8);
NV_DECLARE_ALIGNED(NvU64 remoteChipSid, 8);
NvU32 linkId;
NvU32 laneRxdetStatusMask;
NvU32 remoteLinkNumber;
NvU32 remotePciDeviceId;
NvU32 remoteDomain;
NvU8 remoteBus;
NvU8 remoteDevice;
NvU8 remoteFunction;
NvBool bConnected;
} NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_UPDATE_LINK_CONNECTION (0x20803025U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_UPDATE_LINK_CONNECTION_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY
*
* Enable links post topology via GSP
*
* [In] linkMask
* Mask of links to enable
* [Out] initializedLinks
* Mask of links that were initialized
*/
#define NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID (0x26U)
typedef struct NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS {
NvU32 linkMask;
NvU32 initializedLinks;
} NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ENABLE_LINKS_POST_TOPOLOGY (0x20803026U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_LINKS_POST_TOPOLOGY_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x27U)
typedef struct NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRE_LINK_TRAIN_ALI (0x20803027U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRE_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
//
// Read Refresh counter - the pass/fail occurrences
//
@@ -2290,366 +2140,6 @@ typedef struct NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_CLEAR_REFRESH_COUNTERS (0x20803029U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CLEAR_REFRESH_COUNTERS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET
*
* Get link mask post Rx detection
*
* [Out] postRxDetLinkMask
* Mask of links discovered
* [Out] laneRxdetStatusMask
* RXDET per-lane status mask
*/
#define NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID (0x2aU)
typedef struct NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS {
NvU32 postRxDetLinkMask;
NvU32 laneRxdetStatusMask[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_MASK_POST_RX_DET (0x2080302aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_MASK_POST_RX_DET_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI
*
* [In] linkMask
* Mask of enabled links to train
* [In] bSync
* The input sync boolean
*/
#define NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID (0x2bU)
typedef struct NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS {
NvU32 linkMask;
NvBool bSync;
} NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_LINK_TRAIN_ALI (0x2080302bU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_LINK_TRAIN_ALI_PARAMS_MESSAGE_ID" */
typedef struct NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES {
NvBool bValid;
NvU8 linkId;
NvU32 ioctrlId;
NvU8 pllMasterLinkId;
NvU8 pllSlaveLinkId;
NvU32 ipVerDlPl;
} NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO
*
* [Out] ioctrlMask
* Mask of IOCTRLs discovered from PTOP device info table
* [Out] ioctrlNumEntries
* Number of IOCTRL entries in the PTOP device info table
* [Out] ioctrlSize
* Maximum number of entries in the PTOP device info table
* [Out] discoveredLinks
* Mask of links discovered from all the IOCTRLs
* [Out] ipVerNvlink
* IP revision of the NVLink HW
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2cU)
typedef struct NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS {
NvU32 ioctrlMask;
NvU8 ioctrlNumEntries;
NvU32 ioctrlSize;
NvU32 discoveredLinks;
NvU32 ipVerNvlink;
NV2080_CTRL_NVLINK_DEVICE_LINK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_NVLINK_DEVICE_INFO (0x2080302cU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_NVLINK_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_MAX_LINKS_PER_IOCTRL_SW 6U
typedef struct NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES {
NvU32 ipVerIoctrl;
NvU32 ipVerMinion;
} NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO
*
* [In] ioctrlIdx
* IOCTRL index
* [Out] PublicId
* PublicId of the IOCTRL discovered
* [Out] localDiscoveredLinks
* Mask of discovered links local to the IOCTRL
* [Out] localGlobalLinkOffset
* Global link offsets for the locally discovered links
* [Out] ioctrlDiscoverySize
* IOCTRL table size
* [Out] numDevices
* Number of devices discovered from the IOCTRL
* [Out] deviceIpRevisions
* IP revisions for the devices discovered in the IOCTRL
*/
#define NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x2dU)
typedef struct NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS {
NvU32 ioctrlIdx;
NvU32 PublicId;
NvU32 localDiscoveredLinks;
NvU32 localGlobalLinkOffset;
NvU32 ioctrlDiscoverySize;
NvU8 numDevices;
NV2080_CTRL_NVLINK_DEVICE_IP_REVISION_VALUES ipRevisions;
} NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_IOCTRL_DEVICE_INFO (0x2080302dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_IOCTRL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED
*
* Program NVLink Speed from OS/VBIOS
*
* [In] bPlatformLinerateDefined
* Whether line rate is defined in the platform
* [In] platformLineRate
* Platform defined line rate
* [Out] nvlinkLinkSpeed
* The line rate that was programmed for the links
*/
#define NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID (0x2eU)
typedef struct NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS {
NvBool bPlatformLinerateDefined;
NvU32 platformLineRate;
NvU32 nvlinkLinkSpeed;
} NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROGRAM_LINK_SPEED (0x2080302eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROGRAM_LINK_SPEED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED
*
* [In] linkMask
* Mask of links whose state will be checked
* [In] bActiveOnly
* The input boolean to check for Link Active state
* [Out] bIsLinkActive
* Boolean array to track if the link is trained
*/
#define NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID (0x2fU)
typedef struct NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS {
NvU32 linkMask;
NvBool bActiveOnly;
NvBool bIsLinkActive[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ARE_LINKS_TRAINED (0x2080302fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ARE_LINKS_TRAINED_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_RESET_FLAGS_ASSERT (0x00000000)
#define NV2080_CTRL_NVLINK_RESET_FLAGS_DEASSERT (0x00000001)
#define NV2080_CTRL_NVLINK_RESET_FLAGS_TOGGLE (0x00000002)
/*
* NV2080_CTRL_CMD_NVLINK_RESET_LINKS
*
* [In] linkMask
* Mask of links which need to be reset
* [In] flags
* Whether to assert, de-assert or toggle the Nvlink reset
*/
#define NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID (0x30U)
typedef struct NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS {
NvU32 linkMask;
NvU32 flags;
} NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_RESET_LINKS (0x20803030U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_RESET_LINKS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS
*
* [In] linkMask
* Mask of links for which DL interrrupts need to be disabled
*/
#define NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID (0x31U)
typedef struct NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS {
NvU32 linkMask;
} NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_DISABLE_DL_INTERRUPTS (0x20803031U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DISABLE_DL_INTERRUPTS_PARAMS_MESSAGE_ID" */
/*
* Structure to store the GET_LINK_AND_CLOCK__INFO params
*
* [Out] bLinkConnectedToSystem
* Boolean indicating sysmem connection of a link
* [Out] bLinkConnectedToPeer
* Boolean indicating peer connection of a link
* [Out] bLinkReset
* Whether the link is in reset
* [Out] subLinkWidth
* Number of lanes per sublink
* [Out] linkState
* Mode of the link
* [Out] txSublinkState
* Tx sublink state
* [Out] rxSublinkState
* Rx sublink state
* [Out] bLaneReversal
* Boolean indicating if a link's lanes are reversed
* [Out] nvlinkLinkClockKHz
* Link clock value in KHz
* [Out] nvlinkLineRateMbps
* Link line rate in Mbps
* [Out] nvlinkLinkClockMhz
* Link clock in MHz
* [Out] nvlinkLinkDataRateKiBps
* Link Data rate in KiBps
* [Out] nvlinkRefClkType
* Current Nvlink refclk source
* [Out] nvlinkReqLinkClockMhz
* Requested link clock value
* [Out] nvlinkMinL1Threshold
* Requested link Min L1 Threshold
* [Out] nvlinkMaxL1Threshold
* Requested link Max L1 Threshold
* [Out] nvlinkL1ThresholdUnits
* Requested link L1 Threshold Units
*/
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES {
NvBool bLinkConnectedToSystem;
NvBool bLinkConnectedToPeer;
NvBool bLinkReset;
NvU8 subLinkWidth;
NvU32 linkState;
NvU32 txSublinkState;
NvU32 rxSublinkState;
NvBool bLaneReversal;
NvU32 nvlinkLinkClockKHz;
NvU32 nvlinkLineRateMbps;
NvU32 nvlinkLinkClockMhz;
NvU32 nvlinkLinkDataRateKiBps;
NvU8 nvlinkRefClkType;
NvU32 nvlinkReqLinkClockMhz;
NvU32 nvlinkMinL1Threshold;
NvU32 nvlinkMaxL1Threshold;
NvU32 nvlinkL1ThresholdUnits;
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO
*
* [In] linkMask
* Mask of enabled links to loop over
* [Out] nvlinkRefClkSpeedKHz
* Ref clock value n KHz
* [Out] linkInfo
* Per link information
*/
#define NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID (0x32U)
typedef struct NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS {
NvU32 linkMask;
NvU32 nvlinkRefClkSpeedKHz;
NvBool bSublinkStateInst; // whether instantaneous sublink state is needed
NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_VALUES linkInfo[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_LINK_AND_CLOCK_INFO (0x20803032U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LINK_AND_CLOCK_INFO_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM
*
* Updates the HSHUB sysmem config resgister state to reflect sysmem NVLinks
*
* [In] sysmemLinkMask
* Mask of discovered sysmem NVLinks
*/
#define NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID (0x33U)
typedef struct NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SETUP_NVLINK_SYSMEM (0x20803033U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SETUP_NVLINK_SYSMEM_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS
*
* Process NVLink forced configurations which includes setting of HSHUB and memory system
*
* [In] bLegacyForcedConfig
* Tracks whether the forced config is legacy forced config or chiplib config
* [Out] bOverrideComputePeerMode
* Whether compute peer mode was enabled
* [In] phase
* Only applicable when bLegacyForcedConfig is true
* Tracks the set of registers to program from the NVLink table
* [In] linkConnection
* Array of chiplib configurations
*/
#define NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID (0x34U)
typedef struct NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS {
NvBool bLegacyForcedConfig;
NvBool bOverrideComputePeerMode;
NvU32 phase;
NvU32 linkConnection[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PROCESS_FORCED_CONFIGS (0x20803034U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PROCESS_FORCED_CONFIGS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS
*
* Sync the NVLink lane shutdown properties with GSP-RM
*
* [In] bLaneShutdownOnUnload
* Whether nvlink shutdown should be triggered on driver unload
*/
#define NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID (0x35U)
typedef struct NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS {
NvBool bLaneShutdownOnUnload;
} NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS (0x20803035U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_SYNC_NVLINK_SHUTDOWN_PROPS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS
*
* Enable ATS functionality related to NVLink sysmem if hardware support is available
*
* [In] notUsed
*/
#define NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID (0x36U)
typedef struct NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS {
NvU32 notUsed;
} NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_ENABLE_SYSMEM_NVLINK_ATS (0x20803036U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_ENABLE_SYSMEM_NVLINK_ATS_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK
*
* Get the mask of Nvlink links connected to system
*
* [Out] sysmemLinkMask
* Mask of Nvlink links connected to system
*/
#define NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID (0x37U)
typedef struct NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS {
NvU32 sysmemLinkMask;
} NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK (0x20803037U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_HSHUB_GET_SYSMEM_NVLINK_MASK_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_GET_SET_NVSWITCH_FLA_ADDR
*
@@ -2707,12 +2197,12 @@ typedef struct NV2080_CTRL_NVLINK_GET_SET_NVSWITCH_FLA_ADDR_PARAMS {
#define NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS_MESSAGE_ID (0x39U)
typedef struct NV2080_CTRL_NVLINK_SYNC_LINK_MASKS_AND_VBIOS_INFO_PARAMS {
NvU32 discoveredLinks;
NV_DECLARE_ALIGNED(NvU64 discoveredLinks, 8);
NvU32 connectedLinksMask;
NvU32 bridgeSensableLinks;
NV_DECLARE_ALIGNED(NvU64 bridgeSensableLinks, 8);
NvU32 bridgedLinks;
NvU32 initDisabledLinksMask;
NvU32 vbiosDisabledLinkMask;
NV_DECLARE_ALIGNED(NvU64 vbiosDisabledLinkMask, 8);
NvU32 initializedLinks;
NvBool bEnableTrainingAtLoad;
NvBool bEnableSafeModeAtLoad;
@@ -3340,7 +2830,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_SLTP_PARAMS {
typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PGUID_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvU8 plane_ind;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
@@ -3362,7 +2851,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPRT_PARAMS {
NvBool sw;
NvBool dm_ig;
NvBool p;
NvBool tun_ovr;
NvBool s;
NvBool e;
NvU8 modulation;
@@ -3546,7 +3034,6 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS {
NvU8 critical_inactive_time;
NvU8 critical_active_time;
NvBool cc;
NvU16 queue_depth_th;
} NV2080_CTRL_NVLINK_PRM_ACCESS_MPSCR_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_PRM_ACCESS_MTSR (0x2080307dU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_PRM_ACCESS_MTSR_PARAMS_MESSAGE_ID" */
@@ -3745,6 +3232,127 @@ typedef struct NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS {
NvU8 rbmMode;
} NV2080_CTRL_NVLINK_GET_BW_MODE_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO
*
* localDeviceInfo
* NVLINK-relevant information about the device
*/
#define NV2080_CTRL_CMD_NVLINK_GET_LOCAL_DEVICE_INFO (0x20803088U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS_MESSAGE_ID (0x88U)
typedef struct NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS {
NV_DECLARE_ALIGNED(NV2080_CTRL_NVLINK_DEVICE_INFO localDeviceInfo, 8);
} NV2080_CTRL_NVLINK_GET_LOCAL_DEVICE_INFO_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR
*
* This command is used to inject NVL5 ERROR_INJECT_V2 commands
*
* [out]
* Error Types to be injected
*
* Possible status values returned are:
* NV_OK
* If the Error is injected successfully
* NV_ERR_NOT_SUPPORTED
* If NVLINK is not supported on the chip
* NV_ERR_INVALID_ARGUMENT
* If the link is not enabled on the GPU
* NV_ERR_INVALID_STATE
* If the link is in an invalid state
*/
#define NV2080_CTRL_CMD_NVLINK_INJECT_SW_ERROR (0x20803089U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY {
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_NONFATAL = 0,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_APP_FATAL = 1,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_FATAL = 2,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_DEGRADATION = 3,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_WATCHDOG_TIMEOUT = 4,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MVB_NON_FATAL = 5,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_SAW_MSE = 6,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_NON_FATAL = 7,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_FATAL = 8,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_RLW_PRIV_ERR = 9,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_NON_FATAL = 10,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TLW_FATAL = 11,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_TREX_NON_FATAL = 12,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_NON_FATAL = 13,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_GIN_NETIR_FATAL = 14,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_NON_FATAL = 15,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_SAW_MVB_FATAL = 16,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_NON_FATAL = 17,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_RLW_FATAL = 18,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_NON_FATAL = 19,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MSE_ECC_INJECT_TLW_FATAL = 20,
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY_MAX = 21,
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY;
#define NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS_MESSAGE_ID (0x89U)
typedef struct NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_INJECT_SW_ERROR_SEVERITY severity;
} NV2080_CTRL_NVLINK_INJECT_SW_ERROR_PARAMS;
/*
* NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY
*
* Signal to GSP that lazy error recovery can proceed.
*/
#define NV2080_CTRL_CMD_NVLINK_POST_LAZY_ERROR_RECOVERY (0x2080308aU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | 0x8A" */
/*
* NV2080_CTRL_CMD_SET_NVLINK_CONFIGURE_L1_TOGGLE
*
* This command configures the nvlink L1 toggle pattern
*
* Commands returns SUCCESS only when it successfully sets value of all
* parameter in the list.
*
* Possible status return values are:
* NV_OK
*
* Reference:
*
*/
#define NV2080_CTRL_CMD_NVLINK_CONFIGURE_L1_TOGGLE (0x2080308eU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID" */
typedef enum NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE {
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DISABLED = 0,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_TRIGGER_ONCE = 1,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_EXITED = 2,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_FORCE_ENTERED = 3,
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE_DUTY_CYCLE = 4,
} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE;
typedef struct NV2080_CTRL_NVLINK_L1_FORCE_CONFIG {
NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_MODE mode;
NvU8 toggleActiveTime;
NvU8 toggleInactiveTime;
NvBool bTrigger;
} NV2080_CTRL_NVLINK_L1_FORCE_CONFIG;
#define NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8EU)
typedef struct NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config;
} NV2080_CTRL_NVLINK_CONFIGURE_L1_TOGGLE_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_GET_L1_TOGGLE (0x2080308fU) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS_MESSAGE_ID (0x8FU)
typedef struct NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS {
NvU32 linkMask;
NV2080_CTRL_NVLINK_L1_FORCE_CONFIG config[NV2080_CTRL_NVLINK_MAX_LINKS];
} NV2080_CTRL_NVLINK_GET_L1_TOGGLE_PARAMS;
/* _ctrl2080nvlink_h_ */

20
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080perf.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2005-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2005-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -471,6 +471,12 @@ typedef struct NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE {
* the sample was taken. If no process is active then NULL will be returned.
*/
char subProcessName[NV_SUBPROC_NAME_MAX_LENGTH];
/*!
* PID struct pointer of the process that was active on the engine when the
* the sample was taken. If no process is active then NULL pointer
* will be returned
*/
NV_DECLARE_ALIGNED(NvU64 pOsPidInfo, 8);
} NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE;
/*!
@@ -484,27 +490,27 @@ typedef struct NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE {
/*!
* FB bandwidth utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE fb, 8);
/*!
* GR utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE gr, 8);
/*!
* NV ENCODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvenc, 8);
/*!
* NV DECODER utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvdec, 8);
/*!
* NV JPEG utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvjpg, 8);
/*!
* NV OFA utilization sample.
*/
NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa;
NV_DECLARE_ALIGNED(NV2080_CTRL_PERF_GPUMON_ENGINE_UTIL_SAMPLE nvofa, 8);
} NV2080_CTRL_PERF_GPUMON_PERFMON_UTIL_SAMPLE;
/*!

18
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080vgpumgrinternal.h
View File

@@ -458,4 +458,22 @@ typedef struct NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS {
NvBool bFlrDisabled;
} NV2080_CTRL_VGPU_MGR_GET_FRAME_RATE_LIMITER_STATUS_PARAMS;
/*
* NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE
*
* This command will set heterogenous mode in GSP RM
*
* bHeterogeneousMode
* Mode of heterogeneous
*
* Possible status values returned are:
* NV_OK
*/
#define NV2080_CTRL_CMD_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE (0x2080400e) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_VGPU_MGR_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID" */
#define NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS_MESSAGE_ID (0xEU)
typedef struct NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS {
NvBool bHeterogeneousMode;
} NV2080_CTRL_VGPU_MGR_INTERNAL_SET_VGPU_HETEROGENEOUS_MODE_PARAMS;
/* _ctrl2080vgpumgrinternal_h_ */