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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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1
src/common/unix/common/inc/nv_amodel_enum.h
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@@ -38,6 +38,7 @@ typedef enum _NVAModelConfig {
NV_AMODEL_ADA,
NV_AMODEL_HOPPER,
NV_AMODEL_BLACKWELL,
NV_AMODEL_GB20X,
} NVAModelConfig;
#endif /* __NV_AMODEL_ENUM_H__ */

8
src/common/unix/common/inc/nv_mode_timings.h
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@@ -76,7 +76,7 @@ enum NvYuv420Mode {
typedef struct _NvModeTimings {
NvU32 RRx1k;
NvU32 pixelClockHz; /* in Hz units */
NvU64 pixelClockHz NV_ALIGN_BYTES(8); /* in Hz units */
NvU16 hVisible;
NvU16 hSyncStart;
NvU16 hSyncEnd;
@@ -149,14 +149,14 @@ static inline NvBool NvModeTimingsMatch(const NvModeTimings *pA,
*
* We do +500 before /1000 in order to round, rather than truncate.
*/
static inline NvU32 HzToKHz(NvU32 hz)
static inline NvU32 HzToKHz(NvU64 hz)
{
return (hz + 500) / 1000;
}
static inline NvU32 KHzToHz(NvU32 kHz)
static inline NvU64 KHzToHz(NvU32 kHz)
{
return kHz * 1000;
return kHz * (NvU64)1000;
}

53
src/common/unix/common/utils/interface/nv_smg.h Normal file
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@@ -0,0 +1,53 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef __NV_SMG_H__
#define __NV_SMG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "nvtypes.h"
/*
* The simplest required abstraction for accessing RM independent of the
* calling component which may be a kernel module or userspace driver.
*/
typedef NvU32 (*NVSubdevSMGRMControl) (void *ctx, NvU32 object, NvU32 cmd, void *params, NvU32 paramsSize);
typedef NvU32 (*NVSubdevSMGRMAlloc) (void *ctx, NvU32 parent, NvU32 object, NvU32 cls, void *allocParams);
typedef NvU32 (*NVSubdevSMGRMFree) (void *ctx, NvU32 parent, NvU32 object);
NvBool NVSubdevSMGSetPartition(void *ctx,
NvU32 subdevHandle,
const char *computeInstUuid,
NvU32 gpuInstSubscriptionHdl,
NvU32 computeInstSubscriptionHdl,
NVSubdevSMGRMControl rmControl,
NVSubdevSMGRMAlloc rmAlloc,
NVSubdevSMGRMFree rmFree);
#ifdef __cplusplus
}
#endif
#endif /* __NV_SMG_H__ */

271
src/common/unix/common/utils/nv_smg.c Normal file
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@@ -0,0 +1,271 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#if defined(NV_SMG_IN_NVKMS)
# include "nvkms-utils.h"
#else
# include <stdlib.h>
# include <string.h>
#endif
#include "nvmisc.h"
#include "nv_smg.h"
#include "class/clc637.h"
#include "class/clc638.h"
#include <ctrl/ctrl2080/ctrl2080gpu.h>
#include <ctrl/ctrlc637.h>
#include <ctrl/ctrlc638.h>
/*
* Set up SMG for the given subdevice. Handles partition allocation and
* selection. Returns true if this subdevice is equipped to do graphics.
* That is, either when not in MIG-mode at all, or when MIG-mode is enabled
* and we were able to successfully set up an SMG partition for doing
* graphics on this subdevice. Returns false otherwise when any kind of
* unrecoverable error condition that means broken graphics is encountered.
*/
NvBool NVSubdevSMGSetPartition(void *ctx,
NvU32 subdevHandle,
const char *computeInstUuid,
NvU32 gpuInstSubscriptionHdl,
NvU32 computeInstSubscriptionHdl,
NVSubdevSMGRMControl rmControl,
NVSubdevSMGRMAlloc rmAlloc,
NVSubdevSMGRMFree rmFree)
{
/*
* These RM parameters can be huge: allocate them from the heap to keep
* kernel stack usage low. For userspace, allocate on stack.
*/
struct workspace {
NV2080_CTRL_GPU_GET_INFO_V2_PARAMS gpuInfoParams;
NV2080_CTRL_GPU_GET_PARTITIONS_PARAMS getPartParams;
NVC637_ALLOCATION_PARAMETERS allocParams;
NVC637_CTRL_EXEC_PARTITIONS_GET_PARAMS getExecPartParams;
NVC638_ALLOCATION_PARAMETERS smgExecAllocParams;
NVC638_CTRL_GET_UUID_PARAMS getUuidParams;
} *ws;
NvU32 res;
NvU32 smcMode;
int i;
int j;
#if defined(NV_SMG_IN_NVKMS)
/* Allocate workspace from heap. */
ws = (struct workspace *)nvAlloc(sizeof(*ws));
if (!ws) {
return NV_FALSE;
}
nvkms_memset(ws, 0, sizeof(*ws));
#else
/* Allocate workspace from stack. */
struct workspace _ws;
ws = &_ws;
memset(ws, 0, sizeof(*ws));
#endif
/*
* Before anything, check explicitly for MIG mode
*/
ws->gpuInfoParams.gpuInfoListSize = 1;
ws->gpuInfoParams.gpuInfoList[0].index = NV2080_CTRL_GPU_INFO_INDEX_GPU_SMC_MODE;
res = rmControl(ctx,
subdevHandle,
NV2080_CTRL_CMD_GPU_GET_INFO_V2,
&ws->gpuInfoParams,
sizeof(ws->gpuInfoParams));
if (res != NV_OK) {
return NV_FALSE;
}
#if !defined(NV_SMG_IN_NVKMS)
/*
* NOTE: The simplest possible support for N-way MIG for a transitional
* period. This handles all SMG subscription calls originating from
* userspace by checking for an environment override for the default MIG
* device UUID. This is a measure that extends the way 1-way SMG works
* to enable further testing and sharing between teams. A complete
* solution of how to negotiate MIG UUIDs between display server and
* clients is a major step that requires larger design considerations
* than just few patches.
*/
if (computeInstUuid == NULL) {
const char *uuid = getenv("MIG_DEVICE_UUID");
if (uuid && uuid[0]) {
computeInstUuid = uuid;
}
}
#endif
/*
* If we're not in MIG mode then just return true to indicate we're able
* to do graphics. No MIG mode, no subscriptions.
*/
smcMode = ws->gpuInfoParams.gpuInfoList[0].data;
if (smcMode != NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_ENABLED &&
smcMode != NV2080_CTRL_GPU_INFO_GPU_SMC_MODE_DISABLE_PENDING) {
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_TRUE;
}
/*
* Query available GPU instances (GPU/graphics partitions) on the given
* subdevice.
*/
ws->getPartParams.bGetAllPartitionInfo = NV_TRUE;
res = rmControl(ctx,
subdevHandle,
NV2080_CTRL_CMD_GPU_GET_PARTITIONS,
&ws->getPartParams,
sizeof(ws->getPartParams));
if (res != NV_OK || ws->getPartParams.validPartitionCount == 0) {
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_FALSE;
}
/* Look for graphics partitions only. */
for (i = 0; i < ws->getPartParams.validPartitionCount; i++) {
const NV2080_CTRL_GPU_GET_PARTITION_INFO *pinfo =
&ws->getPartParams.queryPartitionInfo[i];
const NvU32 gfxSize = DRF_VAL(
2080_CTRL_GPU, _PARTITION_FLAG, _GFX_SIZE, pinfo->partitionFlag);
if (gfxSize == NV2080_CTRL_GPU_PARTITION_FLAG_GFX_SIZE_NONE) {
continue;
}
/*
* OK, an SMG partition was found: subscribe to it in order to be
* able to investigate further.
*/
ws->allocParams.swizzId = pinfo->swizzId;
res = rmAlloc(ctx,
subdevHandle,
gpuInstSubscriptionHdl,
AMPERE_SMC_PARTITION_REF,
&ws->allocParams);
if (res != NV_OK) {
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_FALSE;
}
/*
* Next, find out about compute instances (exec partitions) under
* the current graphics partition.
*/
res = rmControl(ctx,
gpuInstSubscriptionHdl,
NVC637_CTRL_CMD_EXEC_PARTITIONS_GET,
&ws->getExecPartParams,
sizeof(ws->getExecPartParams));
if (res != NV_OK) {
rmFree(ctx, subdevHandle, gpuInstSubscriptionHdl);
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_FALSE;
}
/*
* Loop through all compute instances (exec partitions) and try
* subscribing to each one in turn to determine a potential match.
*/
for (j = 0; j < ws->getExecPartParams.execPartCount; j++) {
ws->smgExecAllocParams.execPartitionId =
ws->getExecPartParams.execPartId[j];
res = rmAlloc(ctx,
gpuInstSubscriptionHdl,
computeInstSubscriptionHdl,
AMPERE_SMC_EXEC_PARTITION_REF,
&ws->smgExecAllocParams);
if (res == NV_OK) {
/*
* For 1-way SMG the requested compute instance UUID should
* be null. In this case we just pick the first available
* compute instance. For N-way SMG the UUID can vary based
* on what the application wants and we want to find the
* first matching gpu instance.
*/
NvBool matchingInstance = (computeInstUuid == NULL);
if (computeInstUuid != NULL) {
res = rmControl(ctx,
computeInstSubscriptionHdl,
NVC638_CTRL_CMD_GET_UUID,
&ws->getUuidParams,
sizeof(ws->getUuidParams));
if (res == NV_OK) {
#if defined(NV_SMG_IN_NVKMS)
matchingInstance = (nvkms_strcmp
(computeInstUuid, ws->getUuidParams.uuidStr) == 0);
#else
matchingInstance = (strcmp
(computeInstUuid, ws->getUuidParams.uuidStr) == 0);
#endif
}
}
/*
* Ok, found a matching compute instance. The current GPU
* (GPU partition) instance gets thus implicitly selected as
* we return and leave the subcription objects attached to
* the subdevice.
*/
if (matchingInstance) {
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_TRUE;
}
}
rmFree(ctx, gpuInstSubscriptionHdl, computeInstSubscriptionHdl);
}
rmFree(ctx, subdevHandle, gpuInstSubscriptionHdl);
}
#if defined(NV_SMG_IN_NVKMS)
nvFree(ws);
#endif
return NV_FALSE;
}

1
src/common/unix/nvidia-3d/interface/nvidia-3d-types.h
View File

@@ -363,6 +363,7 @@ enum Nv3dShaderArch {
NV3D_SHADER_ARCH_AMPERE,
NV3D_SHADER_ARCH_HOPPER,
NV3D_SHADER_ARCH_BLACKWELL,
NV3D_SHADER_ARCH_GB20X,
NV3D_SHADER_ARCH_COUNT,
};

6
src/common/unix/nvidia-3d/src/nvidia-3d-init.c
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@@ -38,6 +38,7 @@
#include "nvidia-push-init.h" // nvPushGetSupportedClassIndex()
#include "nvidia-push-utils.h" // nvPushIsAmodel()
#include <class/clce97.h> // BLACKWELL_B
#include <class/clcd97.h> // BLACKWELL_A
#include <class/clcb97.h> // HOPPER_A
#include <class/clc997.h> // ADA_A
@@ -60,6 +61,7 @@
#include "g_ampere_shader_info.h"
#include "g_hopper_shader_info.h"
#include "g_blackwell_shader_info.h"
#include "g_gb20x_shader_info.h"
#define _NV3D_CHANNEL_PROGRAMS_ENTRY(_archLower, _archCamel, _archUpper) \
[NV3D_SHADER_ARCH_ ## _archUpper ] = { \
@@ -95,6 +97,7 @@ static Nv3dChannelProgramsRec PickProgramsRec(
_NV3D_CHANNEL_PROGRAMS_ENTRY(ampere, Ampere, AMPERE),
_NV3D_CHANNEL_PROGRAMS_ENTRY(hopper, Hopper, HOPPER),
_NV3D_CHANNEL_PROGRAMS_ENTRY(blackwell, Blackwell, BLACKWELL),
_NV3D_CHANNEL_PROGRAMS_ENTRY(gb20x, GB20x, GB20X),
};
return programsTable[p3dDevice->shaderArch];
@@ -201,6 +204,7 @@ static NvU32 GetSmVersion(
[NV_AMODEL_ADA] = NV2080_CTRL_GR_INFO_SM_VERSION_8_9,
[NV_AMODEL_HOPPER] = NV2080_CTRL_GR_INFO_SM_VERSION_9_0,
[NV_AMODEL_BLACKWELL] = NV2080_CTRL_GR_INFO_SM_VERSION_10_0,
[NV_AMODEL_GB20X] = NV2080_CTRL_GR_INFO_SM_VERSION_10_4,
};
if (pPushDevice->amodelConfig >= ARRAY_LEN(table)) {
@@ -299,6 +303,7 @@ static NvBool GetSpaVersion(
/* Blackwell */
{ NV2080_CTRL_GR_INFO_SM_VERSION_10_0, { 10,0 } },
{ NV2080_CTRL_GR_INFO_SM_VERSION_10_1, { 10,1 } },
{ NV2080_CTRL_GR_INFO_SM_VERSION_10_4, { 10,4 } },
};
const NvU32 smVersion = GetSmVersion(pPushDevice);
@@ -406,6 +411,7 @@ NvBool nv3dAllocDevice(
* classNumber | | | | | |
* | | | | | | |
*/
ENTRY(BLACKWELL_B,GB20X, GB20X, 0, 0, 32768, Hopper),
ENTRY(BLACKWELL_A,BLACKWELL, BLACKWELL, 0, 0, 32768, Hopper),
ENTRY(HOPPER_A, HOPPER, HOPPER, 0, 0, 32768, Hopper),
ENTRY(ADA_A, AMPERE, ADA, 0, 0, 32768, Ampere),

6
src/common/unix/nvidia-push/src/nvidia-push-init.c
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@@ -47,6 +47,7 @@
#include "class/clc56f.h" // AMPERE_CHANNEL_GPFIFO_A
#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A
#include "class/clc96f.h" // BLACKWELL_CHANNEL_GPFIFO_A
#include "class/clca6f.h" // BLACKWELL_CHANNEL_GPFIFO_B
#include "class/clc361.h" // VOLTA_USERMODE_A
#include "class/clc661.h" // HOPPER_USERMODE_A
@@ -605,6 +606,11 @@ static NvBool GetChannelClassAndUserDSize(
NvPushSupportedClass base;
size_t gpFifoSize;
} gpFifoDmaClasses[] = {
{
{ BLACKWELL_CHANNEL_GPFIFO_B,
NV_AMODEL_GB20X },
sizeof(BlackwellBControlGPFifo)
},
{
{ BLACKWELL_CHANNEL_GPFIFO_A,
NV_AMODEL_BLACKWELL },

4
src/common/unix/nvidia-push/src/nvidia-push.c
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@@ -46,6 +46,7 @@
#include "class/clc86f.h" // HOPPER_CHANNEL_GPFIFO_A
#include "class/clc361.h" // VOLTA_USERMODE_A
#include "class/clc96f.h" // BLACKWELL_CHANNEL_GPFIFO_A
#include "class/clca6f.h" // BLACKWELL_CHANNEL_GPFIFO_B
#include "ctrl/ctrl906f.h" // NV906F_CTRL_GET_CLASS_ENGINEID
/*
@@ -1098,6 +1099,9 @@ NvBool __nvPushGetHal(
NvPushHal *pHal)
{
switch (channelClass) {
case BLACKWELL_CHANNEL_GPFIFO_B:
// backwards compatible
// fall through
case BLACKWELL_CHANNEL_GPFIFO_A:
// backwards compatible with Hopper
// fall through

2
src/common/unix/xzminidec/interface/xz.h
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@@ -2,7 +2,7 @@
* XZ decompressor
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
* Igor Pavlov <https://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.

2
src/common/unix/xzminidec/src/xz_crc32.c
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@@ -2,7 +2,7 @@
* CRC32 using the polynomial from IEEE-802.3
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
* Igor Pavlov <https://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.

2
src/common/unix/xzminidec/src/xz_dec_bcj.c
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@@ -2,7 +2,7 @@
* Branch/Call/Jump (BCJ) filter decoders
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
* Igor Pavlov <https://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.

2
src/common/unix/xzminidec/src/xz_dec_lzma2.c
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@@ -2,7 +2,7 @@
* LZMA2 decoder
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
* Igor Pavlov <https://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.

2
src/common/unix/xzminidec/src/xz_lzma2.h
View File

@@ -2,7 +2,7 @@
* LZMA2 definitions
*
* Authors: Lasse Collin <lasse.collin@tukaani.org>
* Igor Pavlov <http://7-zip.org/>
* Igor Pavlov <https://7-zip.org/>
*
* This file has been put into the public domain.
* You can do whatever you want with this file.

2
src/common/unix/xzminidec/src/xz_stream.h
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@@ -19,7 +19,7 @@
/*
* See the .xz file format specification at
* http://tukaani.org/xz/xz-file-format.txt
* https://tukaani.org/xz/xz-file-format.txt
* to understand the container format.
*/