mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-27 18:34:00 +00:00
570.86.15
This commit is contained in:
Bernhard Stoeckner
@@ -97,18 +97,22 @@ typedef NV_STATUS RpcDmaControl(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32
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typedef NV_STATUS RpcCtrlDbgClearSingleSmErrorState(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcUnsetPageDirectory(POBJGPU, POBJRPC, NvHandle, NvHandle,
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NV0080_CTRL_DMA_UNSET_PAGE_DIRECTORY_PARAMS*);
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typedef NV_STATUS RpcCtrlReserveCcuProf(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcGetGspStaticInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcSaveHibernationData(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcDupObject(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvHandle, NvU32);
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typedef NV_STATUS RpcGspSetSystemInfo(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlPmAreaPcSampler(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*);
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typedef NV_STATUS RpcCtrlSubdeviceGetLibosHeapStats(POBJGPU, POBJRPC, void*);
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typedef NV_STATUS RpcCtrlDbgSetExceptionMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetZbcStencilClear(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlVaspaceCopyServerReservedPdes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGrCtxswPreemptionBind(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlAllocPmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReleaseHes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReserveHwpmLegacy(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSubdeviceGetVgpuHeapStats(POBJGPU, POBJRPC, void*);
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typedef NV_STATUS RpcCtrlInternalQuiescePmaChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPerfRatedTdpGetStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlBusSetP2pMapping(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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@@ -146,6 +150,7 @@ typedef NV_STATUS RpcSwitchToVga(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlResetChannel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpfifoSchedule(POBJGPU, POBJRPC, NvHandle, NvHandle, NvU32, void*);
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typedef NV_STATUS RpcSetRegistry(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlDbgSetModeMmuGccDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGetNvlinkStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcGetStaticData(POBJGPU, POBJRPC);
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typedef NV_STATUS RpcCtrlGrGetTpcPartitionMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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@@ -154,8 +159,9 @@ typedef NV_STATUS RpcCtrlCmdInternalControlGspTrace(POBJGPU, POBJRPC, NV208
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typedef NV_STATUS RpcSetSurfaceProperties(POBJGPU, POBJRPC, NvHandle,
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NVA080_CTRL_VGPU_DISPLAY_SET_SURFACE_PROPERTIES*,
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NvBool);
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typedef NV_STATUS RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReleaseCcuProf(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlTimerSetGrTickFreq(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcAllocEvent(POBJGPU, POBJRPC, NvHandle, NvHandle, NvHandle,
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NvHandle, NvHandle, NvU32, NvU32);
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typedef NV_STATUS RpcCtrlGrPcSamplingMode(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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@@ -201,7 +207,9 @@ typedef NV_STATUS RpcCtrlDbgExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle
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typedef NV_STATUS RpcCtrlFreePmaStream(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlSetTsgInterleaveLevel(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlMasterGetVirtualFunctionErrorContIntrMask(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlReserveHes(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcLog(POBJGPU, POBJRPC, const char*, NvU32);
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typedef NV_STATUS RpcCtrlDbgGetModeMmuGccDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlExecPartitionsDelete(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlPerfBoost(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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typedef NV_STATUS RpcCtrlDbgSetModeMmuDebug(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
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@@ -251,17 +259,21 @@ typedef struct RPC_HAL_IFACES {
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RpcDmaControl *rpcDmaControl; /* DMA_CONTROL */
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RpcCtrlDbgClearSingleSmErrorState *rpcCtrlDbgClearSingleSmErrorState; /* CTRL_DBG_CLEAR_SINGLE_SM_ERROR_STATE */
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RpcUnsetPageDirectory *rpcUnsetPageDirectory; /* UNSET_PAGE_DIRECTORY */
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RpcCtrlReserveCcuProf *rpcCtrlReserveCcuProf; /* RESERVE_CCU_PROF */
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RpcGetGspStaticInfo *rpcGetGspStaticInfo; /* Get static info from GSP RM. */
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RpcSaveHibernationData *rpcSaveHibernationData; /* SAVE_HIBERNATION_DATA */
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RpcDupObject *rpcDupObject; /* DUP_OBJECT */
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RpcGspSetSystemInfo *rpcGspSetSystemInfo; /* Tells GSP-RM about the overall system environment */
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RpcCtrlPmAreaPcSampler *rpcCtrlPmAreaPcSampler; /* CTRL_PM_AREA_PC_SAMPLER */
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RpcCtrlSubdeviceGetLibosHeapStats *rpcCtrlSubdeviceGetLibosHeapStats; /* CTRL_SUBDEVICE_GET_LIBOS_HEAP_STATS */
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RpcCtrlDbgSetExceptionMask *rpcCtrlDbgSetExceptionMask; /* CTRL_DBG_SET_EXCEPTION_MASK */
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RpcCtrlSetZbcStencilClear *rpcCtrlSetZbcStencilClear; /* CTRL_SET_ZBC_STENCIL_CLEAR */
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RpcCtrlVaspaceCopyServerReservedPdes *rpcCtrlVaspaceCopyServerReservedPdes; /* CTRL_VASPACE_COPY_SERVER_RESERVED_PDES */
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RpcCtrlGrCtxswPreemptionBind *rpcCtrlGrCtxswPreemptionBind; /* CTRL_GR_CTXSW_PREEMPTION_BIND */
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RpcCtrlAllocPmaStream *rpcCtrlAllocPmaStream; /* CTRL_ALLOC_PMA_STREAM */
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RpcCtrlReleaseHes *rpcCtrlReleaseHes; /* RELEASE_HES */
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RpcCtrlReserveHwpmLegacy *rpcCtrlReserveHwpmLegacy; /* CTRL_RESERVE_HWPM_LEGACY */
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RpcCtrlSubdeviceGetVgpuHeapStats *rpcCtrlSubdeviceGetVgpuHeapStats; /* CTRL_SUBDEVICE_GET_VGPU_HEAP_STATS */
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RpcCtrlInternalQuiescePmaChannel *rpcCtrlInternalQuiescePmaChannel; /* CTRL_INTERNAL_QUIESCE_PMA_CHANNEL */
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RpcCtrlPerfRatedTdpGetStatus *rpcCtrlPerfRatedTdpGetStatus; /* CTRL_PERF_RATED_TDP_GET_STATUS */
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RpcCtrlBusSetP2pMapping *rpcCtrlBusSetP2pMapping; /* CTRL_BUS_SET_P2P_MAPPING */
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@@ -297,14 +309,16 @@ typedef struct RPC_HAL_IFACES {
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RpcCtrlResetChannel *rpcCtrlResetChannel; /* CTRL_RESET_CHANNEL */
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RpcCtrlGpfifoSchedule *rpcCtrlGpfifoSchedule; /* CTRL_GPFIFO_SCHEDULE */
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RpcSetRegistry *rpcSetRegistry; /* GSP Init Set registry values */
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RpcCtrlDbgSetModeMmuGccDebug *rpcCtrlDbgSetModeMmuGccDebug; /* CTRL_DBG_SET_MODE_MMU_GCC_DEBUG */
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RpcCtrlGetNvlinkStatus *rpcCtrlGetNvlinkStatus; /* CTRL_NVLINK_GET_NVLINK_STATUS */
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RpcGetStaticData *rpcGetStaticData; /* GET_STATIC_DATA published for OpenRM */
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RpcCtrlGrGetTpcPartitionMode *rpcCtrlGrGetTpcPartitionMode; /* CTRL_GR_GET_TPC_PARTITION_MODE */
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RpcCtrlStopChannel *rpcCtrlStopChannel; /* CTRL_STOP_CHANNEL */
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RpcCtrlCmdInternalControlGspTrace *rpcCtrlCmdInternalControlGspTrace; /* CTRL_CMD_INTERNAL_CONTROL_GSP_TRACE */
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RpcSetSurfaceProperties *rpcSetSurfaceProperties; /* SET_SURFACE_PROPERTIES */
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RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex *rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex; /* CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX */
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RpcCtrlReleaseCcuProf *rpcCtrlReleaseCcuProf; /* RELEASE_CCU_PROF */
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RpcCtrlTimerSetGrTickFreq *rpcCtrlTimerSetGrTickFreq; /* CTRL_TIMER_SET_GR_TICK_FREQ */
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RpcCtrlGpfifoSetWorkSubmitTokenNotifIndex *rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex; /* CTRL_GPFIFO_SET_WORK_SUBMIT_TOKEN_NOTIF_INDEX */
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RpcAllocEvent *rpcAllocEvent; /* ALLOC_EVENT */
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RpcCtrlGrPcSamplingMode *rpcCtrlGrPcSamplingMode; /* CTRL_GR_PC_SAMPLING_MODE */
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RpcCtrlMcServiceInterrupts *rpcCtrlMcServiceInterrupts; /* CTRL_MC_SERVICE_INTERRUPTS */
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@@ -344,7 +358,9 @@ typedef struct RPC_HAL_IFACES {
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RpcCtrlFreePmaStream *rpcCtrlFreePmaStream; /* CTRL_FREE_PMA_STREAM */
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RpcCtrlSetTsgInterleaveLevel *rpcCtrlSetTsgInterleaveLevel; /* CTRL_SET_TSG_INTERLEAVE_LEVEL */
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RpcCtrlMasterGetVirtualFunctionErrorContIntrMask *rpcCtrlMasterGetVirtualFunctionErrorContIntrMask; /* CTRL_MASTER_GET_VIRTUAL_FUNCTION_ERROR_CONT_INTR_MASK */
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RpcCtrlReserveHes *rpcCtrlReserveHes; /* RESERVE_HES */
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RpcLog *rpcLog; /* LOG */
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RpcCtrlDbgGetModeMmuGccDebug *rpcCtrlDbgGetModeMmuGccDebug; /* CTRL_DBG_GET_MODE_MMU_GCC_DEBUG */
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RpcCtrlExecPartitionsDelete *rpcCtrlExecPartitionsDelete; /* CTRL_EXEC_PARTITIONS_DELETE */
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RpcCtrlPerfBoost *rpcCtrlPerfBoost; /* CTRL_PERF_BOOST */
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RpcCtrlDbgSetModeMmuDebug *rpcCtrlDbgSetModeMmuDebug; /* CTRL_DBG_SET_MODE_MMU_DEBUG */
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@@ -422,6 +438,8 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcCtrlDbgClearSingleSmErrorState(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcUnsetPageDirectory_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcUnsetPageDirectory(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlReserveCcuProf_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlReserveCcuProf(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcGetGspStaticInfo_HAL(_pGpu, _pRpc) \
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(_pRpc)->_hal.rpcGetGspStaticInfo(_pGpu, _pRpc)
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#define rpcSaveHibernationData_HAL(_pGpu, _pRpc) \
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@@ -432,6 +450,8 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcGspSetSystemInfo(_pGpu, _pRpc)
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#define rpcCtrlPmAreaPcSampler_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3) \
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(_pRpc)->_hal.rpcCtrlPmAreaPcSampler(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3)
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#define rpcCtrlSubdeviceGetLibosHeapStats_HAL(_pGpu, _pRpc, _pArg0) \
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(_pRpc)->_hal.rpcCtrlSubdeviceGetLibosHeapStats(_pGpu, _pRpc, _pArg0)
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#define rpcCtrlDbgSetExceptionMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlDbgSetExceptionMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlSetZbcStencilClear_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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@@ -442,8 +462,12 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcCtrlGrCtxswPreemptionBind(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlAllocPmaStream_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlAllocPmaStream(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlReleaseHes_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlReleaseHes(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlReserveHwpmLegacy_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlReserveHwpmLegacy(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlSubdeviceGetVgpuHeapStats_HAL(_pGpu, _pRpc, _pArg0) \
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(_pRpc)->_hal.rpcCtrlSubdeviceGetVgpuHeapStats(_pGpu, _pRpc, _pArg0)
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#define rpcCtrlInternalQuiescePmaChannel_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlInternalQuiescePmaChannel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlPerfRatedTdpGetStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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@@ -514,6 +538,8 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcCtrlGpfifoSchedule(_pGpu, _pRpc, _arg0, _arg1, _arg2, _pArg3)
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#define rpcSetRegistry_HAL(_pGpu, _pRpc) \
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(_pRpc)->_hal.rpcSetRegistry(_pGpu, _pRpc)
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#define rpcCtrlDbgSetModeMmuGccDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlDbgSetModeMmuGccDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlGetNvlinkStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlGetNvlinkStatus(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcGetStaticData_HAL(_pGpu, _pRpc) \
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@@ -526,10 +552,12 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcCtrlCmdInternalControlGspTrace(_pGpu, _pRpc, _pArg0)
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#define rpcSetSurfaceProperties_HAL(_pGpu, _pRpc, _arg0, _pArg1, _arg2) \
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(_pRpc)->_hal.rpcSetSurfaceProperties(_pGpu, _pRpc, _arg0, _pArg1, _arg2)
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#define rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlReleaseCcuProf_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlReleaseCcuProf(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlTimerSetGrTickFreq_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlTimerSetGrTickFreq(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlGpfifoSetWorkSubmitTokenNotifIndex(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcAllocEvent_HAL(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6) \
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(_pRpc)->_hal.rpcAllocEvent(_pGpu, _pRpc, _arg0, _arg1, _arg2, _arg3, _arg4, _arg5, _arg6)
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#define rpcCtrlGrPcSamplingMode_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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@@ -608,8 +636,12 @@ typedef struct RPC_HAL_IFACES {
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(_pRpc)->_hal.rpcCtrlSetTsgInterleaveLevel(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlMasterGetVirtualFunctionErrorContIntrMask_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlMasterGetVirtualFunctionErrorContIntrMask(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlReserveHes_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlReserveHes(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcLog_HAL(_pGpu, _pRpc, _pChar, _arg0) \
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(_pRpc)->_hal.rpcLog(_pGpu, _pRpc, _pChar, _arg0)
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#define rpcCtrlDbgGetModeMmuGccDebug_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlDbgGetModeMmuGccDebug(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlExecPartitionsDelete_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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(_pRpc)->_hal.rpcCtrlExecPartitionsDelete(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
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#define rpcCtrlPerfBoost_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
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