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This commit is contained in:
Bernhard Stoeckner
2025-01-27 19:36:56 +01:00
parent 9d0b0414a5
commit 54d69484da
1166 changed files with 318863 additions and 182687 deletions
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96
src/nvidia/inc/kernel/gpu/conf_compute/conf_compute_keystore.h
View File

@@ -1,96 +0,0 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*/
#ifndef CONF_COMPUTE_KEYSTORE_H
#define CONF_COMPUTE_KEYSTORE_H
#include "nvtypes.h"
#include "nvstatus.h"
#include "cc_drv.h"
#include "kernel/gpu/fifo/kernel_channel.h"
// Named values for ccKeyStoreDeposit()'s slotNumber parameter.
#define KEYSTORE_SLOT_GSP 0
#define KEYSTORE_SLOT_SEC2 1
// LCE index can range from 0 to 7 inclusive.
#define KEYSTORE_SLOT_LCE_UMD(index) (2 + (index) * 3)
#define KEYSTORE_SLOT_LCE_KMD(index) (3 + (index) * 3)
#define KEYSTORE_SLOT_LCE_MGPU(index) (4 + (index) * 3)
/*!
* @brief Initialize the keystore.
*
* @param[in] pGpu Pointer to GPU object.
*
* @return NV_ERR_INVALID_STATE if system is not in Confidential Compute mode.
*/
NV_STATUS
ccKeyStoreInit (OBJGPU *pGpu);
/*!
* @brief Deposits a KMB into a keystore slot.
*
* @param[in] slotNumber Slot number into which the KMB will be deposited.
* @param[in] keyMaterialBundle Pair of key / IV / IV mask tuples. IV will be set to 0 by function.
*
* @return NV_ERR_INVALID_INDEX if slotNumber is illegal, NV_OK otherwise.
*/
NV_STATUS
ccKeyStoreDeposit
(
NvU32 slotNumber,
CC_KMB keyMaterialBundle
);
/*!
* @brief Retrieves a KMB based on the channel. The keystore uses channel
information such as engine type and the associated privilege mode
to determine which KMB to fetch.
* The IV's channel counter for the given direction is pre-incremented.
*
* @param[in] pKernelChannel
* @param[in] rotateOperation Either:
ROTATE_IV_ENCRYPT
ROTATE_IV_DECRYPT
ROTATE_IV_ALL_VALID
* @param[out] keyMaterialBundle The KMB for the given channel.
*
* @return NV_ERR_INSUFFICIENT_RESOURCES if channel counter overflow would occur.
NV_ERR_GENERIC for other errors.
* NV_OK otherwise.
*/
NV_STATUS
ccKeyStoreRetrieveViaChannel
(
KernelChannel *pKernelChannel,
ROTATE_IV_TYPE rotateOperation,
PCC_KMB keyMaterialBundle
);
/*!
* @brief Clears the contents of the keystore.
*/
void
cckeyStoreClear (void);
#endif // CONF_COMPUTE_KEYSTORE_H

129
src/nvidia/inc/kernel/gpu/error_cont.h
View File

@@ -76,11 +76,11 @@ typedef enum _NV_ERROR_CONT_ERR_ID
*/
typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING
{
NvU32 rcErrorCode;
NvBool bGpuResetReqd;
NvBool bGpuDrainAndResetReqd;
NvBool bPrintSmcPartitionInfo;
NvU32 nv2080Notifier;
NvU32 rcErrorCode;
NvBool bGpuResetReqd;
NvBool bGpuDrainAndResetReqd;
NvBool bPrintSmcPartitionInfo;
NvU32 nv2080Notifier;
} NV_ERROR_CONT_SMC_DIS_EN_SETTING;
/*!
@@ -88,9 +88,9 @@ typedef struct _NV_ERROR_CONT_SMC_DIS_EN_SETTING
*/
typedef struct _NV_ERROR_CONT_STATE_TABLE
{
NV_ERROR_CONT_ERR_ID errorCode;
NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled,
// 1: SMC memory partitioning enabled
NV_ERROR_CONT_ERR_ID errorCode;
NV_ERROR_CONT_SMC_DIS_EN_SETTING smcDisEnSetting[2]; // 0: SMC memory partitioning disabled,
// 1: SMC memory partitioning enabled
} NV_ERROR_CONT_STATE_TABLE;
/*!
@@ -117,8 +117,8 @@ typedef struct _NV_ERROR_CONT_LOCATION_DRAM
*/
typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID
{
RM_ENGINE_TYPE rmEngineId;
Device *pDevice;
RM_ENGINE_TYPE rmEngineId;
Device *pDevice;
} NV_ERROR_CONT_LOCATION_ENG_ID;
/*!
@@ -126,11 +126,11 @@ typedef struct _NV_ERROR_CONT_LOCATION_ENG_ID
*/
typedef enum _NV_ERROR_CONT_LOCATION_TYPE
{
NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available
NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location
NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location
NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3, // Engine location
NV_ERROR_CONT_LOCATION_TYPE_VF = 4 // VF location
NV_ERROR_CONT_LOCATION_TYPE_NONE = 0, // No location information available
NV_ERROR_CONT_LOCATION_TYPE_DRAM = 1, // DRAM location
NV_ERROR_CONT_LOCATION_TYPE_LTC = 2, // LTC location
NV_ERROR_CONT_LOCATION_TYPE_ENGINE = 3, // Engine location
NV_ERROR_CONT_LOCATION_TYPE_VF = 4 // VF location
} NV_ERROR_CONT_LOCATION_TYPE;
/*!
@@ -138,10 +138,10 @@ typedef enum _NV_ERROR_CONT_LOCATION_TYPE
*/
typedef union _NV_ERROR_CONT_LOCATION_INFO
{
NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location
NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location
NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location
NvU32 vfGfid; // VF location
NV_ERROR_CONT_LOCATION_DRAM dramLoc; // DRAM location
NV_ERROR_CONT_LOCATION_LTC ltcLoc; // LTC location
NV_ERROR_CONT_LOCATION_ENG_ID engineLoc; // Engine location
NvU32 vfGfid; // VF location
} NV_ERROR_CONT_LOCATION_INFO;
typedef struct _NV_ERROR_CONT_LOCATION
@@ -152,14 +152,15 @@ typedef struct _NV_ERROR_CONT_LOCATION
/* ------------------------ Macros ------------------------------------------ */
#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained"
#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained"
#define NO_XID NV_U32_MAX
#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT
#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64
#define ROBUST_CHANNEL_CONTAINED_ERROR_STR "Contained"
#define ROBUST_CHANNEL_UNCONTAINED_ERROR_STR "Uncontained"
#define NO_XID NV_U32_MAX
#define NO_NV2080_NOTIFIER NV2080_NOTIFIERS_MAXCOUNT
#define NV_ERR_CONT_LOCATION_STRING_SIZE_MAX 64
/*!
* Error Containment error types string
* Error Containment error types string.
* The order of this list must match the NV_ERROR_CONT_ERR_ID enums.
*/
#define NV_ERROR_CONT_ERR_ID_STRING_PUBLIC {"FB DED", \
"DED CBC", \
@@ -185,82 +186,4 @@ typedef struct _NV_ERROR_CONT_LOCATION
"NVJPG", \
"OFA"}
/*!
* Error Containment state table showing policy settings for each error id
*
* Where:
* RC_Recovery_Type:
* Type of RC recovery handling in response to a given error. Possible values:
*
* - NO_RC : No RC Recovery performed. Subsequent 2nd interrupt by engine
* consuming poison will determine the RC Recovery type.
* - RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE : RC Recovery compute channels of only the processes whose
* channels were loaded on halted TSG when _E10_SM_POISON or
* _E12A_CE_POISON_IN_USER_CHANNEL occurs.
* - RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION : RC Recovery compute channels of only specific MIG partition
* as that error can be attributed to a specific MIG partition.
* - RC_ALL_CHANNELS_IN_VF : RC Recovery compute channels of only specific GFID
* as that error can be attributed to a VF.
* - RC_ALL_USER_CHANNELS : RC Recovery ALL user channels on a GPU.
* - RC_ALL_COMPUTE_CHANNELS : RC Recovery ALL compute channels on a GPU that saw this interrupt.
* (If MIG is enabled, then RC Recovery compute channels in all MIG partitions)
* - CE_TSG_RESET : Reset the halted CE Engine. Impacts the CE channels loaded on the TSG when the CE Halted.
* This is used in NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL &
* NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL along with additional
* Compute Channels RC policy (either RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE or
* RC_ALL_COMPUTE_CHANNELS).
*/
#define NV_ERROR_CONT_STATE_TABLE_SETTINGS \
{ \
/* errorCode , rcErrorCode , bGpuResetReqd, bGpuDrainAndResetReqd, bPrintSmcPartitionInfo, nv2080Notifier , Dynamic Page Blacklisting , RC_Recovery_Type */ \
{ NV_ERROR_CONT_ERR_ID_E01_FB_ECC_DED , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , Yes(PMA but not subheap) , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E02_FB_ECC_DED_IN_CBC_STORE , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , Yes(PMA but not subheap) , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E05_LTC_ECC_DSTG , {{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }, \
{NO_XID , NV_FALSE , NV_FALSE , NV_FALSE , NO_NV2080_NOTIFIER /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E06_LTC_UNSUPPORTED_CLIENT_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E07_LTC_ECC_TSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E08_LTC_ECC_RSTG , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_TRUE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS_IN_SPECIFIC_PARTITION */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E09_FBHUB_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E10_SM_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12A_CE_POISON_IN_USER_CHANNEL , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E12B_CE_POISON_IN_KERNEL_CHANNEL , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS + CE_TSG_RESET */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E13_MMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , NO_RC */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E16_GCC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E17_CTXSW_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E20_XALEP_EGRESS_POISON , {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21A_XALEP_INGRESS_CONTAINED_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_ALL_CHANNELS_IN_VF */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E21B_XALEP_INGRESS_UNCONTAINED_POISON, {{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_UNCONTAINED_ERROR, NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E22_PMU_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E23_SEC2_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E24_GSP_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_USER_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E25_FBFALCON_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_TRUE , NV_FALSE , NV_FALSE , NV2080_NOTIFIERS_POISON_ERROR_FATAL /* , No , RC_ALL_COMPUTE_CHANNELS */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E26_NVDEC_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E27_NVJPG_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}}, \
{ NV_ERROR_CONT_ERR_ID_E28_OFA_POISON , {{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }, \
{ROBUST_CHANNEL_CONTAINED_ERROR , NV_FALSE , NV_FALSE , NV_TRUE , NV2080_NOTIFIERS_POISON_ERROR_NON_FATAL /* , No , RC_COMPUTE_CHANNELS_IN_ADDRESS_SPACE */ }}} \
}
/* ------------------------ Function Prototypes ----------------------------- */
#endif // _ERROR_CONT_H_

2
src/nvidia/inc/kernel/gpu/external_device/dac_p2060.h
View File

@@ -247,7 +247,7 @@ NV_STATUS gsyncSetInterlaceMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU3
NV_STATUS gsyncRefSwapBarrier_P2060 (OBJGPU *, PDACEXTERNALDEVICE, REFTYPE, NvBool *);
NV_STATUS gsyncGetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetWatchdog_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);
NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, PDACEXTERNALDEVICE, GSYNCCAPSPARAMS *);
NV_STATUS gsyncGetRevision_P2060 (OBJGPU *, OBJGSYNC *, GSYNCCAPSPARAMS *);
NV_STATUS gsyncOptimizeTimingParameters_P2060(OBJGPU *, GSYNCTIMINGPARAMS *);
NV_STATUS gsyncGetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32 *);
NV_STATUS gsyncSetStereoLockMode_P2060 (OBJGPU *, PDACEXTERNALDEVICE, NvU32);

2
src/nvidia/inc/kernel/gpu/external_device/dev_p2061.h
View File

@@ -35,7 +35,7 @@
#define NV_P2061_STATUS6_INT_PORT_DIRECTION_OUTPUT 1 /* RWXVF */
// Used in FW 3.00 and above
#define NV_P2061_CONTROL5 0x33 /* RW-1R */
#define NV_P2061_CONTROL5 0x15 /* RW-1R */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE 1:0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SHORT_PULSE 0 /* RWXVF */
#define NV_P2061_CONTROL5_RASTER_SYNC_DECODE_MODE_VSYNC_SINGLE_PULSE 1 /* RWXVF */

3
src/nvidia/inc/kernel/gpu/gpu_child_list.h
View File

@@ -306,6 +306,9 @@
#if RMCFG_MODULE_KERNEL_CCU && GPU_CHILD_MODULE(KERNEL_CCU)
GPU_CHILD_SINGLE_INST( KernelCcu, GPU_GET_KERNEL_CCU, 1, NV_FALSE, pKernelCcu )
#endif
#if RMCFG_MODULE_KERNEL_GSPLITE && GPU_CHILD_MODULE(KERNEL_GSPLITE)
GPU_CHILD_MULTI_INST( KernelGsplite, GPU_GET_KERNEL_GSPLITE, GPU_MAX_GSPLITES, NV_FALSE, pKernelGsplite )
#endif
// Undefine the entry macros to simplify call sites
#undef GPU_CHILD

6
src/nvidia/inc/kernel/gpu/gpu_engine_type.h
View File

@@ -71,7 +71,8 @@ typedef enum
RM_ENGINE_TYPE_NVENC0 = (0x00000025),
RM_ENGINE_TYPE_NVENC1 = (0x00000026),
RM_ENGINE_TYPE_NVENC2 = (0x00000027),
RM_ENGINE_TYPE_RESERVED28 = (0x00000028),
// Bug 4175886 - Use this new value for all chips once GB20X is released
RM_ENGINE_TYPE_NVENC3 = (0x00000028),
RM_ENGINE_TYPE_VP = (0x00000029),
RM_ENGINE_TYPE_ME = (0x0000002a),
RM_ENGINE_TYPE_PPP = (0x0000002b),
@@ -129,7 +130,8 @@ typedef enum
#define RM_ENGINE_TYPE_NVJPG RM_ENGINE_TYPE_NVJPEG0
#define RM_ENGINE_TYPE_COPY_SIZE 20
#define RM_ENGINE_TYPE_NVENC_SIZE 3
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define RM_ENGINE_TYPE_NVENC_SIZE 4
#define RM_ENGINE_TYPE_NVJPEG_SIZE 8
#define RM_ENGINE_TYPE_NVDEC_SIZE 8
#define RM_ENGINE_TYPE_OFA_SIZE 2

1
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
View File

@@ -44,6 +44,7 @@ void gpuFabricProbeStopPhysical(GPU_FABRIC_PROBE_INFO_PHYSICAL *pGpuFabricProbeI
NvU32 gfId);
void gpuFabricProbeSuspend(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
void gpuFabricProbeInvalidate(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NV_STATUS gpuFabricProbeResume(GPU_FABRIC_PROBE_INFO_KERNEL *pGpuFabricProbeInfoKernel);
NV_STATUS gpuFabricProbeGetGpuFabricHandle(GPU_FABRIC_PROBE_INFO_KERNEL *pInfo, NvU64 *pHandle);

2
src/nvidia/inc/kernel/gpu/gpu_shared_data_map.h
View File

@@ -41,6 +41,8 @@ typedef struct GpuSharedDataMap {
NvU64 lastPolledDataMask;
NvU32 processId;
NvU32 pollingRegistryOverride;
NvU32 pollingFrequencyMs;
NvBool bPollFrequencyOverridden;
TMR_EVENT *pRusdRefreshTmrEvent;

33
src/nvidia/inc/kernel/gpu/gsp/gsp_fw_heap.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -68,7 +68,15 @@
//
#define GSP_FW_HEAP_PARAM_CLIENT_ALLOC_SIZE ((48 << 10) * 2048) // Support 2048 channels
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (565 << 20) // Default for all VGPU configs
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA (12u)
#define BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA (70u)
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT \
((581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA)) << 20)
#else
#define GSP_FW_HEAP_SIZE_VGPU_DEFAULT (581 << 20)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
@@ -76,10 +84,25 @@
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MIN_MB (64u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS2_MAX_MB (256u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (86u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (278u)
#if RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
// Size increased for compatibility reasons with ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE
// and ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE in init_partition.h
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB \
(88u + (BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB \
(280u + (BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (565u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB \
(581u + ((BULLSEYE_ROOT_HEAP_ALLOC_RM_DATA_SECTION_SIZE_DELTA)*8u) + \
(BULLSEYE_ROOT_HEAP_ALLOC_BAREMETAL_LIBOS_HEAP_SIZE_DELTA))
#else
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MIN_MB (88u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_BAREMETAL_MAX_MB (280u)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MIN_MB (581u)
#endif // RMCFG_FEATURE_GSPRM_BULLSEYE || defined(GSPRM_BULLSEYE_ENABLE)
#define GSP_FW_HEAP_SIZE_OVERRIDE_LIBOS3_VGPU_MAX_MB (1040u)
#endif // GSP_FW_HEAP_H

7
src/nvidia/inc/kernel/gpu/gsp/gsp_init_args.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,10 +24,10 @@
#ifndef GSP_INIT_ARGS_H
#define GSP_INIT_ARGS_H
#include "core/core.h"
#include "nvtypes.h"
typedef struct {
RmPhysAddr sharedMemPhysAddr;
NvU64 sharedMemPhysAddr;
NvU32 pageTableEntryCount;
NvLength cmdQueueOffset;
NvLength statQueueOffset;
@@ -47,6 +47,7 @@ typedef struct
MESSAGE_QUEUE_INIT_ARGUMENTS messageQueueInitArguments;
GSP_SR_INIT_ARGUMENTS srInitArguments;
NvU32 gpuInstance;
NvBool bDmemStack;
struct
{

12
src/nvidia/inc/kernel/gpu/gsp/gsp_static_config.h
View File

@@ -68,6 +68,12 @@ typedef struct
NvU32 ecidExtended;
} EcidManufacturingInfo;
typedef struct
{
NvU64 nonWprHeapOffset;
NvU64 frtsOffset;
} FW_WPR_LAYOUT_OFFSET;
// Fetched from GSP-RM into CPU-RM
typedef struct GspStaticConfigInfo_t
{
@@ -103,8 +109,10 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsTesla;
NvBool bIsMobile;
NvBool bIsGc6Rtd3Allowed;
NvBool bIsGc8Rtd3Allowed;
NvBool bIsGcOffRtd3Allowed;
NvBool bIsGcoffLegacyAllowed;
NvBool bIsMigSupported;
/* "Total Board Power" refers to power requirement of GPU,
* while in GC6 state. Majority of this power will be used
@@ -154,6 +162,8 @@ typedef struct GspStaticConfigInfo_t
NvBool bIsEfiInit;
EcidManufacturingInfo ecidInfo[MAX_GROUP_COUNT];
FW_WPR_LAYOUT_OFFSET fwWprLayoutOffset;
} GspStaticConfigInfo;
// Pushed from CPU-RM to GSP-RM
@@ -182,6 +192,7 @@ typedef struct GspSystemInfo
NvBool bFlrSupported;
NvBool b64bBar0Supported;
NvBool bMnocAvailable;
NvU32 chipsetL1ssEnable;
NvBool bUpstreamL0sUnsupported;
NvBool bUpstreamL1Unsupported;
NvBool bUpstreamL1PorSupported;
@@ -204,6 +215,7 @@ typedef struct GspSystemInfo
NvBool bFeatureStretchVblankCapable;
NvBool bEnableDynamicGranularityPageArrays;
NvBool bClockBoostSupported;
NvBool bRouteDispIntrsToCPU;
} GspSystemInfo;

26
src/nvidia/inc/kernel/gpu/intr/engine_idx.h
View File

@@ -78,7 +78,8 @@
#define MC_ENGINE_IDX_NVENC 38
#define MC_ENGINE_IDX_NVENC1 39
#define MC_ENGINE_IDX_NVENC2 40
#define MC_ENGINE_IDX_RESERVED41 41
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_NVENC3 41
#define MC_ENGINE_IDX_C2C 42
#define MC_ENGINE_IDX_LTC 43
#define MC_ENGINE_IDX_FBHUB 44
@@ -152,12 +153,19 @@
#define MC_ENGINE_IDX_PXUC 168
#define MC_ENGINE_IDX_SYSLTC 169
#define MC_ENGINE_IDX_LRCC 170
#define MC_ENGINE_IDX_RESERVED171 171
#define MC_ENGINE_IDX_RESERVED172 172
#define MC_ENGINE_IDX_RESERVED173 173
#define MC_ENGINE_IDX_RESERVED174 174
// Bug 4175886 - Use this new value for all chips once GB20X is released
#define MC_ENGINE_IDX_GSPLITE 171
#define MC_ENGINE_IDX_GSPLITE0 MC_ENGINE_IDX_GSPLITE
#define MC_ENGINE_IDX_GSPLITE1 172
#define MC_ENGINE_IDX_GSPLITE2 173
#define MC_ENGINE_IDX_GSPLITE3 174
#define MC_ENGINE_IDX_GSPLITE_MAX MC_ENGINE_IDX_GSPLITE3
#define MC_ENGINE_IDX_DPAUX 175
#define MC_ENGINE_IDX_DISP_LOW 176
// This must be kept as the max bit if we need to add more engines
#define MC_ENGINE_IDX_MAX 175
#define MC_ENGINE_IDX_MAX 177
// Index GR reference
#define MC_ENGINE_IDX_GRn(x) (MC_ENGINE_IDX_GR0 + (x))
@@ -184,6 +192,12 @@
// Index OFA reference
#define MC_ENGINE_IDX_OFA(x) (MC_ENGINE_IDX_OFA0 + (x))
//
// Bug 4175886 - Remove check once GB20X is released
// Index GSPLITE reference
//
#define MC_ENGINE_IDX_GSPLITEn(x) (MC_ENGINE_IDX_GSPLITE + (x))
MAKE_BITVECTOR(MC_ENGINE_BITVECTOR, MC_ENGINE_IDX_MAX);
typedef MC_ENGINE_BITVECTOR *PMC_ENGINE_BITVECTOR;

2
src/nvidia/inc/kernel/gpu/mem_mgr/channel_utils.h
View File

@@ -51,6 +51,8 @@
#include "class/clc9b5.h" // BLACKWELL_DMA_COPY_A
#include "class/clcab5.h" // BLACKWELL_DMA_COPY_B
#include "gpu/conf_compute/ccsl.h"
#include "nvctassert.h"