mirror of
https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-23 16:34:00 +00:00
555.42.02
This commit is contained in:
Bernhard Stoeckner
@@ -37,13 +37,11 @@ typedef enum _HYPERVISOR_TYPE
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OS_HYPERVISOR_UNKNOWN
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} HYPERVISOR_TYPE;
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#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0
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#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1
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#define CMD_VGPU_VFIO_REGISTER_MDEV 2
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#define CMD_VGPU_VFIO_PRESENT 3
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#define CMD_VFIO_PCI_CORE_PRESENT 4
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#define CMD_VFIO_WAKE_REMOVE_GPU 1
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#define CMD_VGPU_VFIO_PRESENT 2
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#define CMD_VFIO_PCI_CORE_PRESENT 3
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#define MAX_VF_COUNT_PER_GPU 64
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#define MAX_VF_COUNT_PER_GPU 64
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typedef enum _VGPU_TYPE_INFO
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{
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@@ -54,17 +52,11 @@ typedef enum _VGPU_TYPE_INFO
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typedef struct
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{
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void *vgpuVfioRef;
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void *waitQueue;
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void *nv;
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NvU32 *vgpuTypeIds;
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NvU8 **vgpuNames;
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NvU32 numVgpuTypes;
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NvU32 domain;
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NvU8 bus;
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NvU8 slot;
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NvU8 function;
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NvBool is_virtfn;
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NvU32 domain;
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NvU32 bus;
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NvU32 device;
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NvU32 return_status;
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} vgpu_vfio_info;
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typedef struct
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@@ -58,14 +58,10 @@
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#include <linux/version.h>
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#include <linux/utsname.h>
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#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 32)
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#error "This driver does not support kernels older than 2.6.32!"
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#elif LINUX_VERSION_CODE < KERNEL_VERSION(2, 7, 0)
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# define KERNEL_2_6
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#elif LINUX_VERSION_CODE >= KERNEL_VERSION(3, 0, 0)
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# define KERNEL_3
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#else
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#error "This driver does not support development kernels!"
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#if LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 0)
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// Version 4.4 is allowed, temporarily, although not officially supported.
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#elif LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)
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#error "This driver does not support kernels older than Linux 4.15!"
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#endif
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#if defined (CONFIG_SMP) && !defined (__SMP__)
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@@ -836,16 +832,16 @@ static inline dma_addr_t nv_phys_to_dma(struct device *dev, NvU64 pa)
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#define NV_PRINT_AT(nv_debug_level,at) \
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{ \
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nv_printf(nv_debug_level, \
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"NVRM: VM: %s:%d: 0x%p, %d page(s), count = %d, flags = 0x%08x, " \
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"NVRM: VM: %s:%d: 0x%p, %d page(s), count = %d, " \
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"page_table = 0x%p\n", __FUNCTION__, __LINE__, at, \
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at->num_pages, NV_ATOMIC_READ(at->usage_count), \
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at->flags, at->page_table); \
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at->page_table); \
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}
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#define NV_PRINT_VMA(nv_debug_level,vma) \
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{ \
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nv_printf(nv_debug_level, \
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"NVRM: VM: %s:%d: 0x%lx - 0x%lx, 0x%08x bytes @ 0x%016llx, 0x%p, 0x%p\n", \
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"NVRM: VM: %s:%d: 0x%lx - 0x%lx, 0x%08lx bytes @ 0x%016llx, 0x%p, 0x%p\n", \
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__FUNCTION__, __LINE__, vma->vm_start, vma->vm_end, NV_VMA_SIZE(vma), \
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NV_VMA_OFFSET(vma), NV_VMA_PRIVATE(vma), NV_VMA_FILE(vma)); \
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}
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@@ -1078,6 +1074,8 @@ static inline void nv_kmem_ctor_dummy(void *arg)
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kmem_cache_destroy(kmem_cache); \
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}
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#define NV_KMEM_CACHE_ALLOC_ATOMIC(kmem_cache) \
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kmem_cache_alloc(kmem_cache, GFP_ATOMIC)
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#define NV_KMEM_CACHE_ALLOC(kmem_cache) \
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kmem_cache_alloc(kmem_cache, GFP_KERNEL)
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#define NV_KMEM_CACHE_FREE(ptr, kmem_cache) \
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@@ -1104,6 +1102,23 @@ static inline void *nv_kmem_cache_zalloc(struct kmem_cache *k, gfp_t flags)
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#endif
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}
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static inline int nv_kmem_cache_alloc_stack_atomic(nvidia_stack_t **stack)
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{
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nvidia_stack_t *sp = NULL;
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#if defined(NVCPU_X86_64)
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if (rm_is_altstack_in_use())
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{
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sp = NV_KMEM_CACHE_ALLOC_ATOMIC(nvidia_stack_t_cache);
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if (sp == NULL)
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return -ENOMEM;
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sp->size = sizeof(sp->stack);
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sp->top = sp->stack + sp->size;
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}
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#endif
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*stack = sp;
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return 0;
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}
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static inline int nv_kmem_cache_alloc_stack(nvidia_stack_t **stack)
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{
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nvidia_stack_t *sp = NULL;
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@@ -1614,6 +1629,10 @@ typedef struct nv_linux_state_s {
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nv_kthread_q_t open_q;
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NvBool is_accepting_opens;
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struct semaphore open_q_lock;
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#if defined(NV_VGPU_KVM_BUILD)
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wait_queue_head_t wait;
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NvS32 return_status;
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#endif
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} nv_linux_state_t;
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extern nv_linux_state_t *nv_linux_devices;
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@@ -29,17 +29,17 @@
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typedef int vm_fault_t;
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#endif
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/* pin_user_pages
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/*
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* pin_user_pages()
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*
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* Presence of pin_user_pages() also implies the presence of unpin-user_page().
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* Both were added in the v5.6-rc1
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* Both were added in the v5.6.
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*
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* pin_user_pages() was added by commit eddb1c228f7951d399240
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* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6-rc1 (2020-01-30)
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*
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* Removed vmas parameter from pin_user_pages() by commit 40896a02751
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* ("mm/gup: remove vmas parameter from pin_user_pages()")
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* in linux-next, expected in v6.5-rc1 (2023-05-17)
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* pin_user_pages() was added by commit eddb1c228f79
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* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6.
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*
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* Removed vmas parameter from pin_user_pages() by commit 4c630f307455
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* ("mm/gup: remove vmas parameter from pin_user_pages()") in v6.5.
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*/
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#include <linux/mm.h>
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@@ -63,25 +63,28 @@ typedef int vm_fault_t;
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#define NV_UNPIN_USER_PAGE put_page
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#endif // NV_PIN_USER_PAGES_PRESENT
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/* get_user_pages
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/*
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* get_user_pages()
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*
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* The 8-argument version of get_user_pages was deprecated by commit
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* (2016 Feb 12: cde70140fed8429acf7a14e2e2cbd3e329036653)for the non-remote case
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* The 8-argument version of get_user_pages() was deprecated by commit
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* cde70140fed8 ("mm/gup: Overload get_user_pages() functions") in v4.6-rc1.
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* (calling get_user_pages with current and current->mm).
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*
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* Completely moved to the 6 argument version of get_user_pages -
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* 2016 Apr 4: c12d2da56d0e07d230968ee2305aaa86b93a6832
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* Completely moved to the 6 argument version of get_user_pages() by
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* commit c12d2da56d0e ("mm/gup: Remove the macro overload API migration
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* helpers from the get_user*() APIs") in v4.6-rc4.
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*
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* write and force parameters were replaced with gup_flags by -
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* 2016 Oct 12: 768ae309a96103ed02eb1e111e838c87854d8b51
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* write and force parameters were replaced with gup_flags by
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* commit 768ae309a961 ("mm: replace get_user_pages() write/force parameters
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* with gup_flags") in v4.9.
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*
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* A 7-argument version of get_user_pages was introduced into linux-4.4.y by
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* commit 8e50b8b07f462ab4b91bc1491b1c91bd75e4ad40 which cherry-picked the
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* replacement of the write and force parameters with gup_flags
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* commit 8e50b8b07f462 ("mm: replace get_user_pages() write/force parameters
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* with gup_flags") which cherry-picked the replacement of the write and
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* force parameters with gup_flags.
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*
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* Removed vmas parameter from get_user_pages() by commit 7bbf9c8c99
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* ("mm/gup: remove unused vmas parameter from get_user_pages()")
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* in linux-next, expected in v6.5-rc1 (2023-05-17)
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* Removed vmas parameter from get_user_pages() by commit 54d020692b34
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* ("mm/gup: remove unused vmas parameter from get_user_pages()") in v6.5.
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*
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*/
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@@ -112,18 +115,19 @@ typedef int vm_fault_t;
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}
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#endif // NV_GET_USER_PAGES_HAS_ARGS_FLAGS
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/* pin_user_pages_remote
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/*
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* pin_user_pages_remote()
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*
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* pin_user_pages_remote() was added by commit eddb1c228f7951d399240
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* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6 (2020-01-30)
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* pin_user_pages_remote() was added by commit eddb1c228f79
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* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6.
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*
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* pin_user_pages_remote() removed 'tsk' parameter by commit
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* 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code")
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* in v5.9-rc1 (2020-08-11). *
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* 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code")
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* in v5.9.
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*
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* Removed unused vmas parameter from pin_user_pages_remote() by commit
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* 83bcc2e132("mm/gup: remove unused vmas parameter from pin_user_pages_remote()")
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* in linux-next, expected in v6.5-rc1 (2023-05-14)
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* 0b295316b3a9 ("mm/gup: remove unused vmas parameter from
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* pin_user_pages_remote()") in v6.5.
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*
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*/
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@@ -143,7 +147,7 @@ typedef int vm_fault_t;
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/*
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* get_user_pages_remote() was added by commit 1e9877902dc7
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* ("mm/gup: Introduce get_user_pages_remote()") in v4.6 (2016-02-12).
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* ("mm/gup: Introduce get_user_pages_remote()") in v4.6.
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*
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* Note that get_user_pages_remote() requires the caller to hold a reference on
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* the task_struct (if non-NULL and if this API has tsk argument) and the mm_struct.
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@@ -153,19 +157,17 @@ typedef int vm_fault_t;
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*
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* get_user_pages_remote() write/force parameters were replaced
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* with gup_flags by commit 9beae1ea8930 ("mm: replace get_user_pages_remote()
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* write/force parameters with gup_flags") in v4.9 (2016-10-13).
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* write/force parameters with gup_flags") in v4.9.
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*
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* get_user_pages_remote() added 'locked' parameter by commit 5b56d49fc31d
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* ("mm: add locked parameter to get_user_pages_remote()") in
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* v4.10 (2016-12-14).
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* ("mm: add locked parameter to get_user_pages_remote()") in v4.10.
|
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*
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* get_user_pages_remote() removed 'tsk' parameter by
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* commit 64019a2e467a ("mm/gup: remove task_struct pointer for
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* all gup code") in v5.9-rc1 (2020-08-11).
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* all gup code") in v5.9.
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*
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* Removed vmas parameter from get_user_pages_remote() by commit a4bde14d549
|
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* ("mm/gup: remove vmas parameter from get_user_pages_remote()")
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* in linux-next, expected in v6.5-rc1 (2023-05-14)
|
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* Removed vmas parameter from get_user_pages_remote() by commit ca5e863233e8
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* ("mm/gup: remove vmas parameter from get_user_pages_remote()") in v6.5.
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*
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*/
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
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* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
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* SPDX-License-Identifier: MIT
|
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
|
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@@ -609,6 +609,15 @@ typedef enum
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NV_POWER_STATE_RUNNING
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} nv_power_state_t;
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typedef struct
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{
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const char *vidmem_power_status;
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const char *dynamic_power_status;
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const char *gc6_support;
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const char *gcoff_support;
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const char *s0ix_status;
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} nv_power_info_t;
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#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga)
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#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL)
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@@ -778,7 +787,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void);
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|
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void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 );
|
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|
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NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **);
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NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, void **);
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NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
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NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *);
|
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|
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@@ -822,6 +831,7 @@ void NV_API_CALL nv_acpi_methods_init (NvU32 *);
|
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void NV_API_CALL nv_acpi_methods_uninit (void);
|
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|
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NV_STATUS NV_API_CALL nv_acpi_method (NvU32, NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
|
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NV_STATUS NV_API_CALL nv_acpi_d3cold_dsm_for_upstream_port (nv_state_t *, NvU8 *, NvU32, NvU32, NvU32 *);
|
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NV_STATUS NV_API_CALL nv_acpi_dsm_method (nv_state_t *, NvU8 *, NvU32, NvBool, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
|
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NV_STATUS NV_API_CALL nv_acpi_ddc_method (nv_state_t *, void *, NvU32 *, NvBool);
|
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NV_STATUS NV_API_CALL nv_acpi_dod_method (nv_state_t *, NvU32 *, NvU32 *);
|
||||
@@ -990,10 +1000,10 @@ NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU6
|
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NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64);
|
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NV_STATUS NV_API_CALL rm_p2p_get_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *);
|
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NV_STATUS NV_API_CALL rm_p2p_get_gpu_info (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **);
|
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NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, void *, void *);
|
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NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, void *, void *, void **);
|
||||
NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **);
|
||||
void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle);
|
||||
@@ -1027,9 +1037,7 @@ void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_s
|
||||
NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
|
||||
void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
|
||||
NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *);
|
||||
const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *);
|
||||
const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *);
|
||||
const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool);
|
||||
void NV_API_CALL rm_get_power_info(nvidia_stack_t *, nv_state_t *, nv_power_info_t *);
|
||||
|
||||
void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32);
|
||||
void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *);
|
||||
@@ -1041,13 +1049,12 @@ NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, c
|
||||
NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *, NvBool *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *,
|
||||
NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_update_request(nvidia_stack_t *, const NvU8 *, NvU32, NvU64 *, NvU64 *, const char *);
|
||||
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *);
|
||||
NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);
|
||||
nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1462,6 +1462,29 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe
|
||||
char *methodStream,
|
||||
NvU32 methodStreamSize);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceKeyRotationChannelDisable
|
||||
|
||||
This function notifies RM that the given channels are idle.
|
||||
|
||||
This function is called after RM has notified UVM that keys need to be rotated.
|
||||
When called RM will disable the channels, rotate their keys, and then re-enable
|
||||
the channels.
|
||||
|
||||
Locking: This function acquires an API and GPU lock.
|
||||
Memory : This function dynamically allocates memory.
|
||||
|
||||
Arguments:
|
||||
channelList[IN] - An array of channel handles whose channels are idle.
|
||||
channelListCount[IN] - Number of channels in channelList. Its value must be
|
||||
greater than 0.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - channelList is NULL or channeListCount is 0.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceKeyRotationChannelDisable(uvmGpuChannelHandle channelList[],
|
||||
NvU32 channeListCount);
|
||||
|
||||
/*******************************************************************************
|
||||
Cryptography Services Library (CSL) Interface
|
||||
*/
|
||||
@@ -1507,7 +1530,7 @@ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext);
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceCslUpdateContext
|
||||
|
||||
Updates a context after a key rotation event and can only be called once per
|
||||
Updates contexts after a key rotation event and can only be called once per
|
||||
key rotation event. Following a key rotation event, and before
|
||||
nvUvmInterfaceCslUpdateContext is called, data encrypted by the GPU with the
|
||||
previous key can be decrypted with nvUvmInterfaceCslDecrypt.
|
||||
@@ -1516,12 +1539,14 @@ void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext);
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN] - The CSL context associated with a channel.
|
||||
|
||||
contextList[IN/OUT] - An array of pointers to CSL contexts.
|
||||
contextListCount[IN] - Number of CSL contexts in contextList. Its value
|
||||
must be greater than 0.
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel.
|
||||
NV_ERR_INVALID_ARGUMENT - contextList is NULL or contextListCount is 0.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslUpdateContext(UvmCslContext *uvmCslContext);
|
||||
NV_STATUS nvUvmInterfaceCslUpdateContext(UvmCslContext *contextList[],
|
||||
NvU32 contextListCount);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceCslRotateIv
|
||||
@@ -1739,7 +1764,14 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext,
|
||||
Checks and logs information about non-CSL encryptions, such as those that
|
||||
originate from the GPU.
|
||||
|
||||
This function does not modify elements of the UvmCslContext.
|
||||
For contexts associated with channels, this function does not modify elements of
|
||||
the UvmCslContext and must be called for each external encryption invocation.
|
||||
|
||||
For the context associated with fault buffers, bufferSize can encompass multiple
|
||||
encryption invocations, and the UvmCslContext will be updated following a key
|
||||
rotation event.
|
||||
|
||||
In either case the IV remains unmodified after this function is called.
|
||||
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
@@ -1748,7 +1780,7 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext,
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
bufferSize[OUT] - The size of the buffer encrypted by the
|
||||
bufferSize[OUT] - The size of the buffer(s) encrypted by the
|
||||
external entity in units of bytes.
|
||||
|
||||
Error codes:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -39,12 +39,12 @@
|
||||
// are multiple BIG page sizes in RM. These defines are used as flags to "0"
|
||||
// should be OK when user is not sure which pagesize allocation it wants
|
||||
//
|
||||
#define UVM_PAGE_SIZE_DEFAULT 0x0
|
||||
#define UVM_PAGE_SIZE_4K 0x1000
|
||||
#define UVM_PAGE_SIZE_64K 0x10000
|
||||
#define UVM_PAGE_SIZE_128K 0x20000
|
||||
#define UVM_PAGE_SIZE_2M 0x200000
|
||||
#define UVM_PAGE_SIZE_512M 0x20000000
|
||||
#define UVM_PAGE_SIZE_DEFAULT 0x0ULL
|
||||
#define UVM_PAGE_SIZE_4K 0x1000ULL
|
||||
#define UVM_PAGE_SIZE_64K 0x10000ULL
|
||||
#define UVM_PAGE_SIZE_128K 0x20000ULL
|
||||
#define UVM_PAGE_SIZE_2M 0x200000ULL
|
||||
#define UVM_PAGE_SIZE_512M 0x20000000ULL
|
||||
|
||||
//
|
||||
// When modifying flags, make sure they are compatible with the mirrored
|
||||
@@ -267,6 +267,7 @@ typedef struct UvmGpuChannelInfo_tag
|
||||
|
||||
// The errorNotifier is filled out when the channel hits an RC error.
|
||||
NvNotification *errorNotifier;
|
||||
NvNotification *keyRotationNotifier;
|
||||
|
||||
NvU32 hwRunlistId;
|
||||
NvU32 hwChannelId;
|
||||
@@ -292,13 +293,13 @@ typedef struct UvmGpuChannelInfo_tag
|
||||
|
||||
// GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing
|
||||
// so a channel can be controlled via another channel (SEC2 or WLC/LCIC)
|
||||
NvU64 gpFifoGpuVa;
|
||||
NvU64 gpPutGpuVa;
|
||||
NvU64 gpGetGpuVa;
|
||||
NvU64 gpFifoGpuVa;
|
||||
NvU64 gpPutGpuVa;
|
||||
NvU64 gpGetGpuVa;
|
||||
// GPU VA of work submission offset is needed in Confidential Computing
|
||||
// so CE channels can ring doorbell of other channels as required for
|
||||
// WLC/LCIC work submission
|
||||
NvU64 workSubmissionOffsetGpuVa;
|
||||
NvU64 workSubmissionOffsetGpuVa;
|
||||
} UvmGpuChannelInfo;
|
||||
|
||||
typedef enum
|
||||
@@ -1086,4 +1087,21 @@ typedef enum UvmCslOperation
|
||||
UVM_CSL_OPERATION_DECRYPT
|
||||
} UvmCslOperation;
|
||||
|
||||
typedef enum UVM_KEY_ROTATION_STATUS {
|
||||
// Key rotation complete/not in progress
|
||||
UVM_KEY_ROTATION_STATUS_IDLE = 0,
|
||||
// RM is waiting for clients to report their channels are idle for key rotation
|
||||
UVM_KEY_ROTATION_STATUS_PENDING = 1,
|
||||
// Key rotation is in progress
|
||||
UVM_KEY_ROTATION_STATUS_IN_PROGRESS = 2,
|
||||
// Key rotation timeout failure, RM will RC non-idle channels.
|
||||
// UVM should never see this status value.
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3,
|
||||
// Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4,
|
||||
// Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_ROTATION = 5,
|
||||
UVM_KEY_ROTATION_STATUS_MAX_COUNT = 6,
|
||||
} UVM_KEY_ROTATION_STATUS;
|
||||
|
||||
#endif // _NV_UVM_TYPES_H_
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -494,6 +494,23 @@ do \
|
||||
//
|
||||
#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
|
||||
|
||||
//
|
||||
// Create a 64b bitmask with n bits set
|
||||
// This is the same as ((1ULL<<n) - 1), but it doesn't overflow for n=64
|
||||
//
|
||||
// ...
|
||||
// n=-1, 0x0000000000000000
|
||||
// n=0, 0x0000000000000000
|
||||
// n=1, 0x0000000000000001
|
||||
// ...
|
||||
// n=63, 0x7FFFFFFFFFFFFFFF
|
||||
// n=64, 0xFFFFFFFFFFFFFFFF
|
||||
// n=65, 0xFFFFFFFFFFFFFFFF
|
||||
// n=66, 0xFFFFFFFFFFFFFFFF
|
||||
// ...
|
||||
//
|
||||
#define NV_BITMASK64(n) ((n<1) ? 0ULL : (NV_U64_MAX>>((n>64) ? 0 : (64-n))))
|
||||
|
||||
#define DRF_READ_1WORD_BS(d,r,f,v) \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
|
||||
@@ -574,6 +591,13 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
|
||||
n32 = BIT_IDX_32(LOWESTBIT(n32));\
|
||||
}
|
||||
|
||||
// Destructive operation on n64
|
||||
#define LOWESTBITIDX_64(n64) \
|
||||
{ \
|
||||
n64 = BIT_IDX_64(LOWESTBIT(n64));\
|
||||
}
|
||||
|
||||
|
||||
// Destructive operation on n32
|
||||
#define HIGHESTBITIDX_32(n32) \
|
||||
{ \
|
||||
@@ -918,6 +942,11 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
|
||||
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
|
||||
//
|
||||
#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); }
|
||||
//
|
||||
// Clear the bit at pos (b) for U64 which is < 128.
|
||||
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
|
||||
//
|
||||
#define NV_BIT_CLEAR_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) &= ~NVBIT64(b); else (hi) &= ~NVBIT64( b & 0x3F ); }
|
||||
|
||||
// Get the number of elements the specified fixed-size array
|
||||
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -152,6 +152,7 @@ NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manag
|
||||
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
|
||||
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
|
||||
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
|
||||
NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled")
|
||||
|
||||
// Warnings:
|
||||
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
|
||||
|
||||
@@ -152,6 +152,12 @@ typedef signed short NvS16; /* -32768 to 32767 */
|
||||
(((NvU32)(c) & 0xff) << 8) | \
|
||||
(((NvU32)(d) & 0xff))))
|
||||
|
||||
// Macro to build an NvU64 from two DWORDS, listed from msb to lsb
|
||||
#define NvU64_BUILD(a, b) \
|
||||
((NvU64)( \
|
||||
(((NvU64)(a) & ~0U) << 32) | \
|
||||
(((NvU64)(b) & ~0U))))
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */
|
||||
typedef uint32_t NvU32; /* 0 to 4294967295 */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -101,9 +101,10 @@ NV_STATUS NV_API_CALL rm_gpu_ops_paging_channels_map(nvidia_stack_t *, nvgpuAdd
|
||||
void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_key_rotation_channel_disable(nvidia_stack_t *, nvgpuChannelHandle_t [], NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_update(nvidia_stack_t *, struct ccslContext_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_update(nvidia_stack_t *, UvmCslContext *[], NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8*, NvU8 *, NvU8 *);
|
||||
|
||||
Reference in New Issue
Block a user