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https://github.com/NVIDIA/open-gpu-kernel-modules.git
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555.42.02
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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* SPDX-License-Identifier: MIT
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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@@ -494,6 +494,23 @@ do \
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//
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#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
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//
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// Create a 64b bitmask with n bits set
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// This is the same as ((1ULL<<n) - 1), but it doesn't overflow for n=64
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//
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// ...
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// n=-1, 0x0000000000000000
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// n=0, 0x0000000000000000
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// n=1, 0x0000000000000001
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// ...
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// n=63, 0x7FFFFFFFFFFFFFFF
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// n=64, 0xFFFFFFFFFFFFFFFF
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// n=65, 0xFFFFFFFFFFFFFFFF
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// n=66, 0xFFFFFFFFFFFFFFFF
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// ...
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//
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#define NV_BITMASK64(n) ((n<1) ? 0ULL : (NV_U64_MAX>>((n>64) ? 0 : (64-n))))
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#define DRF_READ_1WORD_BS(d,r,f,v) \
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((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
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((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
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@@ -574,6 +591,13 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
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n32 = BIT_IDX_32(LOWESTBIT(n32));\
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}
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// Destructive operation on n64
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#define LOWESTBITIDX_64(n64) \
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{ \
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n64 = BIT_IDX_64(LOWESTBIT(n64));\
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}
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// Destructive operation on n32
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#define HIGHESTBITIDX_32(n32) \
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{ \
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@@ -918,6 +942,11 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
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// Use (lo) if (b) is less than 64, and (hi) if >= 64.
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//
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#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); }
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//
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// Clear the bit at pos (b) for U64 which is < 128.
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// Use (lo) if (b) is less than 64, and (hi) if >= 64.
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//
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#define NV_BIT_CLEAR_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) &= ~NVBIT64(b); else (hi) &= ~NVBIT64( b & 0x3F ); }
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// Get the number of elements the specified fixed-size array
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#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
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