NVIDIA/open-gpu-kernel-modules
1
0
Fork 0
mirror of https://github.com/NVIDIA/open-gpu-kernel-modules.git synced 2026-01-30 13:09:47 +00:00
Code Issues Packages Projects Releases Wiki Activity

570.123.11

Browse Source
This commit is contained in:
russellcnv
2025-05-02 17:17:56 -07:00
parent 392cd006d3
commit 5c2ab3bc8a
57 changed files with 52492 additions and 49867 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -135,7 +135,7 @@ namespace DisplayPort
bool multistream;
bool videoSink, audioSink;
bool plugged;
bool bApplyPclkWarBug4949066;
AuxRetry friendlyAux;
bool payloadAllocated; // did the allocate payload go through?

2
src/common/displayport/inc/dp_evoadapter2x.h
View File

@@ -90,6 +90,7 @@ namespace DisplayPort
{
DP2X_RESET_LINK_REASON reason;
bool bForce;
bool bSkipLt;
} DP2XResetParam;
class EvoMainLink2x : public EvoMainLink
@@ -106,6 +107,7 @@ namespace DisplayPort
bool bSupportUHBR2_50; // Support UHBR2.5 for internal testing.
bool bSupportUHBR2_70; // Support UHBR2.7 for internal testing.
bool bSupportUHBR5_00; // Support UHBR5.0 for internal testing.
bool bEnable5147205Fix; // Enable 5147205 fix.
bool bConnectorIsUSBTypeC;

2
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -97,6 +97,7 @@
#define NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE "DP_SKIP_ZERO_OUI_CACHE"
#define NV_DP_REGKEY_DISABLE_FIX_FOR_5019537 "DP_DISABLE_5019537_FIX"
#define NV_DP_REGKEY_ENABLE_FIX_FOR_5147205 "DP_ENABLE_5147205_FIX"
// Bug 5088957 : Force head shutdown in DpLib
#define NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN "DP_WAR_5088957"
@@ -143,6 +144,7 @@ struct DP_REGKEY_DATABASE
bool bDownspreadDisabled;
bool bSkipZeroOuiCache;
bool bDisable5019537Fix;
bool bEnable5147205Fix;
bool bForceHeadShutdown;
bool bEnableLowerBppCheckForDsc;
};

6
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -518,6 +518,7 @@ create:
newDev->dpcdRevisionMinor = device.dpcdRevisionMinor;
newDev->complianceDeviceEdidReadTest = isCompliance;
newDev->maxTmdsClkRate = maxTmdsClkRate;
newDev->bApplyPclkWarBug4949066 = false;
Address::NvU32Buffer addrBuffer;
dpMemZero(addrBuffer, sizeof(addrBuffer));
@@ -525,6 +526,11 @@ create:
NV_DPTRACE_INFO(NEW_SINK_DETECTED, newDev->address.size(), addrBuffer[0], addrBuffer[1], addrBuffer[2], addrBuffer[3],
newDev->multistream, newDev->rawEDID.getManufId(), newDev->rawEDID.getProductId());
if(newDev->rawEDID.getManufId() == 0x6D1E)
{
newDev->bApplyPclkWarBug4949066 = true;
}
// Apply any DPCD overrides if required
newDev->dpcdOverrides();

31
src/common/displayport/src/dp_connectorimpl2x.cpp
View File

@@ -742,7 +742,20 @@ bool ConnectorImpl2x::notifyAttachBegin(Group *target, const DpModesetParams &mo
// Move the group to intransistion since we are at the end of notifyAttachBegin
intransitionGroups.insertFront(targetImpl);
if (dev && dev->bApplyPclkWarBug4949066 == true)
{
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS params = {0};
params.subDeviceInstance = provider->getSubdeviceIndex();
params.head = modesetParams.headIndex;
params.bEnable = NV_TRUE;
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR, &params, sizeof(params));
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "Failed to enable the WAR for bug4949066!");
}
}
bFromResumeToNAB = false;
return bLinkTrainingStatus;
}
@@ -1155,6 +1168,24 @@ void ConnectorImpl2x::notifyDetachBegin(Group *target)
if (!target)
target = firmwareGroup;
Device *newDev = target->enumDevices(0);
DeviceImpl *dev = (DeviceImpl *)newDev;
GroupImpl *group = (GroupImpl*)target;
if (dev != NULL && dev->bApplyPclkWarBug4949066 == true)
{
EvoInterface *provider = ((EvoMainLink *)main)->getProvider();
NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS params = {0};
params.subDeviceInstance = provider->getSubdeviceIndex();
params.head = group->headIndex;
params.bEnable = NV_FALSE;
NvU32 ret = provider->rmControl0073(NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR, &params, sizeof(params));
if (ret != NVOS_STATUS_SUCCESS)
{
DP_PRINTF(DP_ERROR, "Failed to Disable the WAR for bug4949066!");
}
}
return ConnectorImpl::notifyDetachBegin(target);
}

1
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -104,6 +104,7 @@ const struct
{NV_DP_REGKEY_DISABLE_DOWNSPREAD, &dpRegkeyDatabase.bDownspreadDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ZERO_OUI_CACHE, &dpRegkeyDatabase.bSkipZeroOuiCache, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_DISABLE_FIX_FOR_5019537, &dpRegkeyDatabase.bDisable5019537Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_FIX_FOR_5147205, &dpRegkeyDatabase.bEnable5147205Fix, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_FORCE_HEAD_SHUTDOWN, &dpRegkeyDatabase.bForceHeadShutdown, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_LOWER_BPP_CHECK_FOR_DSC, &dpRegkeyDatabase.bEnableLowerBppCheckForDsc, DP_REG_VAL_BOOL}
};

7
src/common/displayport/src/dp_evoadapter2x.cpp
View File

@@ -109,6 +109,7 @@ void EvoMainLink2x::applyDP2xRegkeyOverrides()
this->bSupportUHBR2_50 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_5G;
this->bSupportUHBR2_70 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_2_7G;
this->bSupportUHBR5_00 = dpRegkeyDatabase.supportInternalUhbrOnFpga & NV_DP2X_REGKEY_FPGA_UHBR_SUPPORT_5_0G;
this->bEnable5147205Fix = dpRegkeyDatabase.bEnable5147205Fix;
}
NvU32 EvoMainLink2x::headToStream(NvU32 head, bool bSidebandMessageSupported,
@@ -452,6 +453,7 @@ bool EvoMainLink2x::train(const LinkConfiguration & link, bool force,
DP2XResetParam resetParam;
dpMemZero(&resetParam, sizeof(resetParam));
resetParam.bForce = force;
resetParam.bSkipLt = bSkipLt;
// Get the original skipFallback setting.
bSkipFallback = requestRmLC.policy.skipFallback();
@@ -1110,6 +1112,11 @@ bool EvoMainLink2x::resetDPRXLink(DP2XResetParam resetParam)
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _FAKE_LINK_TRAINING, _DONOT_TOGGLE_TRANSMISSION);
}
if (resetParam.bSkipLt && bEnable5147205Fix)
{
ltRmParams.cmd |= DRF_DEF(0073_CTRL, _DP2X_CMD, _SKIP_HW_PROGRAMMING, _YES);
}
switch (resetParam.reason)
{
case DP2X_ResetLinkForPreLT:

16
src/common/inc/nvBldVer.h
View File

@@ -43,18 +43,18 @@
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/VK571_25-350"
#define NV_BUILD_CHANGELIST_NUM (35858204)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r570/VK571_25-351"
#define NV_BUILD_CHANGELIST_NUM (35924498)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r570/VK571_25-350"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35858204)
#define NV_BUILD_NAME "rel/gpu_drv/r570/VK571_25-351"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35924498)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "VK571_25-10"
#define NV_BUILD_CHANGELIST_NUM (35858204)
#define NV_BUILD_BRANCH_VERSION "VK571_25-11"
#define NV_BUILD_CHANGELIST_NUM (35924498)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "573.04"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35858204)
#define NV_BUILD_NAME "573.11"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35924498)
#define NV_BUILD_BRANCH_BASE_VERSION R570
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "570.123.10"
#define NV_VERSION_STRING "570.123.11"
#else

42
src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
View File

@@ -3377,6 +3377,44 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
#define NV0073_CTRL_CMD_DP2X_GET_LEVEL_INFO_TABLE_DATA (0x73138aU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS_MESSAGE_ID" */
/*
* NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR
*
* This command is used to apply the WAR based on EDID.
* subDeviceInstance
* This parameter specifies the subdevice instance within the
* NV04_DISPLAY_COMMON parent device to which the operation should be
* directed. This parameter must specify a value between zero and the
* total number of subdevices within the parent device. This parameter
* should be set to zero for default behavior.
* displayId
* This parameter specifies the ID of the digital display for which the
* data should be returned. The display ID must a digital display.
* If more than one displayId bit is set or the displayId is not a DP,
* this call will return NV_ERR_INVALID_ARGUMENT.
* bEnable
* This parameter will be used by RM to set the PDB property. Later that PDB
* property will be used for applying the WAR
* head
* This parameter specify for which head RM need to apply the WAR
*
* Possible status values returned are:
* NV_OK
* NV_ERR_INVALID_PARAM_STRUCT
* NV_ERR_INVALID_ARGUMENT
*
*/
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID (0x8BU)
typedef struct NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS {
NvU32 subDeviceInstance;
NvU32 displayId;
NvU32 bEnable;
NvU32 head;
} NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS;
#define NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_DP_SET_PROP_FORCE_PCLK_FACTOR_PARAMS_MESSAGE_ID" */
/*
@@ -3444,7 +3482,7 @@ typedef struct NV0073_CTRL_DP2X_GET_LEVEL_INFO_TABLE_DATA_PARAMS {
* NV_ERR_NOT_SUPPORTED
*/
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138bU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP (0x73138cU) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_DP_INTERFACE_ID << 8) | NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID" */
typedef struct NV0073_CTRL_DP_IMP_LINK_CONFIGURATION {
NvU32 linkRate10M;
@@ -3489,7 +3527,7 @@ typedef struct NV0073_CTRL_DP_IMP_WATERMARK {
NvBool bIsModePossible;
} NV0073_CTRL_DP_IMP_WATERMARK;
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8BU)
#define NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS_MESSAGE_ID (0x8CU)
typedef struct NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS {
NvU32 subDeviceInstance;

6
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2574,11 +2574,17 @@ typedef struct NV2080_CTRL_NVLINK_PRM_ACCESS_PPLM_PARAMS {
NvBool bWrite;
NV2080_CTRL_NVLINK_PRM_DATA prm;
NvBool test_mode;
NvBool plr_vld;
NvU8 plane_ind;
NvU8 port_type;
NvU8 lp_msb;
NvU8 pnat;
NvU8 local_port;
NvBool plr_reject_mode_vld;
NvBool plr_margin_th_override_to_default;
NvU8 plr_reject_mode;
NvU8 tx_crc_plr;
NvU8 plr_margin_th;
NvU8 fec_override_admin_10g_40g;
NvU8 fec_override_admin_25g;
NvU8 fec_override_admin_50g;

1
src/common/uproc/os/common/include/liblogdecode.h
View File

@@ -132,6 +132,7 @@ struct LIBOS_LOG_DECODE_LOG
NvU32 gpuInstance; // GPU that this log is associated with.
char taskPrefix[TASK_NAME_MAX_LENGTH]; // Prefix string printed before each line.
char elfSectionName[ELF_SECTION_NAME_MAX]; // Task section name in container logging ELF serving as ID.
NvU64 localToGlobalTimerDelta;
#if LIBOS_LOG_TO_NVLOG
NvU32 hNvLogNoWrap; // No wrap buffer captures first records.

4
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
View File

@@ -569,7 +569,7 @@ static int libos_printf_a(
// Prefix every line with T:nnnn GPUn Ucode-task: filename(lineNumber):
len = snprintf(
logDecode->curLineBufPtr, remain,
"T:%llu ", pRec->timeStamp);
"T:%llu ", pRec->timeStamp + pRec->log->localToGlobalTimerDelta);
if (len < 0)
{
return -1;
@@ -590,7 +590,7 @@ static int libos_printf_a(
{
struct tm tmStruct;
// Libos timestamp is a PTIMER value, which is UNIX time in ns
time_t timeSec = pRec->timeStamp / 1000000000;
time_t timeSec = (pRec->timeStamp + pRec->log->localToGlobalTimerDelta) / 1000000000;
#if NVOS_IS_WINDOWS
// "The implementation of localtime_s in Microsoft CRT is incompatible with the
// C standard since it has reversed parameter order and returns errno_t."

10
src/nvidia-modeset/kapi/src/nvkms-kapi.c
View File

@@ -79,8 +79,14 @@ static NvU32 EnumerateGpus(nv_gpu_info_t *gpuInfo)
*/
static void RmFreeDevice(struct NvKmsKapiDevice *device)
{
nvKmsKapiFreeRmHandle(device, device->smgGpuInstSubscriptionHdl);
nvKmsKapiFreeRmHandle(device, device->smgComputeInstSubscriptionHdl);
if (device->smgGpuInstSubscriptionHdl != 0x0) {
nvKmsKapiFreeRmHandle(device, device->smgGpuInstSubscriptionHdl);
device->smgGpuInstSubscriptionHdl = 0x0;
}
if (device->smgComputeInstSubscriptionHdl != 0x0) {
nvKmsKapiFreeRmHandle(device, device->smgComputeInstSubscriptionHdl);
device->smgComputeInstSubscriptionHdl = 0x0;
}
if (device->hRmSubDevice != 0x0) {
nvRmApiFree(device->hRmClient,

49724
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmBoot_GB202.c
View File

File diff suppressed because it is too large Load Diff

24852
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwDebugSigned_GB202.c
View File

File diff suppressed because it is too large Load Diff

24898
src/nvidia/generated/g_bindata_kgspGetBinArchiveGspRmFmcGfwProdSigned_GB202.c
View File

File diff suppressed because it is too large Load Diff

4
src/nvidia/generated/g_disp_objs_nvoc.c
View File

@@ -5106,7 +5106,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100u)
/*flags=*/ 0x100u,
/*accessRight=*/0x0u,
/*methodId=*/ 0x73138bu,
/*methodId=*/ 0x73138cu,
/*paramSize=*/ sizeof(NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS),
/*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo),
#if NV_PRINTF_STRINGS_ALLOWED
@@ -5897,7 +5897,7 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) {
pThis->__dispcmnCtrlCmdDp2xSetLaneData__ = &dispcmnCtrlCmdDp2xSetLaneData_IMPL;
#endif
// dispcmnCtrlCmdCalculateDpImp -- exported (id=0x73138b)
// dispcmnCtrlCmdCalculateDpImp -- exported (id=0x73138c)
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x100u)
pThis->__dispcmnCtrlCmdCalculateDpImp__ = &dispcmnCtrlCmdCalculateDpImp_IMPL;
#endif

2
src/nvidia/generated/g_disp_objs_nvoc.h
View File

@@ -1677,7 +1677,7 @@ struct DispCommon {
NV_STATUS (*__dispcmnCtrlCmdDp2xLinkTrain__)(struct DispCommon * /*this*/, NV0073_CTRL_CMD_DP2X_LINK_TRAINING_CTRL_PARAMS *); // exported (id=0x731383)
NV_STATUS (*__dispcmnCtrlCmdDp2xGetLaneData__)(struct DispCommon * /*this*/, NV0073_CTRL_DP2X_LANE_DATA_PARAMS *); // exported (id=0x731384)
NV_STATUS (*__dispcmnCtrlCmdDp2xSetLaneData__)(struct DispCommon * /*this*/, NV0073_CTRL_DP2X_LANE_DATA_PARAMS *); // exported (id=0x731385)
NV_STATUS (*__dispcmnCtrlCmdCalculateDpImp__)(struct DispCommon * /*this*/, NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS *); // exported (id=0x73138b)
NV_STATUS (*__dispcmnCtrlCmdCalculateDpImp__)(struct DispCommon * /*this*/, NV0073_CTRL_CMD_CALCULATE_DP_IMP_PARAMS *); // exported (id=0x73138c)
NV_STATUS (*__dispcmnCtrlCmdDpGetLaneData__)(struct DispCommon * /*this*/, NV0073_CTRL_DP_LANE_DATA_PARAMS *); // exported (id=0x731345)
NV_STATUS (*__dispcmnCtrlCmdDpSetLaneData__)(struct DispCommon * /*this*/, NV0073_CTRL_DP_LANE_DATA_PARAMS *); // exported (id=0x731346)
NV_STATUS (*__dispcmnCtrlCmdDpGetTestpattern__)(struct DispCommon * /*this*/, NV0073_CTRL_DP_GET_TESTPATTERN_PARAMS *); // exported (id=0x731348)

8
src/nvidia/generated/g_gpu_acct_nvoc.h
View File

@@ -49,7 +49,6 @@ extern "C" {
#include "ctrl/ctrl0000/ctrl0000gpuacct.h"
#include "ctrl/ctrl0000/ctrl0000gpu.h" // NV0000_CTRL_GPU_MAX_ATTACHED_GPUS
#include "ctrl/ctrl2080/ctrl2080perf.h" // NV2080_CTRL_PERF_GET_GPUMON_PERFMON_UTIL_SAMPLES_V2_PARAMS
#include "rmapi/client.h"
typedef struct TMR_EVENT TMR_EVENT;
@@ -75,7 +74,6 @@ typedef struct
{
NvU32 procId; // Pid of the process.
NvU32 procType; // Type of the process.
struct RmClient *pClient; // Process' RmClient.
NvU32 gpuUtil; // Process's average GR engine utilization.
NvU64 sumUtil; // Running sum of process's GR engine utilization.
NvU32 fbUtil; // Process's average FB bandwidth utilization.
@@ -242,15 +240,15 @@ static inline NV_STATUS gpuacctClearAccountingData(struct GpuAccounting *arg1, N
#define gpuacctClearAccountingData(arg1, arg2, arg3) gpuacctClearAccountingData_IMPL(arg1, arg2, arg3)
#endif //__nvoc_gpu_acct_h_disabled
NV_STATUS gpuacctStartGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, struct RmClient *arg5);
NV_STATUS gpuacctStartGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4);
#ifdef __nvoc_gpu_acct_h_disabled
static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4, struct RmClient *arg5) {
static inline NV_STATUS gpuacctStartGpuAccounting(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4) {
NV_ASSERT_FAILED_PRECOMP("GpuAccounting was disabled!");
return NV_ERR_NOT_SUPPORTED;
}
#else //__nvoc_gpu_acct_h_disabled
#define gpuacctStartGpuAccounting(arg1, arg2, arg3, arg4, arg5) gpuacctStartGpuAccounting_IMPL(arg1, arg2, arg3, arg4, arg5)
#define gpuacctStartGpuAccounting(arg1, arg2, arg3, arg4) gpuacctStartGpuAccounting_IMPL(arg1, arg2, arg3, arg4)
#endif //__nvoc_gpu_acct_h_disabled
NV_STATUS gpuacctStopGpuAccounting_IMPL(struct GpuAccounting *arg1, NvU32 arg2, NvU32 arg3, NvU32 arg4);

3
src/nvidia/generated/g_hal_stubs.h
View File

@@ -719,7 +719,8 @@ NV_STATUS rpcCtrlGetZbcClearTable_STUB(
NV_STATUS rpcCleanupSurface_STUB(
POBJGPU pGpu,
POBJRPC pRpc,
NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg3
NvHandle arg3,
NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pArg4
)
{
return NV_VGPU_MSG_RESULT_RPC_UNKNOWN_FUNCTION;

2
src/nvidia/generated/g_kern_fsp_nvoc.h
View File

@@ -14,7 +14,7 @@ extern "C" {
#endif
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

18
src/nvidia/generated/g_kernel_nvlink_nvoc.c
View File

@@ -107,7 +107,7 @@ NV_STATUS __nvoc_down_thunk_KernelNvlink_engstateStatePostUnload(struct OBJGPU *
return knvlinkStatePostUnload(arg1, (struct KernelNvlink *)(((unsigned char *) arg_this) - NV_OFFSETOF(KernelNvlink, __nvoc_base_OBJENGSTATE)), arg3);
}
// knvlinkIsPresent: virtual override (engstate) base (engstate)
// knvlinkIsPresent: virtual halified (2 hals) override (engstate) base (engstate)
NvBool __nvoc_down_thunk_KernelNvlink_engstateIsPresent(struct OBJGPU *arg1, struct OBJENGSTATE *arg_this) {
return knvlinkIsPresent(arg1, (struct KernelNvlink *)(((unsigned char *) arg_this) - NV_OFFSETOF(KernelNvlink, __nvoc_base_OBJENGSTATE)));
}
@@ -357,6 +357,17 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO
PORT_UNREFERENCED_VARIABLE(chipHal);
PORT_UNREFERENCED_VARIABLE(chipHal_HalVarIdx);
// knvlinkIsPresent -- virtual halified (2 hals) override (engstate) base (engstate)
if (( ((rmVariantHal_HalVarIdx >> 5) == 0UL) && ((1UL << (rmVariantHal_HalVarIdx & 0x1f)) & 0x00000001UL) )) /* RmVariantHal: VF */
{
pThis->__knvlinkIsPresent__ = &knvlinkIsPresent_3dd2c9;
}
// default
else
{
pThis->__knvlinkIsPresent__ = &knvlinkIsPresent_IMPL;
}
// knvlinkSetUniqueFabricBaseAddress -- halified (3 hals) body
if (( ((chipHal_HalVarIdx >> 5) == 1UL) && ((1UL << (chipHal_HalVarIdx & 0x1f)) & 0x01f0fc00UL) )) /* ChipHal: GA100 | GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 */
{
@@ -770,7 +781,7 @@ static void __nvoc_init_funcTable_KernelNvlink_1(KernelNvlink *pThis, RmHalspecO
{
pThis->__knvlinkGetSupportedCounters__ = &knvlinkGetSupportedCounters_46f6a7;
}
} // End __nvoc_init_funcTable_KernelNvlink_1 with approximately 80 basic block(s).
} // End __nvoc_init_funcTable_KernelNvlink_1 with approximately 82 basic block(s).
// Initialize vtable(s) for 50 virtual method(s).
@@ -790,7 +801,6 @@ void __nvoc_init_funcTable_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm
.OBJENGSTATE.__engstateStateUnload__ = &__nvoc_down_thunk_KernelNvlink_engstateStateUnload, // virtual
.__knvlinkStatePostUnload__ = &knvlinkStatePostUnload_IMPL, // virtual override (engstate) base (engstate)
.OBJENGSTATE.__engstateStatePostUnload__ = &__nvoc_down_thunk_KernelNvlink_engstateStatePostUnload, // virtual
.__knvlinkIsPresent__ = &knvlinkIsPresent_IMPL, // virtual override (engstate) base (engstate)
.OBJENGSTATE.__engstateIsPresent__ = &__nvoc_down_thunk_KernelNvlink_engstateIsPresent, // virtual
.__knvlinkInitMissing__ = &__nvoc_up_thunk_OBJENGSTATE_knvlinkInitMissing, // virtual inherited (engstate) base (engstate)
.OBJENGSTATE.__engstateInitMissing__ = &engstateInitMissing_IMPL, // virtual
@@ -812,7 +822,7 @@ void __nvoc_init_funcTable_KernelNvlink(KernelNvlink *pThis, RmHalspecOwner *pRm
pThis->__nvoc_base_OBJENGSTATE.__nvoc_vtable = &vtable.OBJENGSTATE; // (engstate) super
pThis->__nvoc_vtable = &vtable; // (knvlink) this
// Initialize vtable(s) with 36 per-object function pointer(s).
// Initialize vtable(s) with 37 per-object function pointer(s).
__nvoc_init_funcTable_KernelNvlink_1(pThis, pRmhalspecowner);
}

18
src/nvidia/generated/g_kernel_nvlink_nvoc.h
View File

@@ -264,7 +264,8 @@ struct KernelNvlink {
struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; // engstate super
struct KernelNvlink *__nvoc_pbase_KernelNvlink; // knvlink
// Vtable with 36 per-object function pointers
// Vtable with 37 per-object function pointers
NvBool (*__knvlinkIsPresent__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual halified (2 hals) override (engstate) base (engstate)
NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU64); // halified (3 hals) body
void (*__knvlinkClearUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // halified (2 hals) body
NV_STATUS (*__knvlinkSetUniqueFabricEgmBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU64); // halified (2 hals) body
@@ -397,7 +398,8 @@ struct KernelNvlink_PRIVATE {
struct OBJENGSTATE *__nvoc_pbase_OBJENGSTATE; // engstate super
struct KernelNvlink *__nvoc_pbase_KernelNvlink; // knvlink
// Vtable with 36 per-object function pointers
// Vtable with 37 per-object function pointers
NvBool (*__knvlinkIsPresent__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual halified (2 hals) override (engstate) base (engstate)
NV_STATUS (*__knvlinkSetUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU64); // halified (3 hals) body
void (*__knvlinkClearUniqueFabricBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // halified (2 hals) body
NV_STATUS (*__knvlinkSetUniqueFabricEgmBaseAddress__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU64); // halified (2 hals) body
@@ -516,7 +518,7 @@ struct KernelNvlink_PRIVATE {
};
// Metadata including vtable with 14 function pointers plus superclass metadata
// Metadata including vtable with 13 function pointers plus superclass metadata
struct NVOC_VTABLE__KernelNvlink {
const struct NVOC_VTABLE__OBJENGSTATE OBJENGSTATE; // (engstate) 14 function pointers
@@ -526,7 +528,6 @@ struct NVOC_VTABLE__KernelNvlink {
NV_STATUS (*__knvlinkStatePostLoad__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU32); // virtual override (engstate) base (engstate)
NV_STATUS (*__knvlinkStateUnload__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU32); // virtual override (engstate) base (engstate)
NV_STATUS (*__knvlinkStatePostUnload__)(struct OBJGPU *, struct KernelNvlink * /*this*/, NvU32); // virtual override (engstate) base (engstate)
NvBool (*__knvlinkIsPresent__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual override (engstate) base (engstate)
void (*__knvlinkInitMissing__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__knvlinkStatePreInitUnlocked__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual inherited (engstate) base (engstate)
NV_STATUS (*__knvlinkStateInitLocked__)(struct OBJGPU *, struct KernelNvlink * /*this*/); // virtual inherited (engstate) base (engstate)
@@ -618,8 +619,9 @@ NV_STATUS __nvoc_objCreate_KernelNvlink(KernelNvlink**, Dynamic*, NvU32);
#define knvlinkStateUnload(arg1, arg_this, arg3) knvlinkStateUnload_DISPATCH(arg1, arg_this, arg3)
#define knvlinkStatePostUnload_FNPTR(arg_this) arg_this->__nvoc_vtable->__knvlinkStatePostUnload__
#define knvlinkStatePostUnload(arg1, arg_this, arg3) knvlinkStatePostUnload_DISPATCH(arg1, arg_this, arg3)
#define knvlinkIsPresent_FNPTR(arg_this) arg_this->__nvoc_vtable->__knvlinkIsPresent__
#define knvlinkIsPresent_FNPTR(arg_this) arg_this->__knvlinkIsPresent__
#define knvlinkIsPresent(arg1, arg_this) knvlinkIsPresent_DISPATCH(arg1, arg_this)
#define knvlinkIsPresent_HAL(arg1, arg_this) knvlinkIsPresent_DISPATCH(arg1, arg_this)
#define knvlinkSetUniqueFabricBaseAddress_FNPTR(pKernelNvlink) pKernelNvlink->__knvlinkSetUniqueFabricBaseAddress__
#define knvlinkSetUniqueFabricBaseAddress(pGpu, pKernelNvlink, arg3) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg3)
#define knvlinkSetUniqueFabricBaseAddress_HAL(pGpu, pKernelNvlink, arg3) knvlinkSetUniqueFabricBaseAddress_DISPATCH(pGpu, pKernelNvlink, arg3)
@@ -769,7 +771,7 @@ static inline NV_STATUS knvlinkStatePostUnload_DISPATCH(struct OBJGPU *arg1, str
}
static inline NvBool knvlinkIsPresent_DISPATCH(struct OBJGPU *arg1, struct KernelNvlink *arg_this) {
return arg_this->__nvoc_vtable->__knvlinkIsPresent__(arg1, arg_this);
return arg_this->__knvlinkIsPresent__(arg1, arg_this);
}
static inline NV_STATUS knvlinkSetUniqueFabricBaseAddress_DISPATCH(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg3) {
@@ -1866,6 +1868,10 @@ NV_STATUS knvlinkStateUnload_IMPL(struct OBJGPU *arg1, struct KernelNvlink *arg2
NV_STATUS knvlinkStatePostUnload_IMPL(struct OBJGPU *arg1, struct KernelNvlink *arg2, NvU32 arg3);
static inline NvBool knvlinkIsPresent_3dd2c9(struct OBJGPU *arg1, struct KernelNvlink *arg2) {
return NV_FALSE;
}
NvBool knvlinkIsPresent_IMPL(struct OBJGPU *arg1, struct KernelNvlink *arg2);
NV_STATUS knvlinkSetUniqueFabricBaseAddress_GV100(struct OBJGPU *pGpu, struct KernelNvlink *pKernelNvlink, NvU64 arg3);

6
src/nvidia/generated/g_rpc_hal.h
View File

@@ -125,7 +125,7 @@ typedef NV_STATUS RpcCtrlGrSetCtxswPreemptionMode(POBJGPU, POBJRPC, NvHandl
typedef NV_STATUS RpcCtrlB0ccExecRegOps(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
typedef NV_STATUS RpcCtrlGrmgrGetGrFsInfo(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
typedef NV_STATUS RpcCtrlGetZbcClearTable(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC,
typedef NV_STATUS RpcCleanupSurface(POBJGPU, POBJRPC, NvHandle,
NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS*);
typedef NV_STATUS RpcCtrlSetTimeslice(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
typedef NV_STATUS RpcCtrlGpuQueryEccStatus(POBJGPU, POBJRPC, NvHandle, NvHandle, void*);
@@ -498,8 +498,8 @@ typedef struct RPC_HAL_IFACES {
(_pRpc)->_hal.rpcCtrlGrmgrGetGrFsInfo(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
#define rpcCtrlGetZbcClearTable_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
(_pRpc)->_hal.rpcCtrlGetZbcClearTable(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _pArg0) \
(_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _pArg0)
#define rpcCleanupSurface_HAL(_pGpu, _pRpc, _arg0, _pArg1) \
(_pRpc)->_hal.rpcCleanupSurface(_pGpu, _pRpc, _arg0, _pArg1)
#define rpcCtrlSetTimeslice_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \
(_pRpc)->_hal.rpcCtrlSetTimeslice(_pGpu, _pRpc, _arg0, _arg1, _pArg2)
#define rpcCtrlGpuQueryEccStatus_HAL(_pGpu, _pRpc, _arg0, _arg1, _pArg2) \

3
src/nvidia/inc/kernel/gpu/gpu_fabric_probe.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -78,5 +78,6 @@ NV_STATUS gpuFabricProbeReceivePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotif
NV_STATUS gpuFabricProbeReceiveUpdatePhysicalCallback(NvU32 gpuInstance, NvU64 *pNotifyGfIdMask,
NV2080_CTRL_NVLINK_INBAND_RECEIVED_DATA_PARAMS *pInbandRcvParams);
NV_STATUS gpuFabricProbeGetGfid(OBJGPU *pGpu, NvU32 *pGfid);
NvBool gpuFabricProbeIsInProgress(OBJGPU *pGpu);
#endif // GPU_FABRIC_PROBE_H

4
src/nvidia/inc/kernel/vgpu/rpc_vgpu.h
View File

@@ -85,12 +85,12 @@ static NV_INLINE void NV_RM_RPC_UPDATE_GPU_PDES(OBJGPU *pGpu, ...) { }
status = rpcSetSurfaceProperties_HAL(pGpu, pRpc, hClient, pParams, bSkipCompare); \
} while (0)
#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, status) \
#define NV_RM_RPC_CLEANUP_SURFACE(pGpu, hClient, pParams, status) \
do \
{ \
OBJRPC *pRpc = GPU_GET_RPC(pGpu); \
if ((status == NV_OK) && (pRpc != NULL)) \
status = rpcCleanupSurface_HAL(pGpu, pRpc, pParams); \
status = rpcCleanupSurface_HAL(pGpu, pRpc, hClient, pParams); \
} while (0)
#define NV_RM_RPC_SWITCH_TO_VGA(pGpu, status) \

2326
src/nvidia/interface/gsp_abi_check.c Normal file
View File

File diff suppressed because it is too large Load Diff

83
src/nvidia/interface/nvrm_registry.h
View File

@@ -57,16 +57,48 @@
#define NV_REG_STR_GLOBAL_SURFACE_OVERRIDE_RM_ENABLE 3:3
#define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT "RmDefaultTimeout"
//
// This regkey is experimental and may behave differently on specific platforms.
// DO NOT rely on it being a stable regkey to change all timeouts at once.
//
// Type Dword
// Change all RM internal timeouts to experiment with Bug 5203024.
//
// Some timeouts may still silently clamp to differnt min/max values and this
// regkey does NOT validate their range.
//
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT "RmOverrideInternalTimeoutsMs"
// Timeout value to set in milliseconds
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_VALUE_MS 23:0
// Same effect as setting "RmDefaultTimeout" to VALUE_MS
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_RM_DEFAULT_TIMEOUT 31:31
// Same effect as setting "RmWatchDogTimeOut" to VALUE_MS (converted to seconds)
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_RC_WATCHDOG_TIMEOUT 30:30
// Same effect as setting "RmEngineContextSwitchTimeoutUs" to VALUE_MS (converted to usec)
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_CTXSW_TIMEOUT 29:29
// Currently has no effect
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_VIDENG_TIMEOUT 28:28
// Currently has no effect
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_PMU_INTERNAL_TIMEOUT 27:27
// Currently has no effect
#define NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT_FLAGS_SET_FECS_WATCHDOG_TIMEOUT 26:26
//
// Type Dword
// Override default RM timeout. Measured in milliseconds.
// Not scaled for emulation
//
#define NV_REG_STR_RM_DEFAULT_TIMEOUT_MS "RmDefaultTimeout"
//
// Type Dword
// Override default RM timeout flags to either OSDELAY or OSTIMER.
//
#define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS "RmDefaultTimeoutFlags"
#define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSTIMER 4
#define NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT_FLAGS_OSDELAY 8
// Type Dword
// Override default RM timeout flags to either OSDELAY or OSTIMER.
#define NV_REG_STR_SUPPRESS_CLASS_LIST "SuppressClassList"
@@ -1328,6 +1360,33 @@
#define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_DISABLE 0x00000000
#define NV_REG_PROCESS_NONSTALL_INTR_IN_LOCKLESS_ISR_ENABLE 0x00000001
//
// Type: DWORD
// Sets the Initial runlist Context switch timeout value in base 2 microseconds
// (1024 nanosecond timer ticks).
// Default: 0x003fffff base2 usec ~ 4.3 seconds
//
// The lower 31 bits have these limits
// Min: 0x00000002
// Max: 0x7fffffff
// A value of 0 means CTXSW timeout is disabled entirely.
//
// It is possible for a privileged client to change this value for all engines
// using a ctrl call.
//
// If MSB (bit 31) is set, then the timeout value set will be "locked" and the
// ctrl call to change it will fail.
//
#define NV_REG_STR_RM_CTXSW_TIMEOUT "RmEngineContextSwitchTimeoutUs"
#define NV_REG_STR_RM_CTXSW_TIMEOUT_DEFAULT 0x003fffff
#define NV_REG_STR_RM_CTXSW_TIMEOUT_TIME 30:0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_TIME_DISABLE 0x00000000
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK 31:31
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK_FALSE 0x0
#define NV_REG_STR_RM_CTXSW_TIMEOUT_LOCK_TRUE 0x1
#define NV_REG_STR_RM_ROBUST_CHANNELS "RmRobustChannels"
#define NV_REG_STR_RM_ROBUST_CHANNELS_ENABLE 0x00000001
#define NV_REG_STR_RM_ROBUST_CHANNELS_DISABLE 0x00000000
@@ -2498,6 +2557,12 @@
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_DISABLE 0x00000000
#define NV_REG_STR_RM_FORCE_GR_SCRUBBER_CHANNEL_ENABLE 0x00000001
// Type DWORD
// Allows extending PMU FB Operationg Timeout (DMA / FBFlush) on certain profiles
// This currently takes effect on GB10X profile only
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US "RmPmuFBTimeoutUs"
#define NV_REG_STR_RM_PMU_FB_TIMEOUT_US_DEFAULT (0)
//
// Type: Dword
//
@@ -2610,4 +2675,16 @@
#define NV_REG_STR_RM_WAR_5045021_DISABLE 0x00000000
#define NV_REG_STR_RM_WAR_5045021_DEFAULT 0x00000000
//
// Type: DWORD
// Regkey to enable/disable FB sanity check after FSP secure boot complete
// _ENABLE: Enable FB sanity check
// _DISABLE: Disable FB sanity check
// default is _DISABLE
//
#define NV_REG_STR_RM_FB_SANITY_CHECK "RmFbSanityCheck"
#define NV_REG_STR_RM_FB_SANITY_CHECK_ENABLE (0x00000001)
#define NV_REG_STR_RM_FB_SANITY_CHECK_DISABLE (0x00000000)
#define NV_REG_STR_RM_FB_SANITY_CHECK_DEFAULT NV_REG_STR_RM_FB_SANITY_CHECK_DISABLE
#endif // NVRM_REGISTRY_H

39
src/nvidia/src/kernel/diagnostics/gpu_acct.c
View File

@@ -38,7 +38,7 @@ static NvU64 gpuacctGetCurrTime(void);
static NV_STATUS gpuacctAddProcEntry(GPU_ACCT_PROC_DATA_STORE *, GPUACCT_PROC_ENTRY *, NvBool);
static NV_STATUS gpuacctRemoveProcEntry(GPU_ACCT_PROC_DATA_STORE *, GPUACCT_PROC_ENTRY *);
static NV_STATUS gpuacctLookupProcEntry(GPU_ACCT_PROC_DATA_STORE *, NvU32, GPUACCT_PROC_ENTRY **);
static NV_STATUS gpuacctAllocProcEntry(GPU_ACCT_PROC_DATA_STORE *, NvU32, NvU32, RmClient *, GPUACCT_PROC_ENTRY **);
static NV_STATUS gpuacctAllocProcEntry(GPU_ACCT_PROC_DATA_STORE *, NvU32, NvU32, GPUACCT_PROC_ENTRY **);
static NV_STATUS gpuacctFreeProcEntry(GPU_ACCT_PROC_DATA_STORE *, GPUACCT_PROC_ENTRY *);
static NV_STATUS gpuacctCleanupDataStore(GPU_ACCT_PROC_DATA_STORE *);
static NV_STATUS gpuacctDestroyDataStore(GPU_ACCT_PROC_DATA_STORE *);
@@ -218,7 +218,6 @@ void gpuacctDestruct_IMPL
* @param[in] pDS Pointer to data store where process entry is to be added.
* @param[in] pid PID of the process.
* @param[in] procType Type of the process.
* @param[in] pClient Process RmClient
* @param[out] ppEntry Pointer to process entry.
*
* @return NV_OK
@@ -233,7 +232,6 @@ gpuacctAllocProcEntry
GPU_ACCT_PROC_DATA_STORE *pDS,
NvU32 pid,
NvU32 procType,
RmClient *pClient,
GPUACCT_PROC_ENTRY **ppEntry
)
{
@@ -252,7 +250,6 @@ gpuacctAllocProcEntry
pEntry->procId = pid;
pEntry->procType = procType;
pEntry->pClient = pClient;
status = gpuacctAddProcEntry(pDS, pEntry, NV_TRUE);
if (status != NV_OK)
@@ -653,8 +650,7 @@ gpuacctStartGpuAccounting_IMPL
GpuAccounting *pGpuAcct,
NvU32 gpuInstance,
NvU32 pid,
NvU32 subPid,
RmClient *pClient
NvU32 subPid
)
{
OBJGPU *pGpu;
@@ -713,7 +709,7 @@ gpuacctStartGpuAccounting_IMPL
// Create entry for the incoming pid.
status = gpuacctAllocProcEntry(pDS, searchPid,
NV_GPUACCT_PROC_TYPE_CPU, pClient, &pEntry);
NV_GPUACCT_PROC_TYPE_CPU, &pEntry);
NV_ASSERT_OR_RETURN(status == NV_OK, status);
NV_ASSERT_OR_RETURN(pEntry != NULL, NV_ERR_NO_MEMORY);
@@ -866,7 +862,6 @@ gpuacctStopGpuAccounting_IMPL
}
// Move the entry to dead procs data store
pEntry->pClient = NULL;
status = gpuacctRemoveProcEntry(pLiveDS, pEntry);
if (status != NV_OK)
{
@@ -1201,25 +1196,6 @@ gpuacctGetProcAcctInfo_IMPL
return NV_OK;
}
static NV_STATUS _gpuAcctGetPidValue(GPUACCT_PROC_ENTRY *pEntry, NvU32 vmIndex, NvU32 *nsPid)
{
if ((vmIndex != NV_INVALID_VM_INDEX) ||
(pEntry->pClient == NULL) ||
(pEntry->pClient->pOsPidInfo == NULL))
{
*nsPid = pEntry->procId;
}
else
{
if (osFindNsPid(pEntry->pClient->pOsPidInfo, nsPid) != NV_OK)
{
return NV_ERR_OBJECT_NOT_FOUND;
}
}
return NV_OK;
}
/*!
* Gets all the pids for which accounting data is available.
*
@@ -1239,7 +1215,6 @@ gpuacctGetAcctPids_IMPL
{
GPUACCT_PROC_ENTRY *pEntry;
GPU_ACCT_PROC_LIST *pList;
NV_STATUS status;
OBJGPU *pGpu;
NvU32 count;
NvU32 vmPid;
@@ -1292,7 +1267,7 @@ gpuacctGetAcctPids_IMPL
if (vmIndex == NV_INVALID_VM_INDEX)
{
// Skip dead info if the request is for baremetal and from container.
// Skip dead info if the requester is not from root namespace.
if (osIsInitNs() != NV_TRUE)
{
goto addLiveProc;
@@ -1333,11 +1308,7 @@ addLiveProc:
pEntry = iter.pValue;
if (pEntry && pEntry->procType == NV_GPUACCT_PROC_TYPE_GPU)
{
status = _gpuAcctGetPidValue(pEntry, vmIndex, &pParams->pidTbl[count]);
if (status == NV_OK)
{
count++;
}
pParams->pidTbl[count++] = pEntry->procId;
}
}

2
src/nvidia/src/kernel/gpu/conf_compute/ccsl.c
View File

@@ -447,6 +447,7 @@ ccslContextInitViaChannel_IMPL
}
*ppCtx = pCtx;
pCtx->msgCounterSize = CSL_MSG_CTR_32;
pCtx->openrmCtx = NULL;
pCtx->pDecryptBundles = NULL;
@@ -505,7 +506,6 @@ ccslContextInitViaChannel_IMPL
pCtx->pEncStatsBuffer = pKernelChannel->pEncStatsBuf;
pCtx->pMemDesc = pMemDesc;
pCtx->msgCounterSize = CSL_MSG_CTR_32;
// Set values only used for GSP keys to invalid
pCtx->globalKeyIdIn = CC_GKEYID_GEN(CC_KEYSPACE_SIZE, 0);

2
src/nvidia/src/kernel/gpu/device.c
View File

@@ -431,7 +431,7 @@ _deviceInit
// If gpuacctStartGpuAccounting() fails, just assert and print error.
// gpuacctStartGpuAccounting() is not a major failure, we will continue with deviceInit() as normal.
if ((pRsClient->type == CLIENT_TYPE_USER) && (gpuacctStartGpuAccounting(pGpuAcct,
pGpu->gpuInstance, pClient->ProcID, pClient->SubProcessID, pClient) != NV_OK))
pGpu->gpuInstance, pClient->ProcID, pClient->SubProcessID) != NV_OK))
{
NV_ASSERT(0);
NV_PRINTF(LEVEL_ERROR,

2
src/nvidia/src/kernel/gpu/fsp/arch/blackwell/kern_fsp_gb202.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a

3
src/nvidia/src/kernel/gpu/fsp/kern_fsp.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -154,6 +154,7 @@ kfspInitRegistryOverrides
"during boot is disabled using the regkey.\n");
pKernelFsp->setProperty(pKernelFsp, PDB_PROP_KFSP_FSP_FUSE_ERROR_CHECK_ENABLED, NV_FALSE);
}
}
void

5
src/nvidia/src/kernel/gpu/gpu.c
View File

@@ -2077,6 +2077,11 @@ gpuStatePreInit_IMPL
"engine removal in PreInit with NV_ERR_NOT_SUPPORTED is deprecated (%s)\n",
engstateGetName(pEngstate));
break;
case ENG_HDACODEC:
NV_PRINTF(LEVEL_WARNING,
"engine removal in PreInit with NV_ERR_NOT_SUPPORTED is deprecated (%s)\n",
engstateGetName(pEngstate));
break;
default:
NV_PRINTF(LEVEL_ERROR,
"disallowing NV_ERR_NOT_SUPPORTED PreInit removal of untracked engine (%s)\n",

27
src/nvidia/src/kernel/gpu/gpu_timeout.c
View File

@@ -105,11 +105,32 @@ timeoutRegistryOverride
{
NvU32 data32 = 0;
NvU32 bug5203024OverrideTimeouts = (
(osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT,
&data32) == NV_OK) ?
data32 :
0);
NvBool bOverrideDefaultTimeout = (DRF_VAL(_REG_STR,
_RM_BUG5203024_OVERRIDE_TIMEOUT,
_FLAGS_SET_RM_DEFAULT_TIMEOUT,
bug5203024OverrideTimeouts) == 1);
// Override timeout value
if ((osReadRegistryDword(pGpu,
NV_REG_STR_RM_OVERRIDE_DEFAULT_TIMEOUT,
&data32) == NV_OK) && (data32 != 0))
if (bOverrideDefaultTimeout ||
((osReadRegistryDword(pGpu,
NV_REG_STR_RM_DEFAULT_TIMEOUT_MS,
&data32) == NV_OK) &&
(data32 != 0)))
{
if (bOverrideDefaultTimeout)
{
data32 = DRF_VAL(_REG_STR,
_RM_BUG5203024_OVERRIDE_TIMEOUT,
_VALUE_MS,
bug5203024OverrideTimeouts);
}
// Handle 32-bit overflow.
if (data32 > (NV_U32_MAX / 1000))
{

22
src/nvidia/src/kernel/gpu/gr/kernel_graphics.c
View File

@@ -345,6 +345,15 @@ kgraphicsStateLoad_IMPL
{
KernelGraphicsManager *pKernelGraphicsManager = GPU_GET_KERNEL_GRAPHICS_MANAGER(pGpu);
if (IS_VIRTUAL_WITH_SRIOV(pGpu))
{
//
// Force initialize scratch registers
// so won't read back X and assert in RTL
//
kgraphicsSetFecsTraceHwEnable_HAL(pGpu, pKernelGraphics, NV_FALSE);
}
if (fecsGetCtxswLogConsumerCount(pGpu, pKernelGraphicsManager) > 0)
{
fecsBufferMap(pGpu, pKernelGraphics);
@@ -4229,11 +4238,18 @@ subdeviceCtrlCmdGrInternalSetFecsTraceWrOffset_IMPL
NvBool kgraphicsIsCtxswLoggingEnabled_FWCLIENT(OBJGPU *pGpu, KernelGraphics *pKernelGraphics)
{
RUSD_GR_INFO grInfo;
NvBool bEnabled = NV_FALSE;
RUSD_READ_DATA((NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer), grInfo, &grInfo);
pKernelGraphics->bCtxswLoggingEnabled = grInfo.bCtxswLoggingEnabled;
// Skip on CC
if (pGpu->userSharedData.pMapBuffer != NULL)
{
RUSD_GR_INFO grInfo;
RUSD_READ_DATA((NV00DE_SHARED_DATA*)(pGpu->userSharedData.pMapBuffer), grInfo, &grInfo);
bEnabled = grInfo.bCtxswLoggingEnabled;
}
pKernelGraphics->bCtxswLoggingEnabled = bEnabled;
return pKernelGraphics->bCtxswLoggingEnabled;
}

12
src/nvidia/src/kernel/gpu/gr/kernel_graphics_manager.c
View File

@@ -805,11 +805,21 @@ kgrmgrGetVeidSizePerSpan_IMPL
NvU32 *pVeidSizePerSpan
)
{
KernelMIGManager *pKernelMIGManager = GPU_GET_KERNEL_MIG_MANAGER(pGpu);
NV2080_CTRL_INTERNAL_MIGMGR_COMPUTE_PROFILE computeProfile;
NvU32 computeSize;
NV_ASSERT_OR_RETURN(pVeidSizePerSpan != NULL, NV_ERR_INVALID_ARGUMENT);
computeSize = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager);
NV_CHECK_OR_RETURN(LEVEL_ERROR, computeSize != KMIGMGR_COMPUTE_SIZE_INVALID, NV_ERR_INVALID_STATE);
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
kmigmgrGetComputeProfileFromSize(pGpu, pKernelMIGManager, computeSize, &computeProfile));
// VEIDs for each span should be the VEID size we assign to the smallest GPC count
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
kgrmgrGetVeidsFromGpcCount_HAL(pGpu, pKernelGraphicsManager, 1, pVeidSizePerSpan));
kgrmgrGetVeidsFromGpcCount_HAL(pGpu, pKernelGraphicsManager, computeProfile.gpcCount, pVeidSizePerSpan));
return NV_OK;
}

7
src/nvidia/src/kernel/gpu/mig_mgr/arch/blackwell/kmigmgr_gb202.c
View File

@@ -131,11 +131,10 @@ kmigmgrIsGPUInstanceCombinationValid_GB202
return NV_FALSE;
}
NV_CHECK_OR_RETURN(LEVEL_ERROR,
kmigmgrGetSmallestGpuInstanceSize(pGpu, pKernelMIGManager, &smallestComputeSizeFlag) == NV_OK,
NV_FALSE);
smallestComputeSizeFlag = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager);
NV_CHECK_OR_RETURN(LEVEL_ERROR, smallestComputeSizeFlag != KMIGMGR_COMPUTE_SIZE_INVALID, NV_FALSE);
// JPG_OFA profile is only available on the smallest partition
// JPG_OFA profile is only available on the smallest available partition
if (FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA, _ENABLE, gpuInstanceFlag))
{
if (computeSizeFlag != smallestComputeSizeFlag)

7
src/nvidia/src/kernel/gpu/mig_mgr/arch/hopper/kmigmgr_gh100.c
View File

@@ -122,11 +122,10 @@ kmigmgrIsGPUInstanceCombinationValid_GH100
return NV_FALSE;
}
NV_CHECK_OR_RETURN(LEVEL_ERROR,
kmigmgrGetSmallestGpuInstanceSize(pGpu, pKernelMIGManager, &smallestComputeSizeFlag) == NV_OK,
NV_FALSE);
smallestComputeSizeFlag = kmigmgrSmallestComputeProfileSize(pGpu, pKernelMIGManager);
NV_CHECK_OR_RETURN(LEVEL_ERROR, smallestComputeSizeFlag != KMIGMGR_COMPUTE_SIZE_INVALID, NV_FALSE);
// JPG_OFA profile is only available on the smallest partition
// JPG_OFA profile is only available on the smallest available partition
if (FLD_TEST_REF(NV2080_CTRL_GPU_PARTITION_FLAG_REQ_DEC_JPG_OFA, _ENABLE, gpuInstanceFlag))
{
if (computeSizeFlag != smallestComputeSizeFlag)

21
src/nvidia/src/kernel/gpu/mig_mgr/kernel_mig_manager.c
View File

@@ -8115,6 +8115,7 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL
MIG_INSTANCE_REF ref;
NvU32 entryCount;
NvU32 i;
NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO giProfile;
if (!IS_MIG_ENABLED(pGpu))
return NV_ERR_INVALID_STATE;
@@ -8131,16 +8132,16 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL
{
maxSmCount = ref.pKernelMIGGpuInstance->pProfile->smCount;
maxPhysicalSlotCount = ref.pKernelMIGGpuInstance->pProfile->virtualGpcCount;
portMemCopy(&giProfile, sizeof(giProfile), ref.pKernelMIGGpuInstance->pProfile, sizeof(giProfile));
}
else
{
NV2080_CTRL_INTERNAL_MIGMGR_PROFILE_INFO profile;
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
kmigmgrGetGpuProfileFromFlag(pGpu, pKernelMIGManager, pParams->partitionFlag, &profile));
kmigmgrGetGpuProfileFromFlag(pGpu, pKernelMIGManager, pParams->partitionFlag, &giProfile));
maxSmCount = profile.smCount;
maxPhysicalSlotCount = profile.virtualGpcCount;
maxSmCount = giProfile.smCount;
maxPhysicalSlotCount = giProfile.virtualGpcCount;
}
NV_CHECK_OR_RETURN(LEVEL_ERROR, pStaticInfo != NULL, NV_ERR_INVALID_STATE);
@@ -8150,6 +8151,8 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL
entryCount = 0;
for (i = 0; i < pStaticInfo->pCIProfiles->profileCount; i++)
{
NVC637_CTRL_EXEC_PARTITIONS_GET_PROFILE_CAPACITY_PARAMS params = {0};
if ((pStaticInfo->pCIProfiles->profiles[i].smCount > maxSmCount) ||
(pStaticInfo->pCIProfiles->profiles[i].physicalSlots > maxPhysicalSlotCount))
{
@@ -8163,7 +8166,15 @@ subdeviceCtrlCmdGpuGetComputeProfiles_IMPL
(pParams->profiles[entryCount - 1].gpcCount == pStaticInfo->pCIProfiles->profiles[i].gpcCount) &&
(pParams->profiles[entryCount - 1].smCount == pStaticInfo->pCIProfiles->profiles[i].smCount))
{
continue;
continue;
}
params.computeSize = pStaticInfo->pCIProfiles->profiles[i].computeSize;
NV_CHECK_OK_OR_RETURN(LEVEL_ERROR,
kmigmgrComputeProfileGetCapacity(pGpu, pKernelMIGManager, &giProfile, NULL, &params));
if (params.totalProfileCount == 0)
{
continue;
}
pParams->profiles[entryCount].computeSize = pStaticInfo->pCIProfiles->profiles[i].computeSize;

24
src/nvidia/src/kernel/gpu/rc/kernel_rc.c
View File

@@ -135,7 +135,6 @@ _krcInitRegistryOverrides
pKernelRc->bBreakOnRc = NV_TRUE;
}
if (osReadRegistryDword(pGpu,
NV_REG_STR_RM_WATCHDOG_TIMEOUT,
&pKernelRc->watchdogPersistent.timeoutSecs) !=
@@ -145,6 +144,29 @@ _krcInitRegistryOverrides
pKernelRc->watchdogPersistent.timeoutSecs =
NV_REG_STR_RM_WATCHDOG_TIMEOUT_DEFAULT;
}
NvU32 data32 = 0;
NvU32 bug5203024OverrideTimeouts = (
(osReadRegistryDword(pGpu, NV_REG_STR_RM_BUG5203024_OVERRIDE_TIMEOUT,
&data32) == NV_OK) ?
data32 :
0);
NvBool bOverrideWatchdogTimeout = (DRF_VAL(_REG_STR,
_RM_BUG5203024_OVERRIDE_TIMEOUT,
_FLAGS_SET_RC_WATCHDOG_TIMEOUT,
bug5203024OverrideTimeouts) ==
1);
if (bOverrideWatchdogTimeout)
{
pKernelRc->watchdogPersistent.timeoutSecs =
DRF_VAL(_REG_STR, _RM_BUG5203024_OVERRIDE_TIMEOUT, _VALUE_MS,
bug5203024OverrideTimeouts) / 1000;
NV_PRINTF(LEVEL_NOTICE, "RC Watchdog timeout forced to %d seconds.\n",
pKernelRc->watchdogPersistent.timeoutSecs);
}
if (osReadRegistryDword(pGpu,
NV_REG_STR_RM_WATCHDOG_INTERVAL,
&pKernelRc->watchdogPersistent.intervalSecs) !=

10
src/nvidia/src/kernel/gpu/rc/kernel_rc_watchdog.c
View File

@@ -29,6 +29,7 @@
#include "kernel/gpu/mig_mgr/kernel_mig_manager.h"
#include "kernel/gpu/rc/kernel_rc.h"
#include "kernel/gpu/bif/kernel_bif.h"
#include "kernel/gpu/bus/kern_bus.h"
#include "kernel/os/os.h"
#include "platform/sli/sli.h"
@@ -1389,6 +1390,15 @@ krcWatchdogInitPushbuffer_IMPL
SLI_LOOP_START(SLI_LOOP_FLAGS_NONE);
{
//
// On some architectures, if doorbell is mapped via bar0, we need to send
// an extra flush
//
if (kbusFlushPcieForBar0Doorbell_HAL(pGpu, GPU_GET_KERNEL_BUS(pGpu)) != NV_OK)
{
NV_PRINTF(LEVEL_ERROR, "Busflush failed.\n");
return;
}
kfifoUpdateUsermodeDoorbell_HAL(pGpu, GPU_GET_KERNEL_FIFO(pGpu),
pKernelRc->watchdog.notifierToken->info32,
pKernelRc->watchdog.runlistId);

6
src/nvidia/src/kernel/vgpu/rpc.c
View File

@@ -8341,7 +8341,8 @@ done:
return status;
}
NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams)
NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NvHandle hClient,
NVA080_CTRL_VGPU_DISPLAY_CLEANUP_SURFACE_PARAMS *pParams)
{
NV_STATUS status = NV_OK;
OBJVGPU *pVgpu = GPU_GET_VGPU(pGpu);
@@ -8352,7 +8353,8 @@ NV_STATUS rpcCleanupSurface_v03_00(OBJGPU *pGpu, OBJRPC *pRpc, NVA080_CTRL_VGPU_
if (pVgpu && !pVgpu->bVncSupported)
return status;
if (pVgpu && (pVgpu->last_surface_info.last_surface.headIndex == pParams->headIndex))
if (pVgpu && (pVgpu->last_surface_info.last_surface.headIndex == pParams->headIndex) &&
(pVgpu->last_surface_info.hClient == hClient))
{
/* remove last surface information */
portMemSet((void *)&(pVgpu->last_surface_info), 0, sizeof (pVgpu->last_surface_info));

2
src/nvidia/src/kernel/vgpu/vgpuctrl.c
View File

@@ -108,7 +108,7 @@ vgpuapiCtrlCmdVgpuDisplayCleanupSurface_IMPL
OBJGPU *pGpu = GPU_RES_GET_GPU(pVgpuApi);
NV_STATUS rmStatus = NV_OK;
NV_RM_RPC_CLEANUP_SURFACE(pGpu, pParams, rmStatus);
NV_RM_RPC_CLEANUP_SURFACE(pGpu, RES_GET_CLIENT_HANDLE(pVgpuApi), pParams, rmStatus);
return rmStatus;
}

1
src/nvidia/srcs.mk
View File

@@ -319,6 +319,7 @@ SRCS += interface/deprecated/rmapi_deprecated_misc.c
SRCS += interface/deprecated/rmapi_deprecated_utils.c
SRCS += interface/deprecated/rmapi_deprecated_vidheapctrl.c
SRCS += interface/deprecated/rmapi_gss_legacy_control.c
SRCS += interface/gsp_abi_check.c
SRCS += interface/rmapi/src/g_finn_rm_api.c
SRCS += src/kernel/compute/fabric.c
SRCS += src/kernel/compute/fm_session_api.c