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550.120

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This commit is contained in:
Andy Ritger
2024-09-20 12:40:39 -07:00
parent 2cca8b3fd5
commit 5e52edb203
93 changed files with 1186 additions and 712 deletions
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20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r552_86
#define NV_BUILD_BRANCH r550_00
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r552_86
#define NV_PUBLIC_BRANCH r550_00
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r552_86-355"
#define NV_BUILD_CHANGELIST_NUM (34618165)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r550/r550_00-410"
#define NV_BUILD_CHANGELIST_NUM (34843164)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r550/r552_86-355"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34618165)
#define NV_BUILD_NAME "rel/gpu_drv/r550/r550_00-410"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34843164)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r552_86-1"
#define NV_BUILD_CHANGELIST_NUM (34615400)
#define NV_BUILD_BRANCH_VERSION "r550_00-390"
#define NV_BUILD_CHANGELIST_NUM (34843164)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "552.87"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34615400)
#define NV_BUILD_NAME "553.09"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34843164)
#define NV_BUILD_BRANCH_BASE_VERSION R550
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
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@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "550.107.02"
#define NV_VERSION_STRING "550.120"
#else

3
src/common/inc/swref/published/nvswitch/ls10/ptop_discovery_ip.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -25,4 +25,5 @@
#define __ls10_ptop_discovery_ip_h__
/* This file is autogenerated. Do not edit */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SAW_0 0x00028000 /* */
#define NV_PTOP_UNICAST_SW_DEVICE_BASE_SOE_0 0x00840000 /* */
#endif // __ls10_ptop_discovery_ip_h__

90
src/common/nvswitch/common/inc/soe/soeiftnvl.h
View File

@@ -34,6 +34,78 @@
* Command Messages between driver and TNVL unit of SOE
*/
#define RM_SOE_LIST_LS10_ONLY_ENGINES(_op) \
_op(GIN) \
_op(XAL) \
_op(XAL_FUNC) \
_op(XPL) \
_op(XTL) \
_op(XTL_CONFIG) \
_op(UXL) \
_op(GPU_PTOP) \
_op(PMC) \
_op(PBUS) \
_op(ROM2) \
_op(GPIO) \
_op(FSP) \
_op(SYSCTRL) \
_op(CLKS_SYS) \
_op(CLKS_SYSB) \
_op(CLKS_P0) \
_op(SAW_PM) \
_op(PCIE_PM) \
_op(PRT_PRI_HUB) \
_op(PRT_PRI_RS_CTRL) \
_op(SYS_PRI_HUB) \
_op(SYS_PRI_RS_CTRL) \
_op(SYSB_PRI_HUB) \
_op(SYSB_PRI_RS_CTRL) \
_op(PRI_MASTER_RS) \
_op(PTIMER) \
_op(CPR) \
_op(TILEOUT) \
#define RM_SOE_LIST_ALL_ENGINES(_op) \
_op(XVE) \
_op(SAW) \
_op(SOE) \
_op(SMR) \
\
_op(NPG) \
_op(NPORT) \
\
_op(NVLW) \
_op(MINION) \
_op(NVLIPT) \
_op(NVLIPT_LNK) \
_op(NVLTLC) \
_op(NVLDL) \
\
_op(NXBAR) \
_op(TILE) \
\
_op(NPG_PERFMON) \
_op(NPORT_PERFMON) \
\
_op(NVLW_PERFMON) \
#define RM_SOE_ENGINE_ID_LIST(_eng) \
RM_SOE_ENGINE_ID_##_eng,
//
// ENGINE_IDs are the complete list of all engines that are supported on
// LS10 architecture(s) that may support them. Any one architecture may or
// may not understand how to operate on any one specific engine.
// Architectures that share a common ENGINE_ID are not guaranteed to have
// compatible manuals.
//
typedef enum rm_soe_engine_id
{
RM_SOE_LIST_ALL_ENGINES(RM_SOE_ENGINE_ID_LIST)
RM_SOE_LIST_LS10_ONLY_ENGINES(RM_SOE_ENGINE_ID_LIST)
RM_SOE_ENGINE_ID_SIZE,
} RM_SOE_ENGINE_ID;
/*!
* Commands offered by the SOE Tnvl Interface.
*/
@@ -47,6 +119,10 @@ enum
* Issue pre-lock sequence
*/
RM_SOE_TNVL_CMD_ISSUE_PRE_LOCK_SEQUENCE = 0x1,
/*
* Issue engine write command
*/
RM_SOE_TNVL_CMD_ISSUE_ENGINE_WRITE = 0x2,
};
/*!
@@ -60,6 +136,17 @@ typedef struct
NvU32 data;
} RM_SOE_TNVL_CMD_REGISTER_WRITE;
typedef struct
{
NvU8 cmdType;
RM_SOE_ENGINE_ID eng_id;
NvU32 eng_bcast;
NvU32 eng_instance;
NvU32 base;
NvU32 offset;
NvU32 data;
} RM_SOE_TNVL_CMD_ENGINE_WRITE;
typedef struct
{
NvU8 cmdType;
@@ -69,8 +156,9 @@ typedef union
{
NvU8 cmdType;
RM_SOE_TNVL_CMD_REGISTER_WRITE registerWrite;
RM_SOE_TNVL_CMD_ENGINE_WRITE engineWrite;
RM_SOE_TNVL_CMD_PRE_LOCK_SEQUENCE preLockSequence;
} RM_SOE_TNVL_CMD;
#endif // _SOEIFTNVL_H_
#endif // _SOETNVL_H_

3
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -831,6 +831,7 @@ typedef enum nvswitch_err_type
NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007,
NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008,
NVSWITCH_ERR_HW_HOST_FIRMWARE_RECOVERY_MODE = 10009,
NVSWITCH_ERR_HW_HOST_TNVL_ERROR = 10010,
NVSWITCH_ERR_HW_HOST_LAST,

1
src/common/nvswitch/kernel/inc/haldef_nvswitch.h
View File

@@ -213,6 +213,7 @@
_op(NvU32, nvswitch_get_eng_count, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast), _arch) \
_op(NvU32, nvswitch_eng_rd, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 offset), _arch) \
_op(void, nvswitch_eng_wr, (nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 offset, NvU32 data), _arch) \
_op(void, nvswitch_reg_write_32, (nvswitch_device *device, NvU32 offset, NvU32 data), _arch) \
_op(NvU32, nvswitch_get_link_eng_inst, (nvswitch_device *device, NvU32 link_id, NVSWITCH_ENGINE_ID eng_id), _arch) \
_op(void *, nvswitch_alloc_chipdevice, (nvswitch_device *device), _arch) \
_op(NvlStatus, nvswitch_init_thermal, (nvswitch_device *device), _arch) \

8
src/common/nvswitch/kernel/inc/ls10/ls10.h
View File

@@ -189,8 +189,8 @@
#define SOE_VBIOS_VERSION_MASK 0xFF0000
#define SOE_VBIOS_REVLOCK_DISABLE_NPORT_FATAL_INTR 0x370000
#define SOE_VBIOS_REVLOCK_ISSUE_INGRESS_STOP 0x4C0000
#define SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE 0x580000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x600000
#define SOE_VBIOS_REVLOCK_TNVL_PRELOCK_COMMAND 0x590000
#define SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS 0x610000
// LS10 Saved LED state
#define ACCESS_LINK_LED_STATE CPLD_MACHXO3_ACCESS_LINK_LED_CTL_NVL_CABLE_LED
@@ -1060,10 +1060,10 @@ NvlStatus nvswitch_tnvl_get_attestation_certificate_chain_ls10(nvswitch_device *
NvlStatus nvswitch_tnvl_get_attestation_report_ls10(nvswitch_device *device, NVSWITCH_GET_ATTESTATION_REPORT_PARAMS *params);
NvlStatus nvswitch_tnvl_send_fsp_lock_config_ls10(nvswitch_device *device);
NvlStatus nvswitch_tnvl_get_status_ls10(nvswitch_device *device, NVSWITCH_GET_TNVL_STATUS_PARAMS *params);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
void nvswitch_tnvl_eng_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
NvlStatus nvswitch_send_tnvl_prelock_cmd_ls10(nvswitch_device *device);
void nvswitch_tnvl_disable_interrupts_ls10(nvswitch_device *device);
void nvswitch_tnvl_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
NvlStatus nvswitch_ctrl_get_soe_heartbeat_ls10(nvswitch_device *device, NVSWITCH_GET_SOE_HEARTBEAT_PARAMS *p);
NvlStatus nvswitch_cci_enable_iobist_ls10(nvswitch_device *device, NvU32 linkNumber, NvBool bEnable);
NvlStatus nvswitch_cci_initialization_sequence_ls10(nvswitch_device *device, NvU32 linkNumber);

1
src/common/nvswitch/kernel/inc/ls10/soe_ls10.h
View File

@@ -52,4 +52,5 @@ void nvswitch_soe_disable_nport_fatal_interrupts_ls10(nvswitch_device *devi
NvU32 nportIntrEnable, NvU8 nportIntrType);
NvlStatus nvswitch_soe_issue_ingress_stop_ls10(nvswitch_device *device, NvU32 nport, NvBool bStop);
NvlStatus nvswitch_soe_reg_wr_32_ls10(nvswitch_device *device, NvU32 offset, NvU32 data);
NvlStatus nvswitch_soe_eng_wr_32_ls10(nvswitch_device *device, NVSWITCH_ENGINE_ID eng_id, NvU32 eng_bcast, NvU32 eng_instance, NvU32 base_addr, NvU32 offset, NvU32 data);
#endif //_SOE_LS10_H_

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_dbg.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_dbg[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x1de66f4b, 0x98838b38, 0xce342fcf, 0x31422bca,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x154ee848, 0x4d419617, 0xc10ab5e0, 0x5570cfeb,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

8
src/common/nvswitch/kernel/inc/soe/bin/g_soeuc_lr10_prd.h
View File

@@ -272,8 +272,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0xa6b0001d, 0x240cf409, 0x001da03e, 0x0049190f, 0x009ff711, 0x00f802f8, 0xb50294b6, 0x00f804b9,
0xb602af92, 0xb9bc0294, 0xf400f8f9, 0x82f9d430, 0x301590b4, 0xc1b027e1, 0x0ad1b00b, 0x94b6f4bd,
0x0c91b002, 0x900149fe, 0x9fa04499, 0x20079990, 0x0b99929f, 0x95b29fa0, 0xa0049992, 0x9297b29f,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x14bde9a0,
0x34bd84bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0x9fa00499, 0x0005ecdf, 0x90ffbf00, 0x4efe1499, 0xa0a6b201, 0x34ee909f, 0xb4b20209, 0x84bde9a0,
0x14bd34bd, 0x001eef3e, 0x277e6ab2, 0x49bf001a, 0x4bfea2b2, 0x014cfe01, 0x9044bb90, 0x95f94bcc,
0xb31100b4, 0x008e0209, 0x9e0309b3, 0x010db300, 0x499800a8, 0xb27cb201, 0xfe5bb22a, 0xdd90014d,
0x3295f938, 0x0be0b40c, 0xa53ed4bd, 0x5fbf001e, 0xf9a6e9bf, 0x34381bf4, 0xe89827b0, 0x987fbf01,
0xb03302e9, 0xb0b40a00, 0x90b9bc0c, 0x1bf4f9a6, 0x1444df1e, 0xf9180000, 0x0094330c, 0x90f1b206,
@@ -2269,8 +2269,8 @@ const NvU32 soe_ucode_data_lr10_prd[] = {
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x1de66f4b, 0x98838b38, 0xce342fcf, 0x31422bca,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x154ee848, 0x4d419617, 0xc10ab5e0, 0x5570cfeb,
0x69e9060c, 0xe6ca2d91, 0xac20edf2, 0xeafeafcc, 0x294f2cc2, 0x883a9d68, 0x493e2990, 0xc8e27d59,
0x30867660, 0xbc4af25f, 0xbc09e1ed, 0xab87e0fc, 0x8fc5fac6, 0xe1f366be, 0x1ec159bf, 0x352ff984,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,

28
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@@ -1329,6 +1329,13 @@ nvswitch_corelib_set_tl_link_mode_lr10
nvswitch_device *device = link->dev->pDevInfo;
NvlStatus status = NVL_SUCCESS;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (!NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,
@@ -1728,6 +1735,13 @@ nvswitch_corelib_set_rx_mode_lr10
NvlStatus status = NVL_SUCCESS;
NvU32 delay_ns;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (!NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLDL, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,
@@ -1955,6 +1969,13 @@ nvswitch_corelib_set_rx_detect_lr10
NvlStatus status;
nvswitch_device *device = link->dev->pDevInfo;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (nvswitch_does_link_need_termination_enabled(device, link))
{
NVSWITCH_PRINT(device, INFO,
@@ -2094,6 +2115,13 @@ nvswitch_request_tl_link_state_lr10
NvlStatus status = NVL_SUCCESS;
NvU32 linkStatus;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (!NVSWITCH_IS_LINK_ENG_VALID_LR10(device, NVLIPT_LNK, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,

20
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -8204,6 +8204,26 @@ nvswitch_tnvl_disable_interrupts_lr10
return;
}
void
nvswitch_reg_write_32_lr10
(
nvswitch_device *device,
NvU32 offset,
NvU32 data
)
{
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
return;
}
// Write the register
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
}
//
// This function auto creates the lr10 HAL connectivity from the NVSWITCH_INIT_HAL
// macro in haldef_nvswitch.h

52
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -160,6 +160,13 @@ nvswitch_corelib_training_complete_ls10
{
nvswitch_device *device = link->dev->pDevInfo;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return; // NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
nvswitch_init_dlpl_interrupts(link);
_nvswitch_configure_reserved_throughput_counters(link);
@@ -265,6 +272,13 @@ nvswitch_corelib_set_tx_mode_ls10
NvU32 val;
NvlStatus status = NVL_SUCCESS;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,
@@ -352,6 +366,13 @@ nvswitch_corelib_set_dl_link_mode_ls10
NvBool keepPolling;
NVSWITCH_TIMEOUT timeout;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if (!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLDL, link->linkNumber))
{
NVSWITCH_PRINT(device, ERROR,
@@ -494,6 +515,13 @@ nvswitch_corelib_get_rx_detect_ls10
NvlStatus status;
nvswitch_device *device = link->dev->pDevInfo;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
status = nvswitch_minion_get_rxdet_status_ls10(device, link->linkNumber);
if (status != NVL_SUCCESS)
@@ -590,13 +618,22 @@ nvswitch_corelib_get_tl_link_mode_ls10
{
case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_ACTIVE:
// If using ALI, ensure that the request to active completed
if (link->dev->enableALI)
if (nvswitch_is_tnvl_mode_locked(device))
{
status = nvswitch_wait_for_tl_request_ready_ls10(link);
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
*mode = NVLINK_LINKSTATE_HS;
}
else
{
// If using ALI, ensure that the request to active completed
if (link->dev->enableALI)
{
status = nvswitch_wait_for_tl_request_ready_ls10(link);
}
*mode = (status == NVL_SUCCESS) ? NVLINK_LINKSTATE_HS:NVLINK_LINKSTATE_OFF;
*mode = (status == NVL_SUCCESS) ? NVLINK_LINKSTATE_HS:NVLINK_LINKSTATE_OFF;
}
break;
case NV_NVLIPT_LNK_CTRL_LINK_STATE_STATUS_CURRENTLINKSTATE_L2:
@@ -995,6 +1032,13 @@ nvswitch_launch_ALI_link_training_ls10
{
NvlStatus status = NVL_SUCCESS;
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT(device, ERROR,
"%s(%d): Security locked\n", __FUNCTION__, __LINE__);
return NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
if ((link == NULL) ||
!NVSWITCH_IS_LINK_ENG_VALID_LS10(device, NVLIPT_LNK, link->linkNumber) ||
(link->linkNumber >= NVSWITCH_NVLINK_MAX_LINKS))

31
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -4409,11 +4409,11 @@ nvswitch_eng_wr_ls10
if (nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_tnvl_reg_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
nvswitch_tnvl_eng_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data);
}
else
{
nvswitch_reg_write_32(device, base_addr + offset, data);
nvswitch_reg_write_32(device, base_addr + offset, data);
}
#if defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
@@ -4431,6 +4431,33 @@ nvswitch_eng_wr_ls10
#endif //defined(DEVELOP) || defined(DEBUG) || defined(NV_MODS)
}
void
nvswitch_reg_write_32_ls10
(
nvswitch_device *device,
NvU32 offset,
NvU32 data
)
{
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
return;
}
if (nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_tnvl_reg_wr_32_ls10(device, offset, data);
}
else
{
// Write the register
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
}
}
NvU32
nvswitch_get_link_eng_inst_ls10
(

121
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -590,11 +590,19 @@ nvswitch_soe_reg_wr_32_ls10
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
return -NVL_IO_ERROR;
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_ISSUE_REGISTER_WRITE))
SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS))
{
nvswitch_reg_write_32(device, offset, data);
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
return NVL_SUCCESS;
}
@@ -629,6 +637,96 @@ nvswitch_soe_reg_wr_32_ls10
return NVL_SUCCESS;
}
/*
* @Brief : Perform engine writes in SOE during TNVL
*
* @param[in] device
* @param[in] eng_id NVSWITCH_ENGINE_ID*
* @param[in] eng_bcast NVSWITCH_GET_ENG_DESC_TYPE*
* @param[in] eng_instance
* @param[in] base_addr
* @param[in] offset
* @param[in] data
*/
NvlStatus
nvswitch_soe_eng_wr_32_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
NvU32 eng_bcast,
NvU32 eng_instance,
NvU32 base_addr,
NvU32 offset,
NvU32 data
)
{
FLCN *pFlcn;
NvU32 cmdSeqDesc = 0;
NV_STATUS status;
RM_FLCN_CMD_SOE cmd;
NVSWITCH_TIMEOUT timeout;
RM_SOE_TNVL_CMD_ENGINE_WRITE *pEngineWrite;
NVSWITCH_GET_BIOS_INFO_PARAMS params = { 0 };
if (!nvswitch_is_soe_supported(device))
{
NVSWITCH_PRINT(device, INFO,
"%s: SOE is not supported\n",
__FUNCTION__);
return NVL_SUCCESS; // -NVL_ERR_NOT_SUPPORTED
}
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
return -NVL_IO_ERROR;
}
status = device->hal.nvswitch_ctrl_get_bios_info(device, &params);
if ((status != NVL_SUCCESS) || ((params.version & SOE_VBIOS_VERSION_MASK) <
SOE_VBIOS_REVLOCK_SOE_PRI_CHECKS))
{
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + base_addr + offset, data);
return NVL_SUCCESS;
}
pFlcn = device->pSoe->pFlcn;
nvswitch_os_memset(&cmd, 0, sizeof(cmd));
cmd.hdr.unitId = RM_SOE_UNIT_TNVL;
cmd.hdr.size = RM_SOE_CMD_SIZE(TNVL, ENGINE_WRITE);
pEngineWrite = &cmd.cmd.tnvl.engineWrite;
pEngineWrite->cmdType = RM_SOE_TNVL_CMD_ISSUE_ENGINE_WRITE;
pEngineWrite->eng_id = eng_id;
pEngineWrite->eng_bcast = eng_bcast;
pEngineWrite->eng_instance = eng_instance;
pEngineWrite->base = base_addr;
pEngineWrite->offset = offset;
pEngineWrite->data = data;
nvswitch_timeout_create(NVSWITCH_INTERVAL_5MSEC_IN_NS, &timeout);
status = flcnQueueCmdPostBlocking(device, pFlcn,
(PRM_FLCN_CMD)&cmd,
NULL, // pMsg
NULL, // pPayload
SOE_RM_CMDQ_LOG_ID,
&cmdSeqDesc,
&timeout);
if (status != NV_OK)
{
NVSWITCH_PRINT(device, ERROR,
"%s: Failed to send ENGINE_WRITE command to SOE, offset = 0x%x, data = 0x%x\n",
__FUNCTION__, offset, data);
return -NVL_ERR_GENERIC;
}
return NVL_SUCCESS;
}
/*
* @Brief : Init sequence for SOE FSP RISCV image
*
@@ -902,7 +1000,6 @@ _soeService_LS10
)
{
NvBool bRecheckMsgQ = NV_FALSE;
NvBool bRecheckPrintQ = NV_FALSE;
NvU32 clearBits = 0;
NvU32 intrStatus;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
@@ -968,8 +1065,6 @@ _soeService_LS10
NVSWITCH_PRINT(device, INFO,
"%s: Received a SWGEN1 interrupt\n",
__FUNCTION__);
flcnDebugBufferDisplay_HAL(device, pFlcn);
bRecheckPrintQ = NV_TRUE;
}
// Clear any sources that were serviced and get the new status.
@@ -1005,22 +1100,6 @@ _soeService_LS10
}
}
//
// If we just processed a SWGEN1 interrupt (Debug Buffer interrupt), peek
// into the Debug Buffer and see if any text was missed the last time
// the buffer was displayed (above). If it is not empty, re-generate SWGEN1
// (since it is now cleared) and exit. As long as an interrupt is pending,
// this function will be re-entered and the message(s) will be processed.
//
if (bRecheckPrintQ)
{
if (!flcnDebugBufferIsEmpty_HAL(device, pFlcn))
{
flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET,
DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN1, _SET));
}
}
flcnIntrRetrigger_HAL(device, pFlcn);
return intrStatus;

4
src/common/nvswitch/kernel/ls10/sugen_ls10.c
View File

@@ -936,6 +936,7 @@ nvswitch_nvs_top_prod_ls10
NVSWITCH_ENG_WR32(device, SYS_PRI_RS_CTRL, , 0, _PPRIV_RS_CTRL_SYS, _CG1,
DRF_DEF(_PPRIV_RS_CTRL_SYS, _CG1, _SLCG, __PROD));
#if 0
NVSWITCH_ENG_WR32(device, XAL, , 0, _XAL_EP, _CG,
DRF_DEF(_XAL_EP, _CG, _IDLE_CG_DLY_CNT, __PROD) |
DRF_DEF(_XAL_EP, _CG, _IDLE_CG_EN, __PROD) |
@@ -961,7 +962,8 @@ nvswitch_nvs_top_prod_ls10
DRF_DEF(_XAL_EP, _CG1, _SLCG_TXMAP, __PROD) |
DRF_DEF(_XAL_EP, _CG1, _SLCG_UNROLL_MEM, __PROD) |
DRF_DEF(_XAL_EP, _CG1, _SLCG_UPARB, __PROD));
#endif //0
NVSWITCH_ENG_WR32(device, XPL, , 0, _XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG,
DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _IDLE_CG_DLY_CNT, __PROD) |
DRF_DEF(_XPL, _PL_PAD_CTL_PRI_XPL_RXCLK_CG, _IDLE_CG_EN, __PROD) |

144
src/common/nvswitch/kernel/ls10/tnvl_ls10.c
View File

@@ -34,6 +34,10 @@
#include "nvswitch/ls10/dev_ctrl_ip_addendum.h"
#include "nvswitch/ls10/dev_cpr_ip.h"
#include "nvswitch/ls10/dev_npg_ip.h"
#include "nvswitch/ls10/dev_fsp_pri.h"
#include "nvswitch/ls10/dev_soe_ip.h"
#include "nvswitch/ls10/ptop_discovery_ip.h"
#include "nvswitch/ls10/dev_minion_ip.h"
#include <stddef.h>
@@ -1058,7 +1062,7 @@ nvswitch_tnvl_get_status_ls10
}
static NvBool
_nvswitch_reg_cpu_write_allow_list_ls10
_nvswitch_tnvl_eng_wr_cpu_allow_list_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
@@ -1091,6 +1095,15 @@ _nvswitch_reg_cpu_write_allow_list_ls10
return NV_TRUE;
break;
}
case NVSWITCH_ENGINE_ID_MINION:
{
if ((offset == NV_MINION_NVLINK_DL_STAT(0)) ||
(offset == NV_MINION_NVLINK_DL_STAT(1)) ||
(offset == NV_MINION_NVLINK_DL_STAT(2)) ||
(offset == NV_MINION_NVLINK_DL_STAT(3)))
return NV_TRUE;
break;
}
default :
return NV_FALSE;
}
@@ -1099,7 +1112,7 @@ _nvswitch_reg_cpu_write_allow_list_ls10
}
void
nvswitch_tnvl_reg_wr_32_ls10
nvswitch_tnvl_eng_wr_32_ls10
(
nvswitch_device *device,
NVSWITCH_ENGINE_ID eng_id,
@@ -1110,45 +1123,124 @@ nvswitch_tnvl_reg_wr_32_ls10
NvU32 data
)
{
if (!nvswitch_is_tnvl_mode_enabled(device))
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is not enabled\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
return;
}
if (!nvswitch_is_tnvl_mode_enabled(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"ENG reg-write failed. TNVL mode is not enabled\n");
return;
}
if (_nvswitch_tnvl_eng_wr_cpu_allow_list_ls10(device, eng_id, offset))
{
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + base_addr + offset, data);
return;
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL ENG_WR failure - 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
eng_id, eng_instance, eng_bcast, base_addr, offset, data);
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL mode is locked\n");
return;
}
if (nvswitch_soe_eng_wr_32_ls10(device, eng_id, eng_bcast, eng_instance, base_addr, offset, data) != NVL_SUCCESS)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL ENG_WR failure - 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
eng_id, eng_instance, eng_bcast, base_addr, offset, data);
NVSWITCH_PRINT(device, ERROR,
"%s: TNVL mode is locked\n",
__FUNCTION__);
"%s: SOE ENG_WR failed for 0x%x[%d] %s @0x%08x+0x%06x = 0x%08x\n",
__FUNCTION__,
eng_id, eng_instance,
(
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" :
"??"
),
base_addr, offset, data);
}
}
static NvBool
_nvswitch_tnvl_reg_wr_cpu_allow_list_ls10
(
nvswitch_device *device,
NvU32 offset
)
{
if ((offset >= DRF_BASE(NV_PFSP)) &&
(offset <= DRF_EXTENT(NV_PFSP)))
{
return NV_TRUE;
}
if ((offset >= NV_PTOP_UNICAST_SW_DEVICE_BASE_SOE_0 + DRF_BASE(NV_SOE)) &&
(offset <= NV_PTOP_UNICAST_SW_DEVICE_BASE_SOE_0 + DRF_EXTENT(NV_SOE)))
{
return NV_TRUE;
}
return NV_FALSE;
}
void
nvswitch_tnvl_reg_wr_32_ls10
(
nvswitch_device *device,
NvU32 offset,
NvU32 data
)
{
if (device->nvlink_device->pciInfo.bars[0].pBar == NULL)
{
NVSWITCH_PRINT(device, ERROR,
"%s: register write failed at offset 0x%x\n",
__FUNCTION__, offset);
NVSWITCH_ASSERT(0);
return;
}
if (_nvswitch_reg_cpu_write_allow_list_ls10(device, eng_id, offset))
if (!nvswitch_is_tnvl_mode_enabled(device))
{
nvswitch_reg_write_32(device, base_addr + offset, data);
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"Reg-write failed. TNVL mode is not enabled\n");
return;
}
else
if (_nvswitch_tnvl_reg_wr_cpu_allow_list_ls10(device, offset))
{
if (nvswitch_soe_reg_wr_32_ls10(device, base_addr + offset, data) != NVL_SUCCESS)
{
NVSWITCH_PRINT(device, ERROR,
"%s: SOE ENG_WR failed for 0x%x[%d] %s @0x%08x+0x%06x = 0x%08x\n",
__FUNCTION__,
eng_id, eng_instance,
(
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_UNICAST) ? "UC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_BCAST) ? "BC" :
(eng_bcast == NVSWITCH_GET_ENG_DESC_TYPE_MULTICAST) ? "MC" :
"??"
),
base_addr, offset, data);
NVSWITCH_ASSERT(0);
}
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
return;
}
if (nvswitch_is_tnvl_mode_locked(device))
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL REG_WR failure - 0x%08x, 0x%08x\n", offset, data);
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL mode is locked\n");
return;
}
if (nvswitch_soe_reg_wr_32_ls10(device, offset, data) != NVL_SUCCESS)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_TNVL_ERROR,
"TNVL REG_WR failure - 0x%08x, 0x%08x\n", offset, data);
}
}

105
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -4964,10 +4964,7 @@ nvswitch_reg_write_32
device->nvlink_device->pciInfo.bars[0].baseAddr, offset, data);
#endif
// Write the register
nvswitch_os_mem_write32((NvU8 *)device->nvlink_device->pciInfo.bars[0].pBar + offset, data);
return;
device->hal.nvswitch_reg_write_32(device, offset, data);
}
NvU64
@@ -6074,6 +6071,101 @@ _nvswitch_ctrl_set_device_tnvl_lock
return status;
}
/*
* Service ioctls supported when TNVL mode is locked
*/
NvlStatus
nvswitch_lib_ctrl_tnvl_lock_only
(
nvswitch_device *device,
NvU32 cmd,
void *params,
NvU64 size,
void *osPrivate
)
{
NvlStatus retval;
NvU64 flags = 0;
if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device) || params == NULL)
{
return -NVL_BAD_ARGS;
}
flags = NVSWITCH_DEV_CMD_CHECK_ADMIN | NVSWITCH_DEV_CMD_CHECK_FM;
switch (cmd)
{
NVSWITCH_DEV_CMD_DISPATCH(CTRL_NVSWITCH_GET_INFOROM_VERSION,
_nvswitch_ctrl_get_inforom_version,
NVSWITCH_GET_INFOROM_VERSION_PARAMS);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_NVLINK_MAX_ERROR_RATES,
_nvswitch_ctrl_get_inforom_nvlink_max_correctable_error_rate,
NVSWITCH_GET_NVLINK_MAX_CORRECTABLE_ERROR_RATES_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_NVLINK_ERROR_COUNTS,
_nvswitch_ctrl_get_inforom_nvlink_errors,
NVSWITCH_GET_NVLINK_ERROR_COUNTS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_ECC_ERROR_COUNTS,
_nvswitch_ctrl_get_inforom_ecc_errors,
NVSWITCH_GET_ECC_ERROR_COUNTS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SXIDS,
_nvswitch_ctrl_get_inforom_bbx_sxid,
NVSWITCH_GET_SXIDS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_SYS_INFO,
_nvswitch_ctrl_get_inforom_bbx_sys_info,
NVSWITCH_GET_SYS_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TIME_INFO,
_nvswitch_ctrl_get_inforom_bbx_time_info,
NVSWITCH_GET_TIME_INFO_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_DATA,
_nvswitch_ctrl_get_inforom_bbx_temp_data,
NVSWITCH_GET_TEMP_DATA_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TEMP_SAMPLES,
_nvswitch_ctrl_get_inforom_bbx_temp_samples,
NVSWITCH_GET_TEMP_SAMPLES_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN,
_nvswitch_ctrl_get_attestation_certificate_chain,
NVSWITCH_GET_ATTESTATION_CERTIFICATE_CHAIN_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_ATTESTATION_REPORT,
_nvswitch_ctrl_get_attestation_report,
NVSWITCH_GET_ATTESTATION_REPORT_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_GET_TNVL_STATUS,
_nvswitch_ctrl_get_tnvl_status,
NVSWITCH_GET_TNVL_STATUS_PARAMS,
osPrivate, flags);
NVSWITCH_DEV_CMD_DISPATCH_PRIVILEGED(
CTRL_NVSWITCH_SET_FM_DRIVER_STATE,
nvswitch_ctrl_set_fm_driver_state,
NVSWITCH_SET_FM_DRIVER_STATE_PARAMS,
osPrivate, flags);
default:
nvswitch_os_print(NVSWITCH_DBG_LEVEL_INFO, "ioctl %x is not permitted when TNVL is locked\n", cmd);
return -NVL_ERR_INSUFFICIENT_PERMISSIONS;
}
return retval;
}
NvlStatus
nvswitch_lib_ctrl
(
@@ -6087,6 +6179,11 @@ nvswitch_lib_ctrl
NvlStatus retval;
NvU64 flags = 0;
if (nvswitch_is_tnvl_mode_locked(device))
{
return nvswitch_lib_ctrl_tnvl_lock_only(device, cmd, params, size, osPrivate);
}
if (!NVSWITCH_IS_DEVICE_ACCESSIBLE(device) || params == NULL)
{
return -NVL_BAD_ARGS;

9
src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000vgpu.h
View File

@@ -37,6 +37,15 @@
#include "class/cl0000.h"
#include "nv_vgpu_types.h"
/* DRF macros for OBJGPU::gpuId */
#define NV0000_BUSDEVICE_DOMAIN 31:16
#define NV0000_BUSDEVICE_BUS 15:8
#define NV0000_BUSDEVICE_DEVICE 7:0
#define GPU_32_BIT_ID_DECODE_DOMAIN(gpuId) (NvU16)DRF_VAL(0000, _BUSDEVICE, _DOMAIN, gpuId);
#define GPU_32_BIT_ID_DECODE_BUS(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _BUS, gpuId);
#define GPU_32_BIT_ID_DECODE_DEVICE(gpuId) (NvU8) DRF_VAL(0000, _BUSDEVICE, _DEVICE, gpuId);
/*
* NV0000_CTRL_CMD_VGPU_CREATE_DEVICE
*

2
src/common/sdk/nvidia/inc/nvstatuscodes.h
View File

@@ -152,6 +152,8 @@ NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manag
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
NV_STATUS_CODE(NV_ERR_NVSWITCH_FABRIC_NOT_READY, 0x00000081, "Nvswitch Fabric Status or Fabric Probe is not yet complete, caller needs to retry")
NV_STATUS_CODE(NV_ERR_NVSWITCH_FABRIC_FAILURE, 0x00000082, "Nvswitch Fabric Probe failed")
// Warnings:
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")

3
src/common/uproc/os/common/include/liblogdecode.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
* SPDX-License-Identifier: MIT
*
* Permission is hereby granted, free of charge, to any person obtaining a
@@ -187,6 +187,7 @@ void libosLogDestroy(LIBOS_LOG_DECODE *logDecode);
void libosExtractLogs(LIBOS_LOG_DECODE *logDecode, NvBool bSyncNvLog);
void libosPreserveLogs(LIBOS_LOG_DECODE *pLogDecode);
NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInstance);
#ifdef __cplusplus
}

28
src/common/uproc/os/libos-v3.1.0/lib/liblogdecode.c
View File

@@ -1438,6 +1438,34 @@ void libosPreserveLogs(LIBOS_LOG_DECODE *pLogDecode)
}
}
NvBool isLibosPreserveLogBufferFull(LIBOS_LOG_DECODE *pLogDecode, NvU32 gpuInstance)
{
NvU64 i = (NvU32)(pLogDecode->numLogBuffers);
NvU32 tag = LIBOS_LOG_NVLOG_BUFFER_TAG(pLogDecode->sourceName, i * 2);
NVLOG_BUFFER_HANDLE handle = 0;
NV_STATUS status = nvlogGetBufferHandleFromTag(tag, &handle);
if (status != NV_OK)
{
return NV_FALSE;
}
NVLOG_BUFFER *pNvLogBuffer = NvLogLogger.pBuffers[handle];
if (pNvLogBuffer == NULL)
{
return NV_FALSE;
}
if (FLD_TEST_DRF(LOG_BUFFER, _FLAGS, _PRESERVE, _YES, pNvLogBuffer->flags) &&
DRF_VAL(LOG, _BUFFER_FLAGS, _GPU_INSTANCE, pNvLogBuffer->flags) == gpuInstance &&
(pNvLogBuffer->pos >= pNvLogBuffer->size - NV_OFFSETOF(LIBOS_LOG_NVLOG_BUFFER, data) - sizeof(NvU64)))
{
return NV_TRUE;
}
return NV_FALSE;
}
static NvBool findPreservedNvlogBuffer(NvU32 tag, NvU32 gpuInstance, NVLOG_BUFFER_HANDLE *pHandle)
{
NVLOG_BUFFER_HANDLE handle = 0;