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525.60.11

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This commit is contained in:
Andy Ritger
2022-11-28 13:39:27 -08:00
parent 758b4ee818
commit 5f40a5aee5
113 changed files with 1408 additions and 723 deletions
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2
src/common/displayport/inc/dp_connector.h
View File

@@ -203,6 +203,8 @@ namespace DisplayPort
virtual bool getSDPExtnForColorimetrySupported() = 0;
virtual bool getPanelFwRevision(NvU16 *revision) = 0;
virtual bool getIgnoreMSACap() = 0;
virtual AuxRetry::status setIgnoreMSAEnable(bool msaTimingParamIgnoreEn) = 0;

2
src/common/displayport/inc/dp_deviceimpl.h
View File

@@ -381,6 +381,8 @@ namespace DisplayPort
virtual bool getSDPExtnForColorimetrySupported();
virtual bool getPanelFwRevision(NvU16 *revision);
virtual bool isPowerSuspended();
virtual void setPanelPowerParams(bool bSinkPowerStateD0, bool bPanelPowerStateOn);

40
src/common/displayport/src/dp_deviceimpl.cpp
View File

@@ -1043,6 +1043,46 @@ bool DeviceImpl::getSDPExtnForColorimetrySupported()
return (this->bSdpExtCapable == True);
}
bool DeviceImpl::getPanelFwRevision(NvU16 *revision)
{
NvU8 fwRevisionMajor = 0;
NvU8 fwRevisionMinor = 0;
unsigned size = 0;
unsigned nakReason = NakUndefined;
if (!revision)
{
return false;
}
*revision = 0;
//
// On faked mux devices, we cannot check if the device has
// the capability as we don't have access to aux.
//
if (this->isFakedMuxDevice())
{
return false;
}
if (AuxBus::success != this->getDpcdData(NV_DPCD14_FW_SW_REVISION_MAJOR,
&fwRevisionMajor, sizeof(fwRevisionMajor), &size, &nakReason))
{
return false;
}
if (AuxBus::success != this->getDpcdData(NV_DPCD14_FW_SW_REVISION_MINOR,
&fwRevisionMinor, sizeof(fwRevisionMinor), &size, &nakReason))
{
return false;
}
*revision = (fwRevisionMajor << 8) | fwRevisionMinor;
return true;
}
bool DeviceImpl::isPowerSuspended()
{
bool bPanelPowerOn, bDPCDPowerStateD0;

4
src/common/inc/displayport/dpcd14.h
View File

@@ -330,6 +330,10 @@
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_VALID_NO (0x00000000) /* R-XUV */
#define NV_DPCD14_FEC_ERROR_COUNT_FEC_ERROR_COUNT_VALID_YES (0x00000001) /* R-XUV */
// Field definitions for FW/SW Revision
#define NV_DPCD14_FW_SW_REVISION_MAJOR (0x0000040A) /* R-XUR */
#define NV_DPCD14_FW_SW_REVISION_MINOR (0x0000040B) /* R-XUR */
// Field definition for 0x0200E (LANE_ALIGN_STATUS_UPDATED_ESI), used only when DP2.0+ 128b/132b is enabled.
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI (0x0000200E) /* R-XUR */
#define NV_DPCD20_LANE_ALIGN_STATUS_UPDATED_ESI_128B_132B_DPRX_EQ_INTERLANE_ALIGN_DONE 2:2 /* R-XUF */

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r525_00
#define NV_BUILD_BRANCH r526_91
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r525_00
#define NV_PUBLIC_BRANCH r526_91
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r525_00-154"
#define NV_BUILD_CHANGELIST_NUM (31993960)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r525/r526_91-181"
#define NV_BUILD_CHANGELIST_NUM (32108895)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r525/r525_00-154"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31993960)
#define NV_BUILD_NAME "rel/gpu_drv/r525/r526_91-181"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32108895)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r525_00-178"
#define NV_BUILD_CHANGELIST_NUM (31990457)
#define NV_BUILD_BRANCH_VERSION "r526_91-9"
#define NV_BUILD_CHANGELIST_NUM (32103636)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "526.52"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (31990457)
#define NV_BUILD_NAME "527.27"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (32103636)
#define NV_BUILD_BRANCH_BASE_VERSION R525
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "525.53"
#define NV_VERSION_STRING "525.60.11"
#else

3
src/common/inc/swref/published/nvswitch/ls10/dev_minion_ip_addendum.h
View File

@@ -28,6 +28,9 @@
#define NV_MINION_DL_CMD_DATA_RXCAL_EN_ALARM 0x50
#define NV_MINION_DL_CMD_DATA_INIT_CAL_DONE 0x26
#define NV_MINION_NVLINK_DL_CMD_COMMAND_SETUPTC 0x00000094
#define NV_MINION_NVLINK_DL_CMD_COMMAND_CLR_TLC_MISC_REGS 0x00000026
// filtering dev_minion_dlstat.ref for pattern (CMINION|MINION|NVLSTAT|PMINION|SWMINION)
#define NV_NVLSTAT 0x00000103:0x00000000 /* RW--D */
#define NV_NVLSTAT_UC01 0x00000001 /* R--4R */

3
src/common/nvlink/kernel/nvlink/core/nvlink_shutdown.c
View File

@@ -1,5 +1,5 @@
/*******************************************************************************
Copyright (c) 2019-2020 NVidia Corporation
Copyright (c) 2019-2022 NVidia Corporation
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to
@@ -1047,6 +1047,7 @@ nvlink_core_powerdown_floorswept_conns_to_off
if (numConnsToShutdown != 0)
{
nvlink_core_powerdown_intranode_conns_from_active_to_off(connsToShutdown, numConnsToShutdown, 0);
nvlink_core_reset_intranode_conns(connsToShutdown, numConnsToShutdown, NVLINK_STATE_CHANGE_ASYNC);
for (j = 0; j < numConnsToShutdown; ++j)
{

7
src/common/nvswitch/common/inc/soe/soeifcmn.h
View File

@@ -175,4 +175,11 @@ enum
RM_SOE_DMAIDX_GUEST_PHYS_SYS_NCOH_BOUND = 7
};
/*!
* SOE Debug buffer size
* Creating a copy of SOE_DMESG_BUFFER_SIZE in memmap.h
* soe/memmap.h is conflicting with sec2/memmap.h and cannot be used in the driver
*/
#define SOE_DEBUG_BUFFER_SIZE 0x1000
#endif // _GSOEIFCMN_H_

1
src/common/nvswitch/interface/ctrl_dev_nvswitch.h
View File

@@ -802,6 +802,7 @@ typedef enum nvswitch_err_type
NVSWITCH_ERR_HW_HOST_THERMAL_EVENT_END = 10005,
NVSWITCH_ERR_HW_HOST_THERMAL_SHUTDOWN = 10006,
NVSWITCH_ERR_HW_HOST_IO_FAILURE = 10007,
NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE = 10008,
NVSWITCH_ERR_HW_HOST_LAST,

8
src/common/nvswitch/interface/export_nvswitch.h
View File

@@ -804,6 +804,14 @@ nvswitch_os_strncmp
NvLength length
);
char*
nvswitch_os_strncat
(
char *s1,
const char *s2,
NvLength length
);
void *
nvswitch_os_memset
(

66
src/common/nvswitch/kernel/flcn/flcn_call_hal_nvswitch.c
View File

@@ -109,7 +109,7 @@ flcnQueueCmdPostBlocking
if (status != NV_OK)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_COMMAND_QUEUE,
"Failed to post command to SOE\n");
"Fatal, Failed to post command to SOE\n");
return status;
}
@@ -117,7 +117,7 @@ flcnQueueCmdPostBlocking
if (status == NV_ERR_TIMEOUT)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_TIMEOUT,
"Timed out while waiting for SOE command completion\n");
"Fatal, Timed out while waiting for SOE command completion\n");
flcnQueueCmdCancel(device, pFlcn, *pSeqDesc);
}
@@ -691,9 +691,9 @@ flcnSetDmemAddr_HAL
NvU32
flcnRiscvRegRead_HAL
(
struct nvswitch_device *device,
PFLCN pFlcn,
NvU32 offset
nvswitch_device *device,
PFLCN pFlcn,
NvU32 offset
)
{
NVSWITCH_ASSERT(pFlcn->pHal->riscvRegRead != (void *)0);
@@ -703,12 +703,60 @@ flcnRiscvRegRead_HAL
void
flcnRiscvRegWrite_HAL
(
struct nvswitch_device *device,
PFLCN pFlcn,
NvU32 offset,
NvU32 data
nvswitch_device *device,
PFLCN pFlcn,
NvU32 offset,
NvU32 data
)
{
NVSWITCH_ASSERT(pFlcn->pHal->riscvRegWrite != (void *)0);
pFlcn->pHal->riscvRegWrite(device, pFlcn, offset, data);
}
NV_STATUS
flcnDebugBufferInit_HAL
(
nvswitch_device *device,
PFLCN pFlcn,
NvU32 debugBufferMaxSize,
NvU32 writeRegAddr,
NvU32 readRegAddr
)
{
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferInit != (void *)0);
return pFlcn->pHal->debugBufferInit(device, pFlcn, debugBufferMaxSize, writeRegAddr, readRegAddr);
}
NV_STATUS
flcnDebugBufferDestroy_HAL
(
nvswitch_device *device,
FLCN *pFlcn
)
{
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferDestroy != (void *)0);
return pFlcn->pHal->debugBufferDestroy(device, pFlcn);
}
NV_STATUS
flcnDebugBufferDisplay_HAL
(
nvswitch_device *device,
FLCN *pFlcn
)
{
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferDisplay != (void *)0);
return pFlcn->pHal->debugBufferDisplay(device, pFlcn);
}
NvBool
flcnDebugBufferIsEmpty_HAL
(
nvswitch_device *device,
FLCN *pFlcn
)
{
NVSWITCH_ASSERT(pFlcn->pHal->debugBufferIsEmpty != (void *)0);
return pFlcn->pHal->debugBufferIsEmpty(device, pFlcn);
}

2
src/common/nvswitch/kernel/inc/common_nvswitch.h
View File

@@ -260,6 +260,8 @@ typedef struct
NvU32 lp_threshold;
NvU32 minion_intr;
NvU32 surpress_link_errors_for_gpu_reset;
NvU32 block_code_mode;
NvU32 reference_clock_mode;
} NVSWITCH_REGKEY_TYPE;
//

7
src/common/nvswitch/kernel/inc/flcn/flcn_nvswitch.h
View File

@@ -282,6 +282,9 @@ typedef struct FLCN
/*! HW arch that is enabled and running on corresponding uproc engine. */
NvU32 engArch;
/*! Flcn debug buffer object */
} FLCN, *PFLCN;
// hal functions
@@ -339,6 +342,10 @@ void flcnImemCopyTo_HAL (struct nvswitch_device
NvU32 flcnSetDmemAddr_HAL (struct nvswitch_device *, struct FLCN *, NvU32 dst);
NvU32 flcnRiscvRegRead_HAL (struct nvswitch_device *, PFLCN, NvU32 offset);
void flcnRiscvRegWrite_HAL (struct nvswitch_device *, PFLCN, NvU32 offset, NvU32 data);
NV_STATUS flcnDebugBufferInit_HAL (struct nvswitch_device *, struct FLCN *, NvU32 debugBufferMaxSize, NvU32 writeRegAddr, NvU32 readRegAddr);
NV_STATUS flcnDebugBufferDestroy_HAL (struct nvswitch_device *, struct FLCN *);
NV_STATUS flcnDebugBufferDisplay_HAL (struct nvswitch_device *, struct FLCN *);
NvBool flcnDebugBufferIsEmpty_HAL (struct nvswitch_device *, struct FLCN *);
// Falcon core revision / subversion definitions.
#define NV_FLCN_CORE_REV_3_0 0x30 // 3.0 - Core revision 3 subversion 0.

4
src/common/nvswitch/kernel/inc/flcn/haldefs_flcn_nvswitch.h
View File

@@ -91,6 +91,10 @@ typedef struct {
NvU32 (*setDmemAddr) (struct nvswitch_device *, struct FLCN *, NvU32 dst);
NvU32 (*riscvRegRead) (struct nvswitch_device *, struct FLCN *, NvU32 offset);
void (*riscvRegWrite) (struct nvswitch_device *, struct FLCN *, NvU32 offset, NvU32 data);
NV_STATUS (*debugBufferInit) (struct nvswitch_device *, struct FLCN *, NvU32 debugBufferMaxSize, NvU32 writeRegAddr, NvU32 readRegAddr);
NV_STATUS (*debugBufferDestroy) (struct nvswitch_device *, struct FLCN *);
NV_STATUS (*debugBufferDisplay) (struct nvswitch_device *, struct FLCN *);
NvBool (*debugBufferIsEmpty) (struct nvswitch_device *, struct FLCN *);
} flcn_hal;
void flcnQueueSetupHal(struct FLCN *pFlcn);

31
src/common/nvswitch/kernel/inc/regkey_nvswitch.h
View File

@@ -589,4 +589,35 @@
#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_DISABLE 0x0
#define NV_SWITCH_REGKEY_SURPRESS_LINK_ERRORS_FOR_GPU_RESET_ENABLE 0x1
/*
* NV_SWITCH_REGKEY_BLOCK_CODE_MODE - Indicates the Forward Error Correction Mode
*
* Forward Error Correction Mode (Pre-HS).
* DEFAULT = System Default
* OFF = 0x0
* ECC96_ENABLED = 0x1
* ECC88_ENABLED = 0x2
*/
#define NV_SWITCH_REGKEY_BLOCK_CODE_MODE "BlockCodeMode"
#define NV_SWITCH_REGKEY_BLOCK_CODE_MODE_DEFAULT 0x0
#define NV_SWITCH_REGKEY_BLOCK_CODE_MODE_OFF 0x0
#define NV_SWITCH_REGKEY_BLOCK_CODE_MODE_ECC96_ENABLED 0x1
#define NV_SWITCH_REGKEY_BLOCK_CODE_MODE_ECC88_ENABLED 0x2
/*
* NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE - Indicates the reference clock mode for
* the system w.r.t. this link.
*
* DEFAULT = System Default
* COMMON = Common reference clock. Spread Spectrum (SS) may or may not be enabled.
* NON_COMMON_NO_SS = Non-common reference clock without SS enabled.
* NON_COMMON_SS = Non-common reference clock with SS enabled.
*/
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE "ReferenceClockMode"
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_DEFAULT 0x0
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_COMMON 0x0
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_RESERVED 0x1
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_NON_COMMON_NO_SS 0x2
#define NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_NON_COMMON_SS 0x3
#endif //_REGKEY_NVSWITCH_H_

9
src/common/nvswitch/kernel/lr10/flcn_lr10.c
View File

@@ -211,11 +211,10 @@ _flcnConstruct_LR10
PFLCNABLE pFlcnable = pFlcn->pFlcnable;
PFALCON_QUEUE_INFO pQueueInfo;
pFlcn->bConstructed = NV_TRUE;
if (pFlcn->engArch == NV_UPROC_ENGINE_ARCH_DEFAULT)
{
// Default the arch to Falcon if it's not set
pFlcn->engArch = NV_UPROC_ENGINE_ARCH_FALCON;
}
// Set the arch to Falcon
pFlcn->engArch = NV_UPROC_ENGINE_ARCH_FALCON;
// Allocate the memory for Queue Data Structure if needed.
if (pFlcn->bQueuesEnabled)
{

57
src/common/nvswitch/kernel/lr10/link_lr10.c
View File

@@ -2076,7 +2076,8 @@ nvswitch_setup_link_system_registers_lr10
nvlink_link *link
)
{
NvU32 regval, fldval;
NvU32 regval = 0;
NvU32 fldval = 0;
NvU32 lineRate = 0;
NVLINK_CONFIG_DATA_LINKENTRY *vbios_link_entry = NULL;
NVSWITCH_BIOS_NVLINK_CONFIG *bios_config;
@@ -2113,10 +2114,26 @@ nvswitch_setup_link_system_registers_lr10
_LINE_RATE, lineRate, regval);
NVSWITCH_PRINT(device, SETUP, "%s: LINE_RATE = 0x%x requested by regkey\n",
__FUNCTION__, lineRate);
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, regval);
}
// REFERENCE_CLOCK_MODE SYSTEM register
if (device->regkeys.reference_clock_mode != NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_DEFAULT)
{
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL,
_REFERENCE_CLOCK_MODE, device->regkeys.reference_clock_mode, regval);
NVSWITCH_PRINT(device, SETUP, "%s: REFERENCE_CLOCK_MODE = 0x%x requested by regkey\n",
__FUNCTION__, device->regkeys.reference_clock_mode);
}
else if (vbios_link_entry != NULL)
{
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CLK_CTRL, _REFERENCE_CLOCK_MODE,
DRF_VAL(_NVLINK_VBIOS,_PARAM3,_REFERENCE_CLOCK_MODE, vbios_link_entry->nvLinkparam3),
regval);
}
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CLK_CTRL, regval);
// TXTRAIN SYSTEM register
regval = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL);
@@ -2200,6 +2217,40 @@ nvswitch_setup_link_system_registers_lr10
regval);
}
// AC vs DC mode SYSTEM register
if (link->ac_coupled)
{
//
// In NVL3.0, ACMODE is handled by MINION in the INITPHASE1 command
// Here we just setup the register with the proper info
//
NVSWITCH_PRINT(device, SETUP, "%s: AC_DC_MODE = 0x%x\n",
__FUNCTION__, DRF_VAL(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL,
_AC_DC_MODE, regval));
regval = FLD_SET_DRF(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL,
_AC_DC_MODE, _AC, regval);
}
else if (vbios_link_entry != NULL)
{
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _AC_DC_MODE,
DRF_VAL(_NVLINK_VBIOS, _PARAM0, _ACDC_MODE, vbios_link_entry->nvLinkparam0),
regval);
}
if (device->regkeys.block_code_mode != NV_SWITCH_REGKEY_BLOCK_CODE_MODE_DEFAULT)
{
NVSWITCH_PRINT(device, SETUP, "%s: BLOCK_CODE_MODE = 0x%x requested by regkey\n",
__FUNCTION__, device->regkeys.block_code_mode);
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL,
_BLOCK_CODE_MODE, device->regkeys.block_code_mode, regval);
}
else if (vbios_link_entry != NULL)
{
regval = FLD_SET_DRF_NUM(_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, _BLOCK_CODE_MODE,
DRF_VAL(_NVLINK_VBIOS, _PARAM3, _CLOCK_MODE_BLOCK_CODE, vbios_link_entry->nvLinkparam3),
regval);
}
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK_CTRL_SYSTEM_LINK, _CHANNEL_CTRL, regval);

16
src/common/nvswitch/kernel/lr10/lr10.c
View File

@@ -1112,7 +1112,6 @@ nvswitch_setup_system_registers_lr10
{
nvlink_link *link;
NvU8 i;
NvU32 val;
NvU64 enabledLinkMask;
enabledLinkMask = nvswitch_get_enabled_link_mask(device);
@@ -1130,21 +1129,6 @@ nvswitch_setup_system_registers_lr10
continue;
}
// AC vs DC mode SYSTEM register
if (link->ac_coupled)
{
//
// In NVL3.0, ACMODE is handled by MINION in the INITPHASE1 command
// Here we just setup the register with the proper info
//
val = NVSWITCH_LINK_RD32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL);
val = FLD_SET_DRF(_NVLIPT_LNK,
_CTRL_SYSTEM_LINK_CHANNEL_CTRL, _AC_DC_MODE, _AC, val);
NVSWITCH_LINK_WR32_LR10(device, link->linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _CTRL_SYSTEM_LINK_CHANNEL_CTRL, val);
}
nvswitch_setup_link_system_registers(device, link);
nvswitch_load_link_disable_settings(device, link);
}

7
src/common/nvswitch/kernel/lr10/smbpbi_lr10.c
View File

@@ -430,14 +430,15 @@ _makeNewRecord
pNewRec->recordSize = NV_UNSIGNED_DIV_CEIL(*pRecSize, sizeof(NvU32));
pNewRec->xidId = num;
pNewRec->seqNumber = pFifo->seqNumber++;
pNewRec->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC;
pNewRec->timeStamp = nvswitch_os_get_platform_time_epoch() / NVSWITCH_NSEC_PER_SEC;
if (msglen > NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE)
if (osErrorString[msglen - 1] != 0)
{
// The text string is too long. Truncate and notify the client.
osErrorString[msglen - 1] = 0;
pNewRec->flags = FLD_SET_DRF(_MSGBOX, _DEM_RECORD_FLAGS,
_TRUNC, _SET, pNewRec->flags);
msglen = NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE - 1;
msglen = NV_MSGBOX_MAX_DRIVER_EVENT_MSG_TXT_SIZE;
}
nvswitch_os_memcpy(pNewRec->textMessage, osErrorString, msglen);

131
src/common/nvswitch/kernel/ls10/flcn_ls10.c
View File

@@ -63,7 +63,7 @@ _flcnRiscvRegWrite_LS10
/*!
* @brief Retrieve the size of the falcon data memory.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] bFalconReachable If set, returns size that can be reached by Falcon
*
@@ -105,7 +105,7 @@ _flcnSetImemAddr_LS10
*
* @brief Copy contents of pSrc to IMEM
*
* @param[in] pGpu OBJGPU pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] dst Destination in IMEM
* @param[in] pSrc IMEM contents
@@ -156,7 +156,7 @@ _flcnSetDmemAddr_LS10
* Depending on the direction of the copy, copies 'sizeBytes' to/from 'pBuf'
* from/to DMEM offset 'dmemAddr' using DMEM access port 'port'.
*
* @param[in] pGpu GPU object pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] dmemAddr The DMEM offset for the copy
* @param[in] pBuf The pointer to the buffer containing the data to copy
@@ -280,6 +280,16 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
NvU32 ctl, ridx, widx, count, bufferSize;
NvBool full;
// Only supported on riscv
if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn))
{
NVSWITCH_PRINT(device, ERROR, "%s: is not supported on falcon\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
@@ -346,6 +356,115 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, ctl);
}
static NV_STATUS
_flcnDebugBufferInit_LS10
(
nvswitch_device *device,
PFLCN pFlcn,
NvU32 debugBufferMaxSize,
NvU32 writeRegAddr,
NvU32 readRegAddr
)
{
return NVL_SUCCESS;
}
static NV_STATUS
_flcnDebugBufferDestroy_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NVL_SUCCESS;
}
static NV_STATUS
_flcnDebugBufferDisplay_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NVL_SUCCESS;
}
static NvBool
_flcnDebugBufferIsEmpty_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NV_TRUE;
}
//
// Store pointers to ucode header and data.
// Preload ucode from registry if available.
//
NV_STATUS
_flcnConstruct_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
NV_STATUS status;
PFLCNABLE pFlcnable = pFlcn->pFlcnable;
PFALCON_QUEUE_INFO pQueueInfo;
pFlcn->bConstructed = NV_TRUE;
// Set arch to Riscv
pFlcn->engArch = NV_UPROC_ENGINE_ARCH_FALCON_RISCV;
// Allocate the memory for Queue Data Structure if needed.
if (pFlcn->bQueuesEnabled)
{
pQueueInfo = pFlcn->pQueueInfo = nvswitch_os_malloc(sizeof(*pQueueInfo));
if (pQueueInfo == NULL)
{
status = NV_ERR_NO_MEMORY;
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
nvswitch_os_memset(pQueueInfo, 0, sizeof(FALCON_QUEUE_INFO));
// Assert if Number of Queues are zero
NVSWITCH_ASSERT(pFlcn->numQueues != 0);
pQueueInfo->pQueues = nvswitch_os_malloc(sizeof(FLCNQUEUE) * pFlcn->numQueues);
if (pQueueInfo->pQueues == NULL)
{
status = NV_ERR_NO_MEMORY;
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
nvswitch_os_memset(pQueueInfo->pQueues, 0, sizeof(FLCNQUEUE) * pFlcn->numQueues);
// Sequences can be optional
if (pFlcn->numSequences != 0)
{
if ((pFlcn->numSequences - 1) > ((NvU32)NV_U8_MAX))
{
status = NV_ERR_OUT_OF_RANGE;
NVSWITCH_PRINT(device, ERROR,
"Max numSequences index = %d cannot fit into byte\n",
(pFlcn->numSequences - 1));
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
flcnQueueSeqInfoStateInit(device, pFlcn);
}
}
// DEBUG
NVSWITCH_PRINT(device, INFO, "Falcon: %s\n", flcnGetName_HAL(device, pFlcn));
NVSWITCH_ASSERT(pFlcnable != NULL);
flcnableGetExternalConfig(device, pFlcnable, &pFlcn->extConfig);
return NV_OK;
_flcnConstruct_LR10_fail:
// call flcnDestruct to free the memory allocated in this construct function
flcnDestruct_HAL(device, pFlcn);
return status;
}
/**
* @brief set hal function pointers for functions defined in
* LS10 (i.e. this file)
@@ -372,5 +491,9 @@ flcnSetupHal_LS10
pHal->setImemAddr = _flcnSetImemAddr_LS10;
pHal->dmemSize = _flcnDmemSize_LS10;
pHal->dbgInfoCaptureRiscvPcTrace = _flcnDbgInfoCaptureRiscvPcTrace_LS10;
pHal->debugBufferInit = _flcnDebugBufferInit_LS10;
pHal->debugBufferDestroy = _flcnDebugBufferDestroy_LS10;
pHal->debugBufferDisplay = _flcnDebugBufferDisplay_LS10;
pHal->debugBufferIsEmpty = _flcnDebugBufferIsEmpty_LS10;
pHal->construct = _flcnConstruct_LS10;
}

30
src/common/nvswitch/kernel/ls10/link_ls10.c
View File

@@ -34,6 +34,7 @@
#include "nvswitch/ls10/dev_nvlphyctl_ip.h"
#include "nvswitch/ls10/dev_nvltlc_ip.h"
#include "nvswitch/ls10/dev_minion_ip.h"
#include "nvswitch/ls10/dev_minion_ip_addendum.h"
#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h"
#include "nvswitch/ls10/dev_nvlipt_ip.h"
#include "nvswitch/ls10/dev_nport_ip.h"
@@ -502,27 +503,20 @@ nvswitch_reset_persistent_link_hw_state_ls10
NvU32 linkNumber
)
{
NvU32 regData;
NvU32 nvliptWarmResetDelayUs = (IS_RTLSIM(device) || IS_EMULATION(device)) ? 800:8;
nvlink_link *link = nvswitch_get_link(device, linkNumber);
if (nvswitch_is_link_in_reset(device, link))
{
return;
}
regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR);
regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT, regData);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR, regData);
// SETUPTC called with HW Reset
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_SETUPTC , 0x4);
NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR);
regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT, regData);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR, regData);
NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
// clear TLC TP Counters
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_CLR_TLC_MISC_REGS, 0);
// clear DL error counters
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT, 0);
}
NvlStatus

15
src/common/nvswitch/kernel/ls10/ls10.c
View File

@@ -124,25 +124,36 @@ nvswitch_pri_ring_init_ls10
while (keepPolling);
if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command))
{
NVSWITCH_RAW_ERROR_LOG_TYPE report = {0, { 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
NvU32 report_idx = 0;
NvU32 i;
report.data[report_idx++] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
__FUNCTION__, command);
for (i = 0; i <= 15; i++)
{
command = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SW_SCRATCH(i));
report_saw.data[i] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
__FUNCTION__, i, command);
}
for (i = 0; i <= 2; i++)
for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
{
command = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
report.data[report_idx++] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
__FUNCTION__, i, command);
}
// Include useful scratch information for triage
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE,
"Fatal, Firmware initialization failure (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
return -NVL_INITIALIZATION_TOTAL_FAILURE;
}

4
src/common/nvswitch/kernel/ls10/smbpbi_ls10.c
View File

@@ -25,6 +25,7 @@
#include "flcn/flcn_nvswitch.h"
#include "rmflcncmdif_nvswitch.h"
#include "lr10/smbpbi_lr10.h"
#include "nvVer.h"
NvlStatus
@@ -117,7 +118,7 @@ nvswitch_smbpbi_log_message_ls10
pLogCmd->sxidId = num;
pLogCmd->msgLen = msglen;
pLogCmd->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC;
pLogCmd->timeStamp = nvswitch_os_get_platform_time_epoch() / NVSWITCH_NSEC_PER_SEC;
for (offset = 0; msglen > 0; offset += segSize)
{
@@ -211,6 +212,7 @@ nvswitch_smbpbi_send_unload_ls10
nvswitch_device *device
)
{
nvswitch_smbpbi_send_unload_lr10(device);
}
void

22
src/common/nvswitch/kernel/ls10/soe_ls10.c
View File

@@ -428,7 +428,7 @@ nvswitch_init_soe_ls10
if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
"SOE init failed(4)\n");
status = -NVL_ERR_INVALID_STATE;
goto nvswitch_init_soe_fail;
}
@@ -465,6 +465,7 @@ nvswitch_unload_soe_ls10
// Detach driver from SOE Queues
_nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE);
return NVL_SUCCESS;
}
@@ -577,6 +578,7 @@ _soeService_LS10
)
{
NvBool bRecheckMsgQ = NV_FALSE;
NvBool bRecheckPrintQ = NV_FALSE;
NvU32 clearBits = 0;
NvU32 intrStatus;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
@@ -642,6 +644,8 @@ _soeService_LS10
NVSWITCH_PRINT(device, INFO,
"%s: Received a SWGEN1 interrupt\n",
__FUNCTION__);
flcnDebugBufferDisplay_HAL(device, pFlcn);
bRecheckPrintQ = NV_TRUE;
}
// Clear any sources that were serviced and get the new status.
@@ -677,6 +681,22 @@ _soeService_LS10
}
}
//
// If we just processed a SWGEN1 interrupt (Debug Buffer interrupt), peek
// into the Debug Buffer and see if any text was missed the last time
// the buffer was displayed (above). If it is not empty, re-generate SWGEN1
// (since it is now cleared) and exit. As long as an interrupt is pending,
// this function will be re-entered and the message(s) will be processed.
//
if (bRecheckPrintQ)
{
if (!flcnDebugBufferIsEmpty_HAL(device, pFlcn))
{
flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET,
DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN1, _SET));
}
}
flcnIntrRetrigger_HAL(device, pFlcn);
return intrStatus;

20
src/common/nvswitch/kernel/nvswitch.c
View File

@@ -535,6 +535,14 @@ _nvswitch_init_device_regkeys
NVSWITCH_INIT_REGKEY(_PUBLIC, minion_intr,
NV_SWITCH_REGKEY_MINION_INTERRUPTS,
NV_SWITCH_REGKEY_MINION_INTERRUPTS_DEFAULT);
NVSWITCH_INIT_REGKEY(_PRIVATE, block_code_mode,
NV_SWITCH_REGKEY_BLOCK_CODE_MODE,
NV_SWITCH_REGKEY_BLOCK_CODE_MODE_DEFAULT);
NVSWITCH_INIT_REGKEY(_PRIVATE, reference_clock_mode,
NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE,
NV_SWITCH_REGKEY_REFERENCE_CLOCK_MODE_DEFAULT);
}
NvU64
nvswitch_lib_deferred_task_dispatcher
@@ -4164,7 +4172,9 @@ nvswitch_lib_smbpbi_log_sxid
{
va_list arglist;
int msglen;
char string[RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING];
char string[RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING + 1];
nvswitch_os_memset(string, 0, (NvLength)sizeof(string));
va_start(arglist, pFormat);
msglen = nvswitch_os_vsnprintf(string, sizeof(string), pFormat, arglist);
@@ -4172,7 +4182,11 @@ nvswitch_lib_smbpbi_log_sxid
if (!(msglen < 0))
{
msglen = NV_MIN(msglen + 1, (int) sizeof(string));
//
// HALs will know that the string is being truncated by seeing that the
// last byte in the buffer is not nul.
//
msglen = NV_MIN(msglen + 1, (int)RM_SOE_SMBPBI_CMD_LOG_MESSAGE_MAX_STRING);
device->hal.nvswitch_smbpbi_log_message(device, sxid, msglen, (NvU8 *) string);
}
}
@@ -4858,7 +4872,7 @@ nvswitch_lib_ctrl
CTRL_NVSWITCH_RESERVED_2);
NVSWITCH_DEV_CMD_DISPATCH_RESERVED(
CTRL_NVSWITCH_RESERVED_3);
NVSWITCH_DEV_CMD_DISPATCH_RESERVED(
NVSWITCH_DEV_CMD_DISPATCH_RESERVED(
CTRL_NVSWITCH_RESERVED_4);
NVSWITCH_DEV_CMD_DISPATCH_RESERVED(
CTRL_NVSWITCH_RESERVED_5);

2
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080gpu.h
View File

@@ -2057,8 +2057,6 @@ typedef struct NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS {
NV2080_CTRL_GPU_BRIDGE_VERSION_PARAMS bridgeList[NV2080_CTRL_MAX_PHYSICAL_BRIDGE];
} NV2080_CTRL_GPU_GET_ALL_BRIDGES_UPSTREAM_OF_GPU_PARAMS;
/*
* NV2080_CTRL_CMD_GPU_QUERY_SCRUBBER_STATUS
*

23
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080nvlink.h
View File

@@ -2922,6 +2922,29 @@ typedef struct NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS {
#define NV2080_CTRL_CMD_NVLINK_IS_GPU_DEGRADED (0x20803040U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_IS_GPU_DEGRADED_PARAMS_MESSAGE_ID" */
/*
* NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK
*
* This command is used to check for missing
* bridge/nvlink for direct connect GPU
*
* [out] bIsEnoughNvLink
* Check if number of active nvlink meet the minimum requirements.
* [out] numBridge
* Number of NVLink bridge
* [out] bridgePresenceMask
* Bit mask of NVLink bridges's presence
*/
#define NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID (0x41U)
typedef struct NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS {
NvBool bIsEnoughNvLink;
NvU32 numBridge;
NvU32 bridgePresenceMask;
} NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS;
#define NV2080_CTRL_CMD_NVLINK_DIRECT_CONNECT_CHECK (0x20803041U) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_NVLINK_INTERFACE_ID << 8) | NV2080_CTRL_NVLINK_DIRECT_CONNECT_CHECK_PARAMS_MESSAGE_ID" */
/* _ctrl2080nvlink_h_ */

26
src/common/sdk/nvidia/inc/ctrl/ctrla080.h
View File

@@ -548,6 +548,11 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS {
* This parameter returns mask of UVM enabled features on vGPU. It comprises of
* UVM managed APIs and replayable faults that are enabled or disabled based on
* vGPU version.
* enableKmdSysmemScratch
* This parameter is used to overwrite guest regkey PreferSystemMemoryScratch.
* Setting vgpu parameter "vgpu_enable_kmd_sysmem_scratch" in plugin will
* set this parameter. If the parameter is set, guest moves shader buffer
* allocation from FB to sysmem.
*
* Possible status values returned are:
* NV_OK
@@ -632,19 +637,20 @@ typedef struct NVA080_CTRL_UPDATE_SYSMEM_BITMAP_PARAMS {
#define NVA080_CTRL_VGPU_GET_CONFIG_PARAMS_MESSAGE_ID (0x1U)
typedef struct NVA080_CTRL_VGPU_GET_CONFIG_PARAMS {
NvU32 frameRateLimiter;
NvU32 swVSyncEnabled;
NvU32 cudaEnabled;
NvU32 pluginPteBlitEnabled;
NvU32 disableWddm1xPreemption;
NvU32 debugBufferSize;
NvU32 frameRateLimiter;
NvU32 swVSyncEnabled;
NvU32 cudaEnabled;
NvU32 pluginPteBlitEnabled;
NvU32 disableWddm1xPreemption;
NvU32 debugBufferSize;
NV_DECLARE_ALIGNED(NvP64 debugBuffer, 8);
NV_DECLARE_ALIGNED(NvU64 guestFbOffset, 8);
NV_DECLARE_ALIGNED(NvU64 mappableCpuHostAperture, 8);
NvU32 linuxInterruptOptimization;
NvU32 vgpuDeviceCapsBits;
NvU32 maxPixels;
NvU32 uvmEnabledFeatures;
NvU32 linuxInterruptOptimization;
NvU32 vgpuDeviceCapsBits;
NvU32 maxPixels;
NvU32 uvmEnabledFeatures;
NvBool enableKmdSysmemScratch;
} NVA080_CTRL_VGPU_GET_CONFIG_PARAMS;

21
src/common/sdk/nvidia/inc/nverror.h
View File

@@ -195,6 +195,27 @@
(x - ROBUST_CHANNEL_NVENC1_ERROR + 1) : \
(x - ROBUST_CHANNEL_NVENC2_ERROR + 2)))
// Indexed NVJPG reference
#define ROBUST_CHANNEL_NVJPG_ERROR(x) \
((x < 1) ? \
(ROBUST_CHANNEL_NVJPG0_ERROR) : \
(ROBUST_CHANNEL_NVJPG1_ERROR + (x - 1)))
#define ROBUST_CHANNEL_IS_NVJPG_ERROR(x) \
((x == ROBUST_CHANNEL_NVJPG0_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG1_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG2_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG3_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG4_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG5_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG6_ERROR) || \
(x == ROBUST_CHANNEL_NVJPG7_ERROR))
#define ROBUST_CHANNEL_NVJPG_ERROR_IDX(x) \
((x == ROBUST_CHANNEL_NVJPG0_ERROR) ? \
(x - ROBUST_CHANNEL_NVJPG0_ERROR) : \
(x - ROBUST_CHANNEL_NVJPG1_ERROR + 1))
// Error Levels
#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_INFO (0)
#define ROBUST_CHANNEL_ERROR_RECOVERY_LEVEL_NON_FATAL (1)

53
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -2,58 +2,6 @@
* ################### THIS FILE IS AUTOGENERATED. DO NOT EDIT. ################### *
***********************************************************************************/
#ifdef __VGPU_SRIOV_ENABLED_SKUS__
static inline NvBool isSriovEnabledSKU(NvU16 devid, NvU16 ssid)
{
if (devid == 0x20B0)
return NV_TRUE;
if (devid == 0x20B2)
return NV_TRUE;
if ((devid == 0x20B5) && (ssid == 0x1533))
return NV_TRUE;
if ((devid == 0x20B7) && (ssid == 0x1532))
return NV_TRUE;
if (devid == 0x20BE)
return NV_TRUE;
if (devid == 0x20BF)
return NV_TRUE;
if (devid == 0x20F1)
return NV_TRUE;
if (devid == 0x20F3)
return NV_TRUE;
if (devid == 0x20F5)
return NV_TRUE;
if ((devid == 0x20F6) && (ssid == 0x17A3))
return NV_TRUE;
if (devid == 0x2230)
return NV_TRUE;
if (devid == 0x2231)
return NV_TRUE;
if ((devid == 0x2233) && (ssid == 0x165A))
return NV_TRUE;
if (devid == 0x2235)
return NV_TRUE;
if (devid == 0x2236)
return NV_TRUE;
if (devid == 0x2237)
return NV_TRUE;
if ((devid == 0x2238) && (ssid == 0x1677))
return NV_TRUE;
if ((devid == 0x2322) && (ssid == 0x17A4))
return NV_TRUE;
if ((devid == 0x2331) && (ssid == 0x1626))
return NV_TRUE;
if ((devid == 0x25B6) && (ssid == 0x14A9))
return NV_TRUE;
if ((devid == 0x25B6) && (ssid == 0x157E))
return NV_TRUE;
if ((devid == 0x20B8) && (ssid == 0x1581))
return NV_TRUE;
if ((devid == 0x20B9) && (ssid == 0x157F))
return NV_TRUE;
return NV_FALSE;
}
#endif //__VGPU_SRIOV_ENABLED_SKUS__
#ifdef __VGPU_ALIAS_PGPU_LIST__
static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
@@ -64,6 +12,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
NvU32 devid;
NvU32 subdevid;
} vgpu_aliases[] = {
{ 0x20B5, 0x1642, 0x20B5, 0x1533 },
{ 0x20B8, 0x1581, 0x20B5, 0x1533 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
};