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https://github.com/NVIDIA/open-gpu-kernel-modules.git
synced 2026-02-23 00:13:59 +00:00
525.60.11
This commit is contained in:
@@ -63,7 +63,7 @@ _flcnRiscvRegWrite_LS10
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/*!
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* @brief Retrieve the size of the falcon data memory.
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*
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* @param[in] pGpu OBJGPU pointer
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* @param[in] device nvswitch_device pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] bFalconReachable If set, returns size that can be reached by Falcon
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*
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@@ -105,7 +105,7 @@ _flcnSetImemAddr_LS10
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*
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* @brief Copy contents of pSrc to IMEM
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*
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* @param[in] pGpu OBJGPU pointer
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* @param[in] device nvswitch_device pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] dst Destination in IMEM
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* @param[in] pSrc IMEM contents
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@@ -156,7 +156,7 @@ _flcnSetDmemAddr_LS10
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* Depending on the direction of the copy, copies 'sizeBytes' to/from 'pBuf'
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* from/to DMEM offset 'dmemAddr' using DMEM access port 'port'.
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*
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* @param[in] pGpu GPU object pointer
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* @param[in] device nvswitch_device pointer
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* @param[in] pFlcn Falcon object pointer
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* @param[in] dmemAddr The DMEM offset for the copy
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* @param[in] pBuf The pointer to the buffer containing the data to copy
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@@ -280,6 +280,16 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
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NvU32 ctl, ridx, widx, count, bufferSize;
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NvBool full;
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// Only supported on riscv
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if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn))
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{
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NVSWITCH_PRINT(device, ERROR, "%s: is not supported on falcon\n",
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__FUNCTION__);
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NVSWITCH_ASSERT(0);
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return;
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}
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
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DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
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@@ -346,6 +356,115 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
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flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, ctl);
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}
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static NV_STATUS
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_flcnDebugBufferInit_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn,
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NvU32 debugBufferMaxSize,
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NvU32 writeRegAddr,
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NvU32 readRegAddr
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)
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{
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return NVL_SUCCESS;
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}
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static NV_STATUS
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_flcnDebugBufferDestroy_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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return NVL_SUCCESS;
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}
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static NV_STATUS
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_flcnDebugBufferDisplay_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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return NVL_SUCCESS;
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}
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static NvBool
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_flcnDebugBufferIsEmpty_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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return NV_TRUE;
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}
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//
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// Store pointers to ucode header and data.
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// Preload ucode from registry if available.
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//
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NV_STATUS
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_flcnConstruct_LS10
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(
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nvswitch_device *device,
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PFLCN pFlcn
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)
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{
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NV_STATUS status;
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PFLCNABLE pFlcnable = pFlcn->pFlcnable;
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PFALCON_QUEUE_INFO pQueueInfo;
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pFlcn->bConstructed = NV_TRUE;
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// Set arch to Riscv
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pFlcn->engArch = NV_UPROC_ENGINE_ARCH_FALCON_RISCV;
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// Allocate the memory for Queue Data Structure if needed.
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if (pFlcn->bQueuesEnabled)
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{
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pQueueInfo = pFlcn->pQueueInfo = nvswitch_os_malloc(sizeof(*pQueueInfo));
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if (pQueueInfo == NULL)
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{
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status = NV_ERR_NO_MEMORY;
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NVSWITCH_ASSERT(0);
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goto _flcnConstruct_LR10_fail;
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}
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nvswitch_os_memset(pQueueInfo, 0, sizeof(FALCON_QUEUE_INFO));
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// Assert if Number of Queues are zero
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NVSWITCH_ASSERT(pFlcn->numQueues != 0);
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pQueueInfo->pQueues = nvswitch_os_malloc(sizeof(FLCNQUEUE) * pFlcn->numQueues);
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if (pQueueInfo->pQueues == NULL)
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{
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status = NV_ERR_NO_MEMORY;
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NVSWITCH_ASSERT(0);
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goto _flcnConstruct_LR10_fail;
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}
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nvswitch_os_memset(pQueueInfo->pQueues, 0, sizeof(FLCNQUEUE) * pFlcn->numQueues);
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// Sequences can be optional
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if (pFlcn->numSequences != 0)
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{
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if ((pFlcn->numSequences - 1) > ((NvU32)NV_U8_MAX))
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{
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status = NV_ERR_OUT_OF_RANGE;
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NVSWITCH_PRINT(device, ERROR,
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"Max numSequences index = %d cannot fit into byte\n",
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(pFlcn->numSequences - 1));
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NVSWITCH_ASSERT(0);
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goto _flcnConstruct_LR10_fail;
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}
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flcnQueueSeqInfoStateInit(device, pFlcn);
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}
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}
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// DEBUG
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NVSWITCH_PRINT(device, INFO, "Falcon: %s\n", flcnGetName_HAL(device, pFlcn));
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NVSWITCH_ASSERT(pFlcnable != NULL);
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flcnableGetExternalConfig(device, pFlcnable, &pFlcn->extConfig);
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return NV_OK;
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_flcnConstruct_LR10_fail:
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// call flcnDestruct to free the memory allocated in this construct function
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flcnDestruct_HAL(device, pFlcn);
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return status;
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}
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/**
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* @brief set hal function pointers for functions defined in
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* LS10 (i.e. this file)
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@@ -372,5 +491,9 @@ flcnSetupHal_LS10
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pHal->setImemAddr = _flcnSetImemAddr_LS10;
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pHal->dmemSize = _flcnDmemSize_LS10;
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pHal->dbgInfoCaptureRiscvPcTrace = _flcnDbgInfoCaptureRiscvPcTrace_LS10;
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pHal->debugBufferInit = _flcnDebugBufferInit_LS10;
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pHal->debugBufferDestroy = _flcnDebugBufferDestroy_LS10;
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pHal->debugBufferDisplay = _flcnDebugBufferDisplay_LS10;
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pHal->debugBufferIsEmpty = _flcnDebugBufferIsEmpty_LS10;
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pHal->construct = _flcnConstruct_LS10;
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}
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@@ -34,6 +34,7 @@
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#include "nvswitch/ls10/dev_nvlphyctl_ip.h"
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#include "nvswitch/ls10/dev_nvltlc_ip.h"
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#include "nvswitch/ls10/dev_minion_ip.h"
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#include "nvswitch/ls10/dev_minion_ip_addendum.h"
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#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h"
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#include "nvswitch/ls10/dev_nvlipt_ip.h"
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#include "nvswitch/ls10/dev_nport_ip.h"
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@@ -502,27 +503,20 @@ nvswitch_reset_persistent_link_hw_state_ls10
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NvU32 linkNumber
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)
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{
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NvU32 regData;
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NvU32 nvliptWarmResetDelayUs = (IS_RTLSIM(device) || IS_EMULATION(device)) ? 800:8;
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nvlink_link *link = nvswitch_get_link(device, linkNumber);
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if (nvswitch_is_link_in_reset(device, link))
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{
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return;
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}
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regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
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_NVLIPT_LNK, _DEBUG_CLEAR);
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regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
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NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT, regData);
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
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_NVLIPT_LNK, _DEBUG_CLEAR, regData);
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// SETUPTC called with HW Reset
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(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_SETUPTC , 0x4);
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NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
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regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
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_NVLIPT_LNK, _DEBUG_CLEAR);
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regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
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NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT, regData);
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NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
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_NVLIPT_LNK, _DEBUG_CLEAR, regData);
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NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
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// clear TLC TP Counters
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(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_CLR_TLC_MISC_REGS, 0);
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// clear DL error counters
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(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT, 0);
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}
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NvlStatus
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@@ -124,25 +124,36 @@ nvswitch_pri_ring_init_ls10
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while (keepPolling);
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if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command))
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{
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NVSWITCH_RAW_ERROR_LOG_TYPE report = {0, { 0 }};
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NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
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NvU32 report_idx = 0;
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NvU32 i;
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report.data[report_idx++] = command;
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NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
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__FUNCTION__, command);
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for (i = 0; i <= 15; i++)
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{
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command = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SW_SCRATCH(i));
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report_saw.data[i] = command;
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NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
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__FUNCTION__, i, command);
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}
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for (i = 0; i <= 2; i++)
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for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
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{
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command = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
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NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
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report.data[report_idx++] = command;
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NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
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__FUNCTION__, i, command);
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}
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// Include useful scratch information for triage
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE,
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"Fatal, Firmware initialization failure (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
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report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
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report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
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return -NVL_INITIALIZATION_TOTAL_FAILURE;
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}
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@@ -25,6 +25,7 @@
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#include "flcn/flcn_nvswitch.h"
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#include "rmflcncmdif_nvswitch.h"
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#include "lr10/smbpbi_lr10.h"
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#include "nvVer.h"
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NvlStatus
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@@ -117,7 +118,7 @@ nvswitch_smbpbi_log_message_ls10
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pLogCmd->sxidId = num;
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pLogCmd->msgLen = msglen;
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pLogCmd->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC;
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pLogCmd->timeStamp = nvswitch_os_get_platform_time_epoch() / NVSWITCH_NSEC_PER_SEC;
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for (offset = 0; msglen > 0; offset += segSize)
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{
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@@ -211,6 +212,7 @@ nvswitch_smbpbi_send_unload_ls10
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nvswitch_device *device
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)
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{
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nvswitch_smbpbi_send_unload_lr10(device);
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}
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void
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@@ -428,7 +428,7 @@ nvswitch_init_soe_ls10
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if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
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{
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NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
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"SOE init failed(2)\n");
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"SOE init failed(4)\n");
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status = -NVL_ERR_INVALID_STATE;
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goto nvswitch_init_soe_fail;
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}
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@@ -465,6 +465,7 @@ nvswitch_unload_soe_ls10
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// Detach driver from SOE Queues
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_nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE);
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return NVL_SUCCESS;
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}
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@@ -577,6 +578,7 @@ _soeService_LS10
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)
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{
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NvBool bRecheckMsgQ = NV_FALSE;
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NvBool bRecheckPrintQ = NV_FALSE;
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NvU32 clearBits = 0;
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NvU32 intrStatus;
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PFLCN pFlcn = ENG_GET_FLCN(pSoe);
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@@ -642,6 +644,8 @@ _soeService_LS10
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NVSWITCH_PRINT(device, INFO,
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"%s: Received a SWGEN1 interrupt\n",
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__FUNCTION__);
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flcnDebugBufferDisplay_HAL(device, pFlcn);
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bRecheckPrintQ = NV_TRUE;
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}
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// Clear any sources that were serviced and get the new status.
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@@ -677,6 +681,22 @@ _soeService_LS10
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}
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}
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//
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// If we just processed a SWGEN1 interrupt (Debug Buffer interrupt), peek
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// into the Debug Buffer and see if any text was missed the last time
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// the buffer was displayed (above). If it is not empty, re-generate SWGEN1
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// (since it is now cleared) and exit. As long as an interrupt is pending,
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// this function will be re-entered and the message(s) will be processed.
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//
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if (bRecheckPrintQ)
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{
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if (!flcnDebugBufferIsEmpty_HAL(device, pFlcn))
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{
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flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET,
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DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN1, _SET));
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}
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}
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flcnIntrRetrigger_HAL(device, pFlcn);
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return intrStatus;
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