525.60.11

This commit is contained in:
Andy Ritger
2022-11-28 13:39:27 -08:00
parent 758b4ee818
commit 5f40a5aee5
113 changed files with 1408 additions and 723 deletions

View File

@@ -63,7 +63,7 @@ _flcnRiscvRegWrite_LS10
/*!
* @brief Retrieve the size of the falcon data memory.
*
* @param[in] pGpu OBJGPU pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] bFalconReachable If set, returns size that can be reached by Falcon
*
@@ -105,7 +105,7 @@ _flcnSetImemAddr_LS10
*
* @brief Copy contents of pSrc to IMEM
*
* @param[in] pGpu OBJGPU pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] dst Destination in IMEM
* @param[in] pSrc IMEM contents
@@ -156,7 +156,7 @@ _flcnSetDmemAddr_LS10
* Depending on the direction of the copy, copies 'sizeBytes' to/from 'pBuf'
* from/to DMEM offset 'dmemAddr' using DMEM access port 'port'.
*
* @param[in] pGpu GPU object pointer
* @param[in] device nvswitch_device pointer
* @param[in] pFlcn Falcon object pointer
* @param[in] dmemAddr The DMEM offset for the copy
* @param[in] pBuf The pointer to the buffer containing the data to copy
@@ -280,6 +280,16 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
NvU32 ctl, ridx, widx, count, bufferSize;
NvBool full;
// Only supported on riscv
if (!UPROC_ENG_ARCH_FALCON_RISCV(pFlcn))
{
NVSWITCH_PRINT(device, ERROR, "%s: is not supported on falcon\n",
__FUNCTION__);
NVSWITCH_ASSERT(0);
return;
}
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL,
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _MODE, _FULL) |
DRF_DEF(_PRISCV_RISCV, _TRACECTL, _UMODE_ENABLE, _TRUE) |
@@ -346,6 +356,115 @@ _flcnDbgInfoCaptureRiscvPcTrace_LS10
flcnRiscvRegWrite_HAL(device, pFlcn, NV_PRISCV_RISCV_TRACECTL, ctl);
}
static NV_STATUS
_flcnDebugBufferInit_LS10
(
nvswitch_device *device,
PFLCN pFlcn,
NvU32 debugBufferMaxSize,
NvU32 writeRegAddr,
NvU32 readRegAddr
)
{
return NVL_SUCCESS;
}
static NV_STATUS
_flcnDebugBufferDestroy_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NVL_SUCCESS;
}
static NV_STATUS
_flcnDebugBufferDisplay_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NVL_SUCCESS;
}
static NvBool
_flcnDebugBufferIsEmpty_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
return NV_TRUE;
}
//
// Store pointers to ucode header and data.
// Preload ucode from registry if available.
//
NV_STATUS
_flcnConstruct_LS10
(
nvswitch_device *device,
PFLCN pFlcn
)
{
NV_STATUS status;
PFLCNABLE pFlcnable = pFlcn->pFlcnable;
PFALCON_QUEUE_INFO pQueueInfo;
pFlcn->bConstructed = NV_TRUE;
// Set arch to Riscv
pFlcn->engArch = NV_UPROC_ENGINE_ARCH_FALCON_RISCV;
// Allocate the memory for Queue Data Structure if needed.
if (pFlcn->bQueuesEnabled)
{
pQueueInfo = pFlcn->pQueueInfo = nvswitch_os_malloc(sizeof(*pQueueInfo));
if (pQueueInfo == NULL)
{
status = NV_ERR_NO_MEMORY;
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
nvswitch_os_memset(pQueueInfo, 0, sizeof(FALCON_QUEUE_INFO));
// Assert if Number of Queues are zero
NVSWITCH_ASSERT(pFlcn->numQueues != 0);
pQueueInfo->pQueues = nvswitch_os_malloc(sizeof(FLCNQUEUE) * pFlcn->numQueues);
if (pQueueInfo->pQueues == NULL)
{
status = NV_ERR_NO_MEMORY;
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
nvswitch_os_memset(pQueueInfo->pQueues, 0, sizeof(FLCNQUEUE) * pFlcn->numQueues);
// Sequences can be optional
if (pFlcn->numSequences != 0)
{
if ((pFlcn->numSequences - 1) > ((NvU32)NV_U8_MAX))
{
status = NV_ERR_OUT_OF_RANGE;
NVSWITCH_PRINT(device, ERROR,
"Max numSequences index = %d cannot fit into byte\n",
(pFlcn->numSequences - 1));
NVSWITCH_ASSERT(0);
goto _flcnConstruct_LR10_fail;
}
flcnQueueSeqInfoStateInit(device, pFlcn);
}
}
// DEBUG
NVSWITCH_PRINT(device, INFO, "Falcon: %s\n", flcnGetName_HAL(device, pFlcn));
NVSWITCH_ASSERT(pFlcnable != NULL);
flcnableGetExternalConfig(device, pFlcnable, &pFlcn->extConfig);
return NV_OK;
_flcnConstruct_LR10_fail:
// call flcnDestruct to free the memory allocated in this construct function
flcnDestruct_HAL(device, pFlcn);
return status;
}
/**
* @brief set hal function pointers for functions defined in
* LS10 (i.e. this file)
@@ -372,5 +491,9 @@ flcnSetupHal_LS10
pHal->setImemAddr = _flcnSetImemAddr_LS10;
pHal->dmemSize = _flcnDmemSize_LS10;
pHal->dbgInfoCaptureRiscvPcTrace = _flcnDbgInfoCaptureRiscvPcTrace_LS10;
pHal->debugBufferInit = _flcnDebugBufferInit_LS10;
pHal->debugBufferDestroy = _flcnDebugBufferDestroy_LS10;
pHal->debugBufferDisplay = _flcnDebugBufferDisplay_LS10;
pHal->debugBufferIsEmpty = _flcnDebugBufferIsEmpty_LS10;
pHal->construct = _flcnConstruct_LS10;
}

View File

@@ -34,6 +34,7 @@
#include "nvswitch/ls10/dev_nvlphyctl_ip.h"
#include "nvswitch/ls10/dev_nvltlc_ip.h"
#include "nvswitch/ls10/dev_minion_ip.h"
#include "nvswitch/ls10/dev_minion_ip_addendum.h"
#include "nvswitch/ls10/dev_nvlipt_lnk_ip.h"
#include "nvswitch/ls10/dev_nvlipt_ip.h"
#include "nvswitch/ls10/dev_nport_ip.h"
@@ -502,27 +503,20 @@ nvswitch_reset_persistent_link_hw_state_ls10
NvU32 linkNumber
)
{
NvU32 regData;
NvU32 nvliptWarmResetDelayUs = (IS_RTLSIM(device) || IS_EMULATION(device)) ? 800:8;
nvlink_link *link = nvswitch_get_link(device, linkNumber);
if (nvswitch_is_link_in_reset(device, link))
{
return;
}
regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR);
regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_ASSERT, regData);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR, regData);
// SETUPTC called with HW Reset
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_SETUPTC , 0x4);
NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
regData = NVSWITCH_LINK_RD32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR);
regData = FLD_SET_DRF_NUM(_NVLIPT_LNK, _DEBUG_CLEAR, _CLEAR,
NV_NVLIPT_LNK_DEBUG_CLEAR_CLEAR_DEASSERT, regData);
NVSWITCH_LINK_WR32_LS10(device, linkNumber, NVLIPT_LNK,
_NVLIPT_LNK, _DEBUG_CLEAR, regData);
NVSWITCH_NSEC_DELAY(nvliptWarmResetDelayUs * NVSWITCH_INTERVAL_1USEC_IN_NS);
// clear TLC TP Counters
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_CLR_TLC_MISC_REGS, 0);
// clear DL error counters
(void)nvswitch_minion_send_command(device, linkNumber, NV_MINION_NVLINK_DL_CMD_COMMAND_DLSTAT_CLR_DLERRCNT, 0);
}
NvlStatus

View File

@@ -124,25 +124,36 @@ nvswitch_pri_ring_init_ls10
while (keepPolling);
if (!FLD_TEST_DRF(_GFW_GLOBAL, _BOOT_PARTITION_PROGRESS, _VALUE, _SUCCESS, command))
{
NVSWITCH_RAW_ERROR_LOG_TYPE report = {0, { 0 }};
NVSWITCH_RAW_ERROR_LOG_TYPE report_saw = {0, { 0 }};
NvU32 report_idx = 0;
NvU32 i;
report.data[report_idx++] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- _GFW_GLOBAL, _BOOT_PARTITION_PROGRESS (0x%x) != _SUCCESS --\n",
__FUNCTION__, command);
for (i = 0; i <= 15; i++)
{
command = NVSWITCH_SAW_RD32_LS10(device, _NVLSAW, _SW_SCRATCH(i));
report_saw.data[i] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_NVLSAW_SW_SCRATCH(%d) = 0x%08x\n",
__FUNCTION__, i, command);
}
for (i = 0; i <= 2; i++)
for (i = 0; i < NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1; i++)
{
command = NVSWITCH_REG_RD32(device, _PFSP, _FALCON_COMMON_SCRATCH_GROUP_2(i));
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
report.data[report_idx++] = command;
NVSWITCH_PRINT(device, ERROR, "%s: -- NV_PFSP_FALCON_COMMON_SCRATCH_GROUP_2(%d) = 0x%08x\n",
__FUNCTION__, i, command);
}
// Include useful scratch information for triage
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_HOST_FIRMWARE_INITIALIZATION_FAILURE,
"Fatal, Firmware initialization failure (0x%x/0x%x, 0x%x, 0x%x, 0x%x/0x%x, 0x%x, 0x%x, 0x%x, 0x%x\n",
report.data[0], report.data[1], report.data[2], report.data[3], report.data[4],
report_saw.data[0], report_saw.data[1], report_saw.data[12], report_saw.data[14], report_saw.data[15]);
return -NVL_INITIALIZATION_TOTAL_FAILURE;
}

View File

@@ -25,6 +25,7 @@
#include "flcn/flcn_nvswitch.h"
#include "rmflcncmdif_nvswitch.h"
#include "lr10/smbpbi_lr10.h"
#include "nvVer.h"
NvlStatus
@@ -117,7 +118,7 @@ nvswitch_smbpbi_log_message_ls10
pLogCmd->sxidId = num;
pLogCmd->msgLen = msglen;
pLogCmd->timeStamp = nvswitch_os_get_platform_time() / NVSWITCH_NSEC_PER_SEC;
pLogCmd->timeStamp = nvswitch_os_get_platform_time_epoch() / NVSWITCH_NSEC_PER_SEC;
for (offset = 0; msglen > 0; offset += segSize)
{
@@ -211,6 +212,7 @@ nvswitch_smbpbi_send_unload_ls10
nvswitch_device *device
)
{
nvswitch_smbpbi_send_unload_lr10(device);
}
void

View File

@@ -428,7 +428,7 @@ nvswitch_init_soe_ls10
if (_nvswitch_soe_send_test_cmd(device) != NV_OK)
{
NVSWITCH_PRINT_SXID(device, NVSWITCH_ERR_HW_SOE_BOOTSTRAP,
"SOE init failed(2)\n");
"SOE init failed(4)\n");
status = -NVL_ERR_INVALID_STATE;
goto nvswitch_init_soe_fail;
}
@@ -465,6 +465,7 @@ nvswitch_unload_soe_ls10
// Detach driver from SOE Queues
_nvswitch_soe_attach_detach_driver_ls10(device, NV_FALSE);
return NVL_SUCCESS;
}
@@ -577,6 +578,7 @@ _soeService_LS10
)
{
NvBool bRecheckMsgQ = NV_FALSE;
NvBool bRecheckPrintQ = NV_FALSE;
NvU32 clearBits = 0;
NvU32 intrStatus;
PFLCN pFlcn = ENG_GET_FLCN(pSoe);
@@ -642,6 +644,8 @@ _soeService_LS10
NVSWITCH_PRINT(device, INFO,
"%s: Received a SWGEN1 interrupt\n",
__FUNCTION__);
flcnDebugBufferDisplay_HAL(device, pFlcn);
bRecheckPrintQ = NV_TRUE;
}
// Clear any sources that were serviced and get the new status.
@@ -677,6 +681,22 @@ _soeService_LS10
}
}
//
// If we just processed a SWGEN1 interrupt (Debug Buffer interrupt), peek
// into the Debug Buffer and see if any text was missed the last time
// the buffer was displayed (above). If it is not empty, re-generate SWGEN1
// (since it is now cleared) and exit. As long as an interrupt is pending,
// this function will be re-entered and the message(s) will be processed.
//
if (bRecheckPrintQ)
{
if (!flcnDebugBufferIsEmpty_HAL(device, pFlcn))
{
flcnRegWrite_HAL(device, pFlcn, NV_PFALCON_FALCON_IRQSSET,
DRF_DEF(_PFALCON, _FALCON_IRQSSET, _SWGEN1, _SET));
}
}
flcnIntrRetrigger_HAL(device, pFlcn);
return intrStatus;