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580.82.07

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This commit is contained in:
Maneet Singh
2025-09-02 10:35:52 -07:00
parent 288f16e614
commit 6387af3092
67 changed files with 1665 additions and 838 deletions
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4
src/common/displayport/inc/dp_regkeydatabase.h
View File

@@ -47,7 +47,7 @@
#define NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES "APPLY_OVERRIDES_FOR_BUG_2489143"
#define NV_DP_REGKEY_DISABLE_DSC "DISABLE_DSC"
#define NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP "HP_WAR_2189772"
#define NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND "DP_HDCP_AUTH_ONLY_ON_DEMAND"
#define NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH "DP_MST_AUTO_HDCP_AUTH_AT_ATTACH"
#define NV_DP_REGKEY_ENABLE_MSA_OVER_MST "ENABLE_MSA_OVER_MST"
#define NV_DP_REGKEY_DISABLE_DOWNSPREAD "DISABLE_DOWNSPREAD"
@@ -126,7 +126,7 @@ struct DP_REGKEY_DATABASE
NvU32 applyMaxLinkRateOverrides;
bool bDscDisabled;
bool bAssesslinkForEdpSkipped;
bool bHdcpAuthOnlyOnDemand;
bool bMstAutoHdcpAuthAtAttach;
bool bMsaOverMstEnabled;
bool bOptLinkKeptAlive;
bool bOptLinkKeptAliveMst;

24
src/common/displayport/src/dp_connectorimpl.cpp
View File

@@ -52,13 +52,13 @@
#include "dp_tracing.h"
/*
* This is needed by Synaptics to disable DisplayExpand feature
* in some of their docking station based on if GPU supports DSC.
* This is needed by Synaptics to disable DisplayExpand feature
* in some of their docking station based on if GPU supports DSC.
* Feature is not needed if DSC is supported.
* Customers reported problems with the feature enabled on GB20x devices
* and requested GPU DSC detection to disable DisplayExpand feature.
* DSC is supported in Turing and later SKUs hence
* exposing Turing DevId to customers to address their requirement.
* exposing Turing DevId to customers to address their requirement.
*/
#define TURING_DEV_ID 0x1E
@@ -90,7 +90,7 @@ ConnectorImpl::ConnectorImpl(MainLink * main, AuxBus * auxBus, Timer * timer, Co
hdcpCpIrqRxStatusRetries(0),
bFromResumeToNAB(false),
bAttachOnResume(false),
bHdcpAuthOnlyOnDemand(false),
bHdcpAuthOnlyOnDemand(true),
constructorFailed(false),
policyModesetOrderMitigation(false),
policyForceLTAtNAB(false),
@@ -170,8 +170,8 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
this->bSkipAssessLinkForEDP = dpRegkeyDatabase.bAssesslinkForEdpSkipped;
// If Hdcp authenticatoin on demand regkey is set, override to the provided value.
this->bHdcpAuthOnlyOnDemand = dpRegkeyDatabase.bHdcpAuthOnlyOnDemand;
// default bHdcpAuthOnlyOnDemand is true and override to false if regkey bMstAutoHdcpAuthAtAttach set as true.
this->bHdcpAuthOnlyOnDemand = !dpRegkeyDatabase.bMstAutoHdcpAuthAtAttach;
if (dpRegkeyDatabase.bOptLinkKeptAlive)
{
@@ -5687,6 +5687,12 @@ bool ConnectorImpl::train(const LinkConfiguration & lConfig, bool force,
return false;
}
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
// active link training that violates spec.
//
cancelHdcpCallbacks();
if (!lConfig.multistream)
{
for (Device * i = enumDevices(0); i; i=enumDevices(i))
@@ -7428,6 +7434,12 @@ void ConnectorImpl::notifyShortPulse()
activeLinkConfig.peakRate > dp2LinkRate_10_0Gbps &&
main->isCableVconnSourceUnknown())
{
//
// Cancel pending HDCP authentication callbacks if have or may interrupt
// active link training that violates spec.
//
cancelHdcpCallbacks();
if (activeLinkConfig.isValid() && enableFlush())
{
train(originalActiveLinkConfig, true);

2
src/common/displayport/src/dp_evoadapter.cpp
View File

@@ -88,7 +88,7 @@ const struct
{NV_DP_REGKEY_APPLY_MAX_LINK_RATE_OVERRIDES, &dpRegkeyDatabase.applyMaxLinkRateOverrides, DP_REG_VAL_U32},
{NV_DP_REGKEY_DISABLE_DSC, &dpRegkeyDatabase.bDscDisabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_SKIP_ASSESSLINK_FOR_EDP, &dpRegkeyDatabase.bAssesslinkForEdpSkipped, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_HDCP_AUTH_ONLY_ON_DEMAND, &dpRegkeyDatabase.bHdcpAuthOnlyOnDemand, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_MST_AUTO_HDCP_AUTH_AT_ATTACH, &dpRegkeyDatabase.bMstAutoHdcpAuthAtAttach, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_ENABLE_MSA_OVER_MST, &dpRegkeyDatabase.bMsaOverMstEnabled, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE, &dpRegkeyDatabase.bOptLinkKeptAlive, DP_REG_VAL_BOOL},
{NV_DP_REGKEY_KEEP_OPT_LINK_ALIVE_MST, &dpRegkeyDatabase.bOptLinkKeptAliveMst, DP_REG_VAL_BOOL},

20
src/common/inc/nvBldVer.h
View File

@@ -36,25 +36,25 @@
// and then checked back in. You cannot make changes to these sections without
// corresponding changes to the buildmeister script
#ifndef NV_BUILD_BRANCH
#define NV_BUILD_BRANCH r580_92
#define NV_BUILD_BRANCH r581_07
#endif
#ifndef NV_PUBLIC_BRANCH
#define NV_PUBLIC_BRANCH r580_92
#define NV_PUBLIC_BRANCH r581_07
#endif
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r580_92-206"
#define NV_BUILD_CHANGELIST_NUM (36361462)
#define NV_BUILD_BRANCH_VERSION "rel/gpu_drv/r580/r581_07-226"
#define NV_BUILD_CHANGELIST_NUM (36455674)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "rel/gpu_drv/r580/r580_92-206"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36361462)
#define NV_BUILD_NAME "rel/gpu_drv/r580/r581_07-226"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36455674)
#else /* Windows builds */
#define NV_BUILD_BRANCH_VERSION "r580_92-5"
#define NV_BUILD_CHANGELIST_NUM (36361462)
#define NV_BUILD_BRANCH_VERSION "r581_07-4"
#define NV_BUILD_CHANGELIST_NUM (36452923)
#define NV_BUILD_TYPE "Official"
#define NV_BUILD_NAME "580.97"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36361462)
#define NV_BUILD_NAME "581.18"
#define NV_LAST_OFFICIAL_CHANGELIST_NUM (36452923)
#define NV_BUILD_BRANCH_BASE_VERSION R580
#endif
// End buildmeister python edited section

2
src/common/inc/nvUnixVersion.h
View File

@@ -4,7 +4,7 @@
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
#define NV_VERSION_STRING "580.76.05"
#define NV_VERSION_STRING "580.82.07"
#else

4
src/common/modeset/timing/nvt_edid.c
View File

@@ -1200,6 +1200,10 @@ NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID
getEdidHDM1_4bVsdbTiming(pInfo);
#if defined(NVT_USE_NVKMS)
prioritizeEdidHDMIExtTiming(pInfo);
#endif
// Assert if no timings were found (due to a bad EDID) or if we mistakenly
// assigned more timings than we allocated space for (due to bad logic above)
nvt_assert(pInfo->total_timings &&

237
src/common/modeset/timing/nvt_edidext_861.c
View File

@@ -1,6 +1,6 @@
//*****************************************************************************
//
// SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
// SPDX-License-Identifier: MIT
//
// Permission is hereby granted, free of charge, to any person obtaining a
@@ -2838,122 +2838,148 @@ NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, N
return NVT_STATUS_ERR;
}
if ((pCtrl->VSIFVersion != NVT_VSIF_VERSION_HF_VSIF) && (pCtrl->VSIFVersion != NVT_VSIF_VERSION_H14B_VSIF))
{
return NVT_STATUS_INVALID_PARAMETER;
}
// initialize the infoframe buffer
nvt_nvu8_set_bits(pInfoFrame->Header.type, NVT_HDMI_VS_HB0_VALUE, NVT_HDMI_VS_HB0_MASK, NVT_HDMI_VS_HB0_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Header.version, NVT_HDMI_VS_HB1_VALUE, NVT_HDMI_VS_HB1_MASK, NVT_HDMI_VS_HB1_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Header.length, NVT_HDMI_VS_HB2_VALUE, NVT_HDMI_VS_HB2_MASK, NVT_HDMI_VS_HB2_SHIFT);
if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_H14B_VSIF)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_1_4, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_1_4, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_1_4, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT);
}
else if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_HF_VSIF)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_2_0, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_2_0, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_2_0, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT);
}
// init the header (mostly done in default Infoframe)
pInfoFrame->Header.length = offsetof(NVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD, optionalBytes);
// construct the desired infoframe contents based on the control
// clear all static reserved fields
nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT);
// setup the parameters
nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT);
// determine what the format is -- if disabled, force the format to NONE.
if (pCtrl->Enable)
if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_HF_VSIF)
{
HDMIFormat = pCtrl->HDMIFormat;
}
else
{
HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE;
}
switch(HDMIFormat)
{
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE:
// infoframe is only supported on 861F and later
if (pEdidInfo->ext861.revision < NVT_CEA861_REV_F)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT);
break;
return NVT_STATUS_ERR;
}
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT:
{
// Note: extended resolution frames are not yet fully supported
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT);
break;
}
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D:
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT);
// side by side half requires additional format data in the infoframe.
if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc)
if (pCtrl->Enable && (pCtrl->HDMIFormat != NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE))
{
return NVT_STATUS_INVALID_PARAMETER;
}
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_2_0, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_2_0, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_2_0, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT);
// construct the desired HF-VSIF infoframe contents based on the control
nvt_nvu8_set_bits(pInfoFrame->Data.byte4, NVT_HDMI_HF_VS_BYTE4_VER_1_0, NVT_HDMI_HF_VS_BYTE4_VER_MASK, NVT_HDMI_HF_VS_BYTE4_VER_SHIFT);
if (pCtrl->Enable)
{
if (pCtrl->ALLMEnable == 1)
{
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT);
optIdx++;
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_EN, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT);
}
if (pCtrl->MetadataPresent)
else if (pCtrl->ALLMEnable == 0)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT);
}
}
else
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTENv_RSVD, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT);
}
}
else if (pCtrl->VSIFVersion == NVT_VSIF_VERSION_H14B_VSIF)
{
// construct the desired H14b-VSIF infoframe contents based on the control
switch(pCtrl->MetadataType)
nvt_nvu8_set_bits(pInfoFrame->Data.byte1, NVT_HDMI_VS_BYTE1_OUI_VER_1_4, NVT_HDMI_VS_BYTE1_OUI_MASK, NVT_HDMI_VS_BYTE1_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte2, NVT_HDMI_VS_BYTE2_OUI_VER_1_4, NVT_HDMI_VS_BYTE2_OUI_MASK, NVT_HDMI_VS_BYTE2_OUI_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte3, NVT_HDMI_VS_BYTE3_OUI_VER_1_4, NVT_HDMI_VS_BYTE3_OUI_MASK, NVT_HDMI_VS_BYTE3_OUI_SHIFT);
// clear all static reserved fields
nvt_nvu8_set_bits(pInfoFrame->Data.byte4, 0, NVT_HDMI_VS_BYTE4_RSVD_MASK, NVT_HDMI_VS_BYTE4_RSVD_SHIFT);
// setup the parameters
nvt_nvu8_set_bits(pInfoFrame->Data.byte4, pCtrl->HDMIFormat, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK, NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT);
// determine what the format is -- if disabled, force the format to NONE.
if (pCtrl->Enable)
{
HDMIFormat = pCtrl->HDMIFormat;
}
else
{
HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE;
}
switch(HDMIFormat)
{
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE:
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTENv_RSVD_MASK, NVT_HDMI_VS_BYTENv_RSVD_SHIFT);
break;
}
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT:
{
// Note: extended resolution frames are not yet fully supported
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->HDMI_VIC, NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK, NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT);
break;
}
case NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D:
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, 0, NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK, NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, pCtrl->ThreeDStruc, NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK, NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT);
// side by side half requires additional format data in the infoframe.
if (NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF == pCtrl->ThreeDStruc)
{
case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX:
{
if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX &&
sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX)
{
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT);
++optIdx;
NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX);
optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX;
}
else
{
// not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!!
// ignore metadata.
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
}
break;
}
default:
{
// unrecognised metadata, recover the best we can.
// note -- can not copy whatever is there because type implies length.
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
RetCode = NVT_STATUS_ERR;
}
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], pCtrl->ThreeDDetail, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK, NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT);
optIdx++;
}
if (pCtrl->MetadataPresent)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
switch(pCtrl->MetadataType)
{
case NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX:
{
if (sizeof(pCtrl->Metadata) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX &&
sizeof(pInfoFrame->Data.optionalBytes) - (optIdx + 1) >= NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX)
{
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT);
nvt_nvu8_set_bits(pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK, NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT);
++optIdx;
NVMISC_MEMCPY(pCtrl->Metadata, &pInfoFrame->Data.optionalBytes[optIdx], NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX);
optIdx += NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX;
}
else
{
// not enough data in the control struct or not enough room in the infoframe -- BOTH compile time issues!!
// ignore metadata.
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
}
break;
}
default:
{
// unrecognised metadata, recover the best we can.
// note -- can not copy whatever is there because type implies length.
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
RetCode = NVT_STATUS_ERR;
}
}
}
else
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
}
break;
}
else
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK, NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT);
}
break;
}
}
if (pCtrl->ALLMEnable == 1)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_EN, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT);
}
else if (pCtrl->ALLMEnable == 0)
{
nvt_nvu8_set_bits(pInfoFrame->Data.byte5, NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS, NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK, NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT);
}
// clear last byte of infoframe (reserved per spec).
@@ -3599,6 +3625,27 @@ void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pMapS
}
}
CODE_SEGMENT(PAGE_DD_CODE)
void prioritizeEdidHDMIExtTiming(NVT_EDID_INFO *pInfo)
{
NvU16 i, j;
nvt_assert(pInfo->total_timings <= COUNT(pInfo->timing));
for (i = 0; i < pInfo->total_timings; ++i)
{
if (NVT_GET_TIMING_STATUS_TYPE(pInfo->timing[i].etc.status) == NVT_TYPE_HDMI_EXT)
{
const NVT_TIMING extTimings = pInfo->timing[i];
for (j = i; j > 0; j--)
{
pInfo->timing[j] = pInfo->timing[j - 1];
}
pInfo->timing[0] = extTimings;
}
}
}
// get HDMI 1.4 3D mandatory stereo format datail base on the input vic.
// If the vic is not in the mandatory format list, return error.
CODE_SEGMENT(PAGE_DD_CODE)

5
src/common/modeset/timing/nvtiming.h
View File

@@ -3807,6 +3807,11 @@ typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME
#define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE 0x00
#define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT 0x01
#define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D 0x02
#define NVT_HDMI_HF_VS_BYTE4_VER_MASK 0xff
#define NVT_HDMI_HF_VS_BYTE4_VER_SHIFT 0x00
#define NVT_HDMI_HF_VS_BYTE4_VER_1_0 0x01
// 0x03-0x07 reserved
//
#define NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK 0xff // HDMI_VID_FMT = HDMI_VID_FMT_EXT

1
src/common/modeset/timing/nvtiming_pvt.h
View File

@@ -88,6 +88,7 @@ void parseEdidHdmiLlcBasicInfo(VSDB_DATA *pVsdb, NVT_HDMI_LLC_INFO *pHdmiL
void parseEdidHdmiForumVSDB(VSDB_DATA *pVsdb, NVT_HDMI_FORUM_INFO *pHdmiInfo);
void getEdidHDM1_4bVsdbTiming(NVT_EDID_INFO *pInfo);
void parseEdidHDMILLCTiming(NVT_EDID_INFO *pInfo, VSDB_DATA *pVsdb, NvU32 *pSupported, HDMI3DSUPPORTMAP * pM);
void prioritizeEdidHDMIExtTiming(NVT_EDID_INFO *pInfo);
void parseEdidNvidiaVSDBBlock(VSDB_DATA *pVsdb, NVDA_VSDB_PARSED_INFO *vsdbInfo);
void parseCta861HdrStaticMetadataDataBlock(NVT_EDID_CEA861_INFO *pExt861, void *pRawInfo, NVT_CTA861_ORIGIN flag);
void parseCta861DvStaticMetadataDataBlock(VSVDB_DATA* pVsvdb, NVT_DV_STATIC_METADATA* pDvInfo);

3
src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080fb.h
View File

@@ -364,8 +364,9 @@ typedef NVXXXX_CTRL_XXX_INFO NV2080_CTRL_FB_INFO;
#define NV2080_CTRL_FB_INFO_INDEX_LTC_MASK_1 (0x00000038U)
#define NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT (0x00000039U)
#define NV2080_CTRL_FB_INFO_INDEX_COHERENCE_INFO (0x0000003AU)
#define NV2080_CTRL_FB_INFO_INDEX_NUMA_NODE_ID (0x0000003BU)
#define NV2080_CTRL_FB_INFO_INDEX_MAX NV2080_CTRL_FB_INFO_INDEX_ACCESS_COUNTER_BUFFER_COUNT
#define NV2080_CTRL_FB_INFO_INDEX_MAX NV2080_CTRL_FB_INFO_INDEX_NUMA_NODE_ID
/* Intentionally picking a value much bigger than NV2080_CTRL_FB_INFO_INDEX_MAX to prevent VGPU plumbing updates */
#define NV2080_CTRL_FB_INFO_MAX_LIST_SIZE (0x00000080U)

19
src/common/shared/inc/g_vgpu_chip_flags.h
View File

@@ -621,6 +621,25 @@ ENTRY(0x2238, 0x16B8, 0x10de, "NVIDIA A10M-10C"),
ENTRY(0x2238, 0x16B9, 0x10de, "NVIDIA A10M-20C"),
ENTRY(0x2238, 0x16E6, 0x10de, "NVIDIA A10M-1"),
ENTRY(0x2238, 0x2208, 0x10de, "NVIDIA A10M-3B"),
ENTRY(0x230E, 0x20F5, 0x10de, "NVIDIA H20L-1-15CME"),
ENTRY(0x230E, 0x20F6, 0x10de, "NVIDIA H20L-1-15C"),
ENTRY(0x230E, 0x20F7, 0x10de, "NVIDIA H20L-1-30C"),
ENTRY(0x230E, 0x20F8, 0x10de, "NVIDIA H20L-2-30C"),
ENTRY(0x230E, 0x20F9, 0x10de, "NVIDIA H20L-3-60C"),
ENTRY(0x230E, 0x20FA, 0x10de, "NVIDIA H20L-4-60C"),
ENTRY(0x230E, 0x20FB, 0x10de, "NVIDIA H20L-7-120C"),
ENTRY(0x230E, 0x20FC, 0x10de, "NVIDIA H20L-4C"),
ENTRY(0x230E, 0x20FD, 0x10de, "NVIDIA H20L-5C"),
ENTRY(0x230E, 0x20FE, 0x10de, "NVIDIA H20L-6C"),
ENTRY(0x230E, 0x20FF, 0x10de, "NVIDIA H20L-8C"),
ENTRY(0x230E, 0x2100, 0x10de, "NVIDIA H20L-10C"),
ENTRY(0x230E, 0x2101, 0x10de, "NVIDIA H20L-12C"),
ENTRY(0x230E, 0x2102, 0x10de, "NVIDIA H20L-15C"),
ENTRY(0x230E, 0x2103, 0x10de, "NVIDIA H20L-20C"),
ENTRY(0x230E, 0x2104, 0x10de, "NVIDIA H20L-30C"),
ENTRY(0x230E, 0x2105, 0x10de, "NVIDIA H20L-40C"),
ENTRY(0x230E, 0x2106, 0x10de, "NVIDIA H20L-60C"),
ENTRY(0x230E, 0x2107, 0x10de, "NVIDIA H20L-120C"),
ENTRY(0x2321, 0x1853, 0x10de, "NVIDIA H100L-1-12CME"),
ENTRY(0x2321, 0x1854, 0x10de, "NVIDIA H100L-1-12C"),
ENTRY(0x2321, 0x1855, 0x10de, "NVIDIA H100L-1-24C"),

8
src/common/shared/inc/g_vgpu_resman_specific.h
View File

@@ -17,6 +17,7 @@ static inline void _get_chip_id_for_alias_pgpu(NvU32 *dev_id, NvU32 *subdev_id)
{ 0x20B7, 0x1804, 0x20B7, 0x1532 },
{ 0x20B9, 0x157F, 0x20B7, 0x1532 },
{ 0x20FD, 0x17F8, 0x20F5, 0x0 },
{ 0x230E, 0x20DF, 0x230E, 0x20DF },
{ 0x2324, 0x17A8, 0x2324, 0x17A6 },
{ 0x2329, 0x198C, 0x2329, 0x198B },
{ 0x232C, 0x2064, 0x232C, 0x2063 },
@@ -121,6 +122,13 @@ static const struct {
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1094}, // GRID A800-4-20C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1095}, // GRID A800-7-40C
{0x20F610DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1091}, // GRID A800-1-10C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1499}, // NVIDIA H20L-1-15CME
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1500}, // NVIDIA H20L-1-15C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1501}, // NVIDIA H20L-1-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_QUARTER_GPU , 1502}, // NVIDIA H20L-2-30C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_HALF_GPU , 1503}, // NVIDIA H20L-3-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_HALF_GPU , 1504}, // NVIDIA H20L-4-60C
{0x230E10DE, NV2080_CTRL_GPU_PARTITION_FLAG_FULL_GPU , 1505}, // NVIDIA H20L-7-120C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU | DRF_DEF(2080, _CTRL_GPU_PARTITION_FLAG, _REQ_DEC_JPG_OFA, _ENABLE), 1061}, // NVIDIA H100L-1-12CME
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_EIGHTHED_GPU , 1062}, // NVIDIA H100L-1-12C
{0x232110DE, NV2080_CTRL_GPU_PARTITION_FLAG_ONE_MINI_QUARTER_GPU , 1063}, // NVIDIA H100L-1-24C