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530.41.03

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This commit is contained in:
Andy Ritger
2023-03-23 11:00:12 -07:00
parent 4397463e73
commit 6dd092ddb7
63 changed files with 848 additions and 149 deletions
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5
src/nvidia/generated/g_mem_desc_nvoc.h
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@@ -344,6 +344,9 @@ typedef struct MEMORY_DESCRIPTOR
// Serve as a head node in a list of submemdescs
MEMORY_DESCRIPTOR_LIST *pSubMemDescList;
// Reserved for RM exclusive use
NvBool bRmExclusiveUse;
// If strung in a intrusive linked list
ListNode node;
@@ -653,6 +656,8 @@ NvBool memdescGetCustomHeap(PMEMORY_DESCRIPTOR);
// Temporary function for 64-bit pageSize transition
NvU64 memdescGetPageSize64(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRANSLATION addressTranslation);
NvBool memdescAcquireRmExclusiveUse(MEMORY_DESCRIPTOR *pMemDesc);
/*!
* @brief Get PTE kind
*

1
src/nvidia/generated/g_mem_mgr_nvoc.h
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@@ -481,7 +481,6 @@ struct MemoryManager {
NvU32 zbcSurfaces;
NvU64 overrideInitHeapMin;
NvU64 overrideHeapMax;
NvU64 fbOverrideStartKb;
NvU64 rsvdMemorySizeIncrement;
struct OBJFBSR *pFbsr[8];
struct OBJFBSR *pActiveFbsr;

19
src/nvidia/generated/g_nv_name_released.h
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@@ -884,9 +884,13 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2236, 0x1482, 0x10de, "NVIDIA A10" },
{ 0x2237, 0x152f, 0x10de, "NVIDIA A10G" },
{ 0x2238, 0x1677, 0x10de, "NVIDIA A10M" },
{ 0x2322, 0x17a4, 0x10de, "NVIDIA H800 PCIe" },
{ 0x2324, 0x17a6, 0x10de, "NVIDIA H800" },
{ 0x2324, 0x17a8, 0x10de, "NVIDIA H800" },
{ 0x2330, 0x16c0, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2330, 0x16c1, 0x10de, "NVIDIA H100 80GB HBM3" },
{ 0x2331, 0x1626, 0x10de, "NVIDIA H100 PCIe" },
{ 0x2339, 0x17fc, 0x10de, "NVIDIA H100" },
{ 0x2414, 0x0000, 0x0000, "NVIDIA GeForce RTX 3060 Ti" },
{ 0x2420, 0x0000, 0x0000, "NVIDIA GeForce RTX 3080 Ti Laptop GPU" },
{ 0x2438, 0x0000, 0x0000, "NVIDIA RTX A5500 Laptop GPU" },
@@ -973,11 +977,18 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B1, 0x16a1, 0x10de, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B1, 0x16a1, 0x17aa, "NVIDIA RTX 6000 Ada Generation" },
{ 0x26B5, 0x169d, 0x10de, "NVIDIA L40" },
{ 0x26B5, 0x17da, 0x10de, "NVIDIA L40" },
{ 0x2704, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080" },
{ 0x2717, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2757, 0x0000, 0x0000, "NVIDIA GeForce RTX 4090 Laptop GPU" },
{ 0x2782, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Ti" },
{ 0x27A0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x27B0, 0x16fa, 0x1028, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x103c, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x10de, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B0, 0x16fa, 0x17aa, "NVIDIA RTX 4000 SFF Ada Generation" },
{ 0x27B8, 0x16ca, 0x10de, "NVIDIA L4" },
{ 0x27B8, 0x16ee, 0x10de, "NVIDIA L4" },
{ 0x27E0, 0x0000, 0x0000, "NVIDIA GeForce RTX 4080 Laptop GPU" },
{ 0x2820, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
{ 0x2860, 0x0000, 0x0000, "NVIDIA GeForce RTX 4070 Laptop GPU" },
@@ -1236,6 +1247,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x1E37, 0x148a, 0x10DE, "GRID RTX T10-2" },
{ 0x1E37, 0x148b, 0x10DE, "GRID RTX T10-1" },
{ 0x1E37, 0x148c, 0x10DE, "GRID RTX T10-0" },
{ 0x1E37, 0x180d, 0x10DE, "NVIDIA GeForce GTX 1060" },
{ 0x1E37, 0x1820, 0x10DE, "GeForce RTX 2080" },
{ 0x1E78, 0x13f7, 0x10DE, "GRID RTX6000P-1B" },
{ 0x1E78, 0x13f8, 0x10DE, "GRID RTX6000P-2B" },
{ 0x1E78, 0x13f9, 0x10DE, "GRID RTX6000P-1Q" },
@@ -1523,6 +1536,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x2237, 0x1631, 0x10DE, "NVIDIA A10G-8Q" },
{ 0x2237, 0x1632, 0x10DE, "NVIDIA A10G-12Q" },
{ 0x2237, 0x1633, 0x10DE, "NVIDIA A10G-24Q" },
{ 0x2237, 0x1810, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x2237, 0x1811, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x2238, 0x16a3, 0x10DE, "NVIDIA A10M-1B" },
{ 0x2238, 0x16a4, 0x10DE, "NVIDIA A10M-2B" },
{ 0x2238, 0x16a5, 0x10DE, "NVIDIA A10M-1Q" },
@@ -1636,6 +1651,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B5, 0x1791, 0x10DE, "NVIDIA L40-16C" },
{ 0x26B5, 0x1792, 0x10DE, "NVIDIA L40-24C" },
{ 0x26B5, 0x1793, 0x10DE, "NVIDIA L40-48C" },
{ 0x26B5, 0x1818, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x26B5, 0x181a, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x26B8, 0x174e, 0x10DE, "NVIDIA L40G-1B" },
{ 0x26B8, 0x174f, 0x10DE, "NVIDIA L40G-2B" },
{ 0x26B8, 0x1750, 0x10DE, "NVIDIA L40G-1Q" },
@@ -1659,6 +1676,8 @@ static const CHIPS_RELEASED sChipsReleased[] = {
{ 0x26B8, 0x176a, 0x10DE, "NVIDIA L40G-8C" },
{ 0x26B8, 0x176b, 0x10DE, "NVIDIA L40G-12C" },
{ 0x26B8, 0x176c, 0x10DE, "NVIDIA L40G-24C" },
{ 0x26B8, 0x181c, 0x10DE, "NVIDIA GeForce RTX 3060" },
{ 0x26B8, 0x181e, 0x10DE, "NVIDIA GeForce RTX 3050" },
{ 0x27B8, 0x172f, 0x10DE, "NVIDIA L4-1B" },
{ 0x27B8, 0x1730, 0x10DE, "NVIDIA L4-2B" },
{ 0x27B8, 0x1731, 0x10DE, "NVIDIA L4-1Q" },

7
src/nvidia/generated/g_profiler_v2_nvoc.h
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@@ -115,6 +115,13 @@ struct ProfilerBase {
void (*__profilerBaseControlSerialization_Epilogue__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_RES_CONTROL_PARAMS_INTERNAL *);
NV_STATUS (*__profilerBaseMap__)(struct ProfilerBase *, struct CALL_CONTEXT *, struct RS_CPU_MAP_PARAMS *, struct RsCpuMapping *);
NvBool (*__profilerBaseAccessCallback__)(struct ProfilerBase *, struct RsClient *, void *, RsAccessRight);
NvU32 maxPmaChannels;
NvU32 pmaVchIdx;
NvBool bLegacyHwpm;
struct RsResourceRef **ppBytesAvailable;
struct RsResourceRef **ppStreamBuffers;
struct RsResourceRef *pBoundCntBuf;
struct RsResourceRef *pBoundPmaBuf;
};
#ifndef __NVOC_CLASS_ProfilerBase_TYPEDEF__

13
src/nvidia/generated/g_virt_mem_allocator_nvoc.h
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@@ -572,10 +572,15 @@ RmPhysAddr dmaPageArrayGetPhysAddr(DMA_PAGE_ARRAY *pPageArray, NvU32 pageIndex);
//
// hal.dmaAllocVASpace() flags
//
#define DMA_ALLOC_VASPACE_NONE 0
#define DMA_VA_LIMIT_49B NVBIT(0)
#define DMA_VA_LIMIT_57B NVBIT(1)
#define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9)
#define DMA_ALLOC_VASPACE_NONE 0
#define DMA_VA_LIMIT_49B NVBIT(0)
#define DMA_VA_LIMIT_57B NVBIT(1)
#define DMA_ALLOC_VASPACE_SIZE_ALIGNED NVBIT(9)
//
// Bug 3610538 For unlinked SLI, clients want to restrict internal buffers to
// Internal VA range, so that SLI vaspaces can mirror each other.
//
#define DMA_ALLOC_VASPACE_USE_RM_INTERNAL_VALIMITS NVBIT(10)
//
// Internal device allocation flags